introduce WED RX support to MT7986 SoC
Subsystems (5)
Lorenzo Bianconi
maintainerv2 cover introduce WED RX support to MT7986 SoC
Similar to TX counterpart available on MT7622 and MT7986, introduce RX Wireless Ethernet Dispatch available on MT7986 SoC in order to offload traffic received by wlan nic to the wired interfaces (lan/wan).
Changes since v1:
- fix sparse warnings
- rely on memory-region property in mt7622-wed.yaml
- some more binding fixes
Lorenzo Bianconi (6):
arm64: dts: mediatek: mt7986: add support for RX Wireless Ethernet
Dispatch
dt-bindings: net: mediatek: add WED RX binding for MT7986 eth driver
net: ethernet: mtk_wed: introduce wed mcu support
net: ethernet: mtk_wed: introduce wed wo support
net: ethernet: mtk_wed: add configure wed wo support
net: ethernet: mtk_wed: add rx mib counters
.../arm/mediatek/mediatek,mt7622-wed.yaml | 91 +++ .../arm/mediatek/mediatek,mt7986-wo-boot.yaml | 46 ++ .../arm/mediatek/mediatek,mt7986-wo-ccif.yaml | 49 ++ .../arm/mediatek/mediatek,mt7986-wo-dlm.yaml | 50 ++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 73 +++ drivers/net/ethernet/mediatek/Makefile | 2 +- drivers/net/ethernet/mediatek/mtk_wed.c | 577 ++++++++++++++++-- drivers/net/ethernet/mediatek/mtk_wed.h | 21 + .../net/ethernet/mediatek/mtk_wed_debugfs.c | 87 +++ drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 390 ++++++++++++ drivers/net/ethernet/mediatek/mtk_wed_regs.h | 129 +++- drivers/net/ethernet/mediatek/mtk_wed_wo.c | 545 +++++++++++++++++ drivers/net/ethernet/mediatek/mtk_wed_wo.h | 287 +++++++++ include/linux/soc/mediatek/mtk_wed.h | 104 +++- 14 files changed, 2407 insertions(+), 44 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_mcu.c create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_wo.c create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_wo.h
Signature · 1 line
2.37.3
Lorenzo Bianconi
maintainerPATCH v2 1/6 arm64: dts: mediatek: mt7986: add support for RX Wireless Ethernet Dispatch
Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet Dispatch to offload traffic received by the wlan interface to lan/wan one.
Co-developed-by Sujuan Chen <[email protected]>
Signed-off-by Sujuan Chen <[email protected]>
Signed-off-by Lorenzo Bianconi <[email protected]>
--- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 73 +++++++++++++++++++++++ 1 file changed, 73 insertions(+)
arch/arm64/boot/dts/mediatek/mt7986a.dtsi +73 -0
@@ -8,6 +8,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/mt7986-clk.h> #include <dt-bindings/reset/mt7986-resets.h> +#include <dt-bindings/reset/ti-syscon.h> / { interrupt-parent = <&gic>;
@@ -76,6 +77,31 @@ wmcpu_emi: wmcpu-reserved@4fc00000 { no-map; reg = <0 0x4fc00000 0 0x00100000>; }; + + wo_emi0: wo-emi0@4fd00000 { + reg = <0 0x4fd00000 0 0x40000>; + no-map; + }; + + wo_emi1: wo-emi1@4fd40000 { + reg = <0 0x4fd40000 0 0x40000>; + no-map; + }; + + wo_ilm0: wo-ilm0@151e0000 { + reg = <0 0x151e0000 0 0x8000>; + no-map; + }; + + wo_ilm1: wo-ilm1@151f0000 { + reg = <0 0x151f0000 0 0x8000>; + no-map; + }; + + wo_data: wo-data@4fd80000 { + reg = <0 0x4fd80000 0 0x240000>; + no-map; + }; }; timer {
@@ -226,6 +252,12 @@ ethsys: syscon@15000000 { reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + ethsysrst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; + }; }; wed_pcie: wed-pcie@10003000 {
@@ -240,6 +272,10 @@ wed0: wed@15010000 { reg = <0 0x15010000 0 0x1000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_data>; + mediatek,wo-ccif = <&wo_ccif0>; + mediatek,wo-dlm = <&wo_dlm0>; + mediatek,wo-boot = <&wo_boot>; }; wed1: wed@15011000 {
@@ -248,6 +284,43 @@ wed1: wed@15011000 { reg = <0 0x15011000 0 0x1000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_data>; + mediatek,wo-ccif = <&wo_ccif1>; + mediatek,wo-dlm = <&wo_dlm1>; + mediatek,wo-boot = <&wo_boot>; + }; + + wo_ccif0: wo-ccif1@151a5000 { + compatible = "mediatek,mt7986-wo-ccif","syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + }; + + wo_ccif1: wo-ccif1@151ad000 { + compatible = "mediatek,mt7986-wo-ccif","syscon"; + reg = <0 0x151ad000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + }; + + wo_dlm0: wo-dlm@151e8000 { + compatible = "mediatek,mt7986-wo-dlm"; + reg = <0 0x151e8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + }; + + wo_dlm1: wo-dlm@0x151f8000 { + compatible = "mediatek,mt7986-wo-dlm"; + reg = <0 0x151f8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + }; + + wo_boot: wo-boot@15194000 { + compatible = "mediatek,mt7986-wo-boot","syscon"; + reg = <0 0x15194000 0 0x1000>; }; eth: ethernet@15100000 {
Signature · 1 line
2.37.3
Re: [PATCH v2 net-next 1/6] arm64: dts: mediatek: mt7986: add support for RX Wireless Ethernet Dispatch
Quoted 3 lines · Lorenzo Bianconi
Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet Dispatch to offload traffic received by the wlan interface to lan/wan one.
Please use scripts/get_maintainers.pl to get a list of necessary people and lists to CC. It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel.
Quoted 77 lines
Co-developed-by Sujuan Chen <[email protected]>Signed-off-by Sujuan Chen <[email protected]>Signed-off-by Lorenzo Bianconi <[email protected]>--- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 73 +++++++++++++++++++++++ 1 file changed, 73 insertions(+)arch/arm64/boot/dts/mediatek/mt7986a.dtsi +36
-0@@ -8,6 +8,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/mt7986-clk.h> #include <dt-bindings/reset/mt7986-resets.h> +#include <dt-bindings/reset/ti-syscon.h> / { interrupt-parent = <&gic>;@@ -76,6 +77,31 @@ wmcpu_emi: wmcpu-reserved@4fc00000 { no-map; reg = <0 0x4fc00000 0 0x00100000>; }; + + wo_emi0: wo-emi0@4fd00000 { + reg = <0 0x4fd00000 0 0x40000>; + no-map; + }; + + wo_emi1: wo-emi1@4fd40000 { + reg = <0 0x4fd40000 0 0x40000>; + no-map; + }; + + wo_ilm0: wo-ilm0@151e0000 { + reg = <0 0x151e0000 0 0x8000>; + no-map; + }; + + wo_ilm1: wo-ilm1@151f0000 { + reg = <0 0x151f0000 0 0x8000>; + no-map; + }; + + wo_data: wo-data@4fd80000 { + reg = <0 0x4fd80000 0 0x240000>; + no-map; + }; }; timer {@@ -226,6 +252,12 @@ ethsys: syscon@15000000 { reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + ethsysrst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; + }; }; wed_pcie: wed-pcie@10003000 {@@ -240,6 +272,10 @@ wed0: wed@15010000 { reg = <0 0x15010000 0 0x1000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_data>; + mediatek,wo-ccif = <&wo_ccif0>; + mediatek,wo-dlm = <&wo_dlm0>; + mediatek,wo-boot = <&wo_boot>; }; wed1: wed@15011000 {
arch/arm64/boot/dts/mediatek/mt7986a.dtsi wed1: wed@15011000 { · line 293
Quoted 10 lines
arch/arm64/boot/dts/mediatek/mt7986a.dtsi +7
-0@@ -248,6 +284,43 @@ wed1: wed@15011000 { reg = <0 0x15011000 0 0x1000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_data>; + mediatek,wo-ccif = <&wo_ccif1>; + mediatek,wo-dlm = <&wo_dlm1>; + mediatek,wo-boot = <&wo_boot>; + }; + + wo_ccif0: wo-ccif1@151a5000 {
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
"1" suffix is for sure not generic. Neither wo-ccif is... unless there is some article on Wikipedia about it? Or maybe generic name is not possible to get, which happens...
Quoted 19 lines
arch/arm64/boot/dts/mediatek/mt7986a.dtsi +19
-0+ compatible = "mediatek,mt7986-wo-ccif","syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + }; + + wo_ccif1: wo-ccif1@151ad000 { + compatible = "mediatek,mt7986-wo-ccif","syscon"; + reg = <0 0x151ad000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + }; + + wo_dlm0: wo-dlm@151e8000 { + compatible = "mediatek,mt7986-wo-dlm"; + reg = <0 0x151e8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + };
arch/arm64/boot/dts/mediatek/mt7986a.dtsi wed1: wed@15011000 { · line 322
Quoted 10 lines
arch/arm64/boot/dts/mediatek/mt7986a.dtsi +10
-0+ + wo_dlm1: wo-dlm@0x151f8000 { + compatible = "mediatek,mt7986-wo-dlm"; + reg = <0 0x151f8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + }; + + wo_boot: wo-boot@15194000 { + compatible = "mediatek,mt7986-wo-boot","syscon";
Missing space.
arch/arm64/boot/dts/mediatek/mt7986a.dtsi wed1: wed@15011000 { · line 326
Quoted 4 lines
arch/arm64/boot/dts/mediatek/mt7986a.dtsi +1
-0+ reg = <0 0x15194000 0 0x1000>; }; eth: ethernet@15100000 {
Best regards,
Krzysztof
Lorenzo Bianconi
maintainerRe: [PATCH v2 net-next 1/6] arm64: dts: mediatek: mt7986: add support for RX Wireless Ethernet Dispatch
Quoted 9 lines · Lorenzo Bianconi
Quoted 3 lines
Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet Dispatch to offload traffic received by the wlan interface to lan/wan one.
Please use
scripts/get_maintainers.plto get a list of necessary people and lists to CC. It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel.
Hi Krzysztof,
Ack, sorry. I will do it in v3.
Quoted 92 lines
Quoted 78 lines
Co-developed-by Sujuan Chen <[email protected]>Signed-off-by Sujuan Chen <[email protected]>Signed-off-by Lorenzo Bianconi <[email protected]>--- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 73 +++++++++++++++++++++++ 1 file changed, 73 insertions(+)arch/arm64/boot/dts/mediatek/mt7986a.dtsi +36
-0@@ -8,6 +8,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/mt7986-clk.h> #include <dt-bindings/reset/mt7986-resets.h> +#include <dt-bindings/reset/ti-syscon.h> / { interrupt-parent = <&gic>;@@ -76,6 +77,31 @@ wmcpu_emi: wmcpu-reserved@4fc00000 { no-map; reg = <0 0x4fc00000 0 0x00100000>; }; + + wo_emi0: wo-emi0@4fd00000 { + reg = <0 0x4fd00000 0 0x40000>; + no-map; + }; + + wo_emi1: wo-emi1@4fd40000 { + reg = <0 0x4fd40000 0 0x40000>; + no-map; + }; + + wo_ilm0: wo-ilm0@151e0000 { + reg = <0 0x151e0000 0 0x8000>; + no-map; + }; + + wo_ilm1: wo-ilm1@151f0000 { + reg = <0 0x151f0000 0 0x8000>; + no-map; + }; + + wo_data: wo-data@4fd80000 { + reg = <0 0x4fd80000 0 0x240000>; + no-map; + }; }; timer {@@ -226,6 +252,12 @@ ethsys: syscon@15000000 { reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + ethsysrst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; + }; }; wed_pcie: wed-pcie@10003000 {@@ -240,6 +272,10 @@ wed0: wed@15010000 { reg = <0 0x15010000 0 0x1000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_data>; + mediatek,wo-ccif = <&wo_ccif0>; + mediatek,wo-dlm = <&wo_dlm0>; + mediatek,wo-boot = <&wo_boot>; }; wed1: wed@15011000 {arch/arm64/boot/dts/mediatek/mt7986a.dtsi wed1: wed@15011000 { · line 293
Quoted 10 lines
arch/arm64/boot/dts/mediatek/mt7986a.dtsi +7
-0@@ -248,6 +284,43 @@ wed1: wed@15011000 { reg = <0 0x15011000 0 0x1000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_data>; + mediatek,wo-ccif = <&wo_ccif1>; + mediatek,wo-dlm = <&wo_dlm1>; + mediatek,wo-boot = <&wo_boot>; + }; + + wo_ccif0: wo-ccif1@151a5000 {Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Quoted 3 lines
"1" suffix is for sure not generic. Neither wo-ccif is... unless there is some article on Wikipedia about it? Or maybe generic name is not possible to get, which happens...
I think we can use "syscon" for wo_ccif and wo_boot. I can't find a better name for wo_dlm since afaik it is a hw ring used for packet processing. What do you think?
Regards,
Lorenzo
Quoted 41 lines
Quoted 20 lines
arch/arm64/boot/dts/mediatek/mt7986a.dtsi +19
-0+ compatible = "mediatek,mt7986-wo-ccif","syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + }; + + wo_ccif1: wo-ccif1@151ad000 { + compatible = "mediatek,mt7986-wo-ccif","syscon"; + reg = <0 0x151ad000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + }; + + wo_dlm0: wo-dlm@151e8000 { + compatible = "mediatek,mt7986-wo-dlm"; + reg = <0 0x151e8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + };arch/arm64/boot/dts/mediatek/mt7986a.dtsi wed1: wed@15011000 { · line 322
Quoted 10 lines
arch/arm64/boot/dts/mediatek/mt7986a.dtsi +10
-0+ + wo_dlm1: wo-dlm@0x151f8000 { + compatible = "mediatek,mt7986-wo-dlm"; + reg = <0 0x151f8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + }; + + wo_boot: wo-boot@15194000 { + compatible = "mediatek,mt7986-wo-boot","syscon";Missing space.
arch/arm64/boot/dts/mediatek/mt7986a.dtsi wed1: wed@15011000 { · line 326
Quoted 4 lines
arch/arm64/boot/dts/mediatek/mt7986a.dtsi +1
-0+ reg = <0 0x15194000 0 0x1000>; }; eth: ethernet@15100000 {Best regards,
Krzysztof
Lorenzo Bianconi
maintainerPATCH v2 2/6 dt-bindings: net: mediatek: add WED RX binding for MT7986 eth driver
In reply to Lorenzo BianconiDocument the binding for the RX Wireless Ethernet Dispatch core on the MT7986 ethernet driver used to offload traffic received by WLAN NIC and forwarded to LAN/WAN one.
Signed-off-by Lorenzo Bianconi <[email protected]>
--- .../arm/mediatek/mediatek,mt7622-wed.yaml | 91 +++++++++++++++++++ .../arm/mediatek/mediatek,mt7986-wo-boot.yaml | 46 ++++++++++ .../arm/mediatek/mediatek,mt7986-wo-ccif.yaml | 49 ++++++++++ .../arm/mediatek/mediatek,mt7986-wo-dlm.yaml | 50 ++++++++++ 4 files changed, 236 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +91 -0
@@ -29,6 +29,41 @@ properties: interrupts: maxItems: 1 + memory-region: + minItems: 3 + maxItems: 3 + description: + phandles to nodes describing reserved memory used by mt7986-wed firmware + (see bindings/reserved-memory/reserved-memory.txt) + + mediatek,wo-ccif: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek wed-wo controller. + + mediatek,wo-boot: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek wed-wo boot interface. + + mediatek,wo-dlm: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek wed-wo rx hw ring. + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt7986-wed + then: + properties: + mediatek,wo-boot: true + mediatek,wo-ccif: true + mediatek,wo-dlm: true + memory-region: true + required: - compatible - reg
@@ -49,3 +84,59 @@ examples: interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>; }; }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + wo_emi: wo-emi@4fd00000 { + reg = <0 0x4fd00000 0 0x40000>; + no-map; + }; + + wo_data: wo-data@4fd80000 { + reg = <0 0x4fd80000 0 0x240000>; + no-map; + }; + + wo_ilm: wo-ilm@151e0000 { + reg = <0 0x151e0000 0 0x8000>; + no-map; + }; + }; + + wo_boot: wo-boot@15194000 { + compatible = "mediatek,mt7986-wo-boot","syscon"; + reg = <0 0x15194000 0 0x1000>; + }; + + wo_ccif0: wo-ccif@151a5000 { + compatible = "mediatek,mt7986-wo-ccif","syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + }; + + wo_dlm0: wo-dlm@151e8000 { + compatible = "mediatek,mt7986-wo-dlm"; + reg = <0 0x151e8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + }; + + wed1: wed@1020a000 { + compatible = "mediatek,mt7986-wed","syscon"; + reg = <0 0x15010000 0 0x1000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + + memory-region = <&wo_emi>, <&wo_data>, <&wo_ilm>; + mediatek,wo-ccif = <&wo_ccif0>; + mediatek,wo-boot = <&wo_boot>; + mediatek,wo-dlm = <&wo_dlm0>; + }; + };
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +46 -0
46 lines not on this page · raw message
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +49 -0
49 lines not on this page · raw message
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file +50 -0
50 lines not on this page · raw message
Signature · 1 line
2.37.3
Rob Herring
maintainerRe: [PATCH v2 net-next 2/6] dt-bindings: net: mediatek: add WED RX binding for MT7986 eth driver
Quoted 20 lines · Lorenzo Bianconi
Document the binding for the RX Wireless Ethernet Dispatch core on the MT7986 ethernet driver used to offload traffic received by WLAN NIC and forwarded to LAN/WAN one.
Signed-off-by Lorenzo Bianconi <[email protected]>--- .../arm/mediatek/mediatek,mt7622-wed.yaml | 91 +++++++++++++++++++ .../arm/mediatek/mediatek,mt7986-wo-boot.yaml | 46 ++++++++++ .../arm/mediatek/mediatek,mt7986-wo-ccif.yaml | 49 ++++++++++ .../arm/mediatek/mediatek,mt7986-wo-dlm.yaml | 50 ++++++++++ 4 files changed, 236 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yamlDocumentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +0
-0
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml properties: · line 34
Quoted 6 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +3
-0@@ -29,6 +29,41 @@ properties: interrupts: maxItems: 1 + memory-region: + minItems: 3 + maxItems: 3
What is each entry? Need to define them.
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml properties: · line 37
Quoted 3 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +3
-0+ description: + phandles to nodes describing reserved memory used by mt7986-wed firmware + (see bindings/reserved-memory/reserved-memory.txt)
What does that document say?
(You don't need generic descriptions/refs of common properties)
Quoted 18 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +18
-0+ + mediatek,wo-ccif: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek wed-wo controller. + + mediatek,wo-boot: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek wed-wo boot interface. + + mediatek,wo-dlm: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek wed-wo rx hw ring. + +allOf: + - if:
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml properties: · line 65
Quoted 10 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +10
-0+ properties: + compatible: + contains: + const: mediatek,mt7986-wed + then: + properties: + mediatek,wo-boot: true + mediatek,wo-ccif: true + mediatek,wo-dlm: true + memory-region: true
This does nothing. You need the opposite? Disallow these properties for 7622?
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml examples: · line 88
Quoted 10 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +3
-0+ required: - compatible - reg@@ -49,3 +84,59 @@ examples: interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>; }; }; + + - |
Why a new example?
Quoted 14 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +14
-0+ #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + wo_emi: wo-emi@4fd00000 { + reg = <0 0x4fd00000 0 0x40000>; + no-map; + }; +
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml examples: · line 112
Quoted 10 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +10
-0+ wo_data: wo-data@4fd80000 { + reg = <0 0x4fd80000 0 0x240000>; + no-map; + }; + + wo_ilm: wo-ilm@151e0000 { + reg = <0 0x151e0000 0 0x8000>; + no-map; + }; + };
Don't need to show /reserved-memory in examples.
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml examples: · line 123
Quoted 11 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +11
-0+ + wo_boot: wo-boot@15194000 { + compatible = "mediatek,mt7986-wo-boot","syscon"; + reg = <0 0x15194000 0 0x1000>; + }; + + wo_ccif0: wo-ccif@151a5000 { + compatible = "mediatek,mt7986-wo-ccif","syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + };
Don't really need to show these either. You already have them in their own schemas and we don't need 2 examples.
Didn't I already say this?
Quoted 186 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +19
-0+ + wo_dlm0: wo-dlm@151e8000 { + compatible = "mediatek,mt7986-wo-dlm"; + reg = <0 0x151e8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + }; + + wed1: wed@1020a000 { + compatible = "mediatek,mt7986-wed","syscon"; + reg = <0 0x15010000 0 0x1000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + + memory-region = <&wo_emi>, <&wo_data>, <&wo_ilm>; + mediatek,wo-ccif = <&wo_ccif0>; + mediatek,wo-boot = <&wo_boot>; + mediatek,wo-dlm = <&wo_dlm0>; + }; + };Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +46
-0@@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-boot.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: + MediaTek Wireless Ethernet Dispatch WO boot controller interface for MT7986 + +maintainers: + - Lorenzo Bianconi <[email protected]> + - Felix Fietkau <[email protected]> + +description: + The mediatek wo-boot provides a configuration interface for WED WO + boot controller on MT7986 soc. + +properties: + compatible: + items: + - enum: + - mediatek,mt7986-wo-boot + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + wo_boot: wo-boot@15194000 { + compatible = "mediatek,mt7986-wo-boot","syscon"; + reg = <0 0x15194000 0 0x1000>; + }; + };Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +49
-0@@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-ccif.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Wireless Ethernet Dispatch WO Controller for MT7986 + +maintainers: + - Lorenzo Bianconi <[email protected]> + - Felix Fietkau <[email protected]> + +description: + The mediatek wo-ccif provides a configuration interface for WED WO + controller on MT7986 soc. + +properties: + compatible: + items: + - enum: + - mediatek,mt7986-wo-ccif + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + wo_ccif0: wo-ccif@151a5000 { + compatible = "mediatek,mt7986-wo-ccif","syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + }; + };Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file +50
-0@@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-dlm.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Wireless Ethernet Dispatch WO hw rx ring interface for MT7986 + +maintainers: + - Lorenzo Bianconi <[email protected]> + - Felix Fietkau <[email protected]> + +description: + The mediatek wo-dlm provides a configuration interface for WED WO + rx ring on MT7986 soc. + +properties: + compatible: + const: mediatek,mt7986-wo-dlm + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + maxItems: 1 + +required: + - compatible + - reg + - resets + - reset-names + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + wo_dlm0: wo-dlm@151e8000 { + compatible = "mediatek,mt7986-wo-dlm"; + reg = <0 0x151e8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + }; + };Signature · 1 line
2.37.3
Lorenzo Bianconi
maintainerRe: [PATCH v2 net-next 2/6] dt-bindings: net: mediatek: add WED RX binding for MT7986 eth driver
Quoted 24 lines · Lorenzo Bianconi
Quoted 23 lines
Document the binding for the RX Wireless Ethernet Dispatch core on the MT7986 ethernet driver used to offload traffic received by WLAN NIC and forwarded to LAN/WAN one.
Signed-off-by Lorenzo Bianconi <[email protected]>--- .../arm/mediatek/mediatek,mt7622-wed.yaml | 91 +++++++++++++++++++ .../arm/mediatek/mediatek,mt7986-wo-boot.yaml | 46 ++++++++++ .../arm/mediatek/mediatek,mt7986-wo-ccif.yaml | 49 ++++++++++ .../arm/mediatek/mediatek,mt7986-wo-dlm.yaml | 50 ++++++++++ 4 files changed, 236 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yamlDocumentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +0
-0@@ -29,6 +29,41 @@ properties: interrupts: maxItems: 1
Quoted 5 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml properties: · line 34
Quoted 3 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +3
-0+ memory-region: + minItems: 3 + maxItems: 3What is each entry? Need to define them.
Is something like the chunk below works for you?
....
memory-region:
items:
- description:
Phandle for the node (wo-emi) used to run firmware EMI region
- description:
Phandle for the node (wo-ilm) used to run firmware ILM region
- description:
Phandle for the node (wo-data) used to run firmware CPU DATA region
memory-region-names:
items:
- const: wo-emi
- const: wo-ilm
- const: wo-data
....
Quoted 8 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml properties: · line 37
Quoted 4 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +3
-0+ description: + phandles to nodes describing reserved memory used by mt7986-wed firmware + (see bindings/reserved-memory/reserved-memory.txt)What does that document say?
(You don't need generic descriptions/refs of common properties)
I used some other bindings as reference (e.g. ti,k3-dsp-rproc.yaml) and I have not checked the document. I will drop it in v3.
Quoted 24 lines
Quoted 24 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +23
-0+ + mediatek,wo-ccif: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek wed-wo controller. + + mediatek,wo-boot: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek wed-wo boot interface. + + mediatek,wo-dlm: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek wed-wo rx hw ring. + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt7986-wed + then:
Quoted 8 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml properties: · line 65
Quoted 5 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +5
-0+ properties: + mediatek,wo-boot: true + mediatek,wo-ccif: true + mediatek,wo-dlm: true + memory-region: trueThis does nothing. You need the opposite? Disallow these properties for 7622?
ack, I will fix in v3.
Quoted 13 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml examples: · line 88
Quoted 11 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +3
-0+ required: - compatible - reg@@ -49,3 +84,59 @@ examples: interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>; }; }; + + - |Why a new example?
do you mean to drop mt7986-wed example or squash it with mt7622-wed one? Something like:
wed0: wed@1020a000 {
compatible = "mediatek,mt7622-wed","syscon";
....
};wed1: wed@15011000 {
compatible = "mediatek,mt7986-wed","syscon";
....
};Quoted 21 lines
Quoted 21 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +19
-0+ wed1: wed@1020a000 { + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + wo_emi: wo-emi@4fd00000 { + reg = <0 0x4fd00000 0 0x40000>; + no-map; + }; + + wo_data: wo-data@4fd80000 { + reg = <0 0x4fd80000 0 0x240000>; + no-map; + };
Quoted 8 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml examples: · line 112
Quoted 6 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +6
-0+ + wo_ilm: wo-ilm@151e0000 { + reg = <0 0x151e0000 0 0x8000>; + no-map; + }; + };Don't need to show /reserved-memory in examples.
ack, I will fix it in v3.
Quoted 16 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml examples: · line 123
Quoted 12 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +11
-0+ + wo_boot: wo-boot@15194000 { + compatible = "mediatek,mt7986-wo-boot","syscon"; + reg = <0 0x15194000 0 0x1000>; + }; + + wo_ccif0: wo-ccif@151a5000 { + compatible = "mediatek,mt7986-wo-ccif","syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + };Don't really need to show these either. You already have them in their own schemas and we don't need 2 examples.
Quoted 1 line
Didn't I already say this?
sorry, I missed it. I will fix it in v3.
Regards,
Lorenzo
Quoted 187 lines
Quoted 187 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +19
-0+ + wo_dlm0: wo-dlm@151e8000 { + compatible = "mediatek,mt7986-wo-dlm"; + reg = <0 0x151e8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + }; + + wed1: wed@1020a000 { + compatible = "mediatek,mt7986-wed","syscon"; + reg = <0 0x15010000 0 0x1000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + + memory-region = <&wo_emi>, <&wo_data>, <&wo_ilm>; + mediatek,wo-ccif = <&wo_ccif0>; + mediatek,wo-boot = <&wo_boot>; + mediatek,wo-dlm = <&wo_dlm0>; + }; + };Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +46
-0@@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-boot.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: + MediaTek Wireless Ethernet Dispatch WO boot controller interface for MT7986 + +maintainers: + - Lorenzo Bianconi <[email protected]> + - Felix Fietkau <[email protected]> + +description: + The mediatek wo-boot provides a configuration interface for WED WO + boot controller on MT7986 soc. + +properties: + compatible: + items: + - enum: + - mediatek,mt7986-wo-boot + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + wo_boot: wo-boot@15194000 { + compatible = "mediatek,mt7986-wo-boot","syscon"; + reg = <0 0x15194000 0 0x1000>; + }; + };Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +49
-0@@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-ccif.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Wireless Ethernet Dispatch WO Controller for MT7986 + +maintainers: + - Lorenzo Bianconi <[email protected]> + - Felix Fietkau <[email protected]> + +description: + The mediatek wo-ccif provides a configuration interface for WED WO + controller on MT7986 soc. + +properties: + compatible: + items: + - enum: + - mediatek,mt7986-wo-ccif + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + wo_ccif0: wo-ccif@151a5000 { + compatible = "mediatek,mt7986-wo-ccif","syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + }; + };Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file +50
-0@@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-dlm.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Wireless Ethernet Dispatch WO hw rx ring interface for MT7986 + +maintainers: + - Lorenzo Bianconi <[email protected]> + - Felix Fietkau <[email protected]> + +description: + The mediatek wo-dlm provides a configuration interface for WED WO + rx ring on MT7986 soc. + +properties: + compatible: + const: mediatek,mt7986-wo-dlm + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + maxItems: 1 + +required: + - compatible + - reg + - resets + - reset-names + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + wo_dlm0: wo-dlm@151e8000 { + compatible = "mediatek,mt7986-wo-dlm"; + reg = <0 0x151e8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + }; + };Signature · 1 line
2.37.3
Re: [PATCH v2 net-next 2/6] dt-bindings: net: mediatek: add WED RX binding for MT7986 eth driver
In reply to Lorenzo BianconiQuoted 5 lines · Lorenzo Bianconi
Document the binding for the RX Wireless Ethernet Dispatch core on the MT7986 ethernet driver used to offload traffic received by WLAN NIC and forwarded to LAN/WAN one.
Signed-off-by Lorenzo Bianconi <[email protected]>
Please use scripts/get_maintainers.pl to get a list of necessary people and lists to CC. It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel.
Quoted 15 lines
--- .../arm/mediatek/mediatek,mt7622-wed.yaml | 91 +++++++++++++++++++ .../arm/mediatek/mediatek,mt7986-wo-boot.yaml | 46 ++++++++++ .../arm/mediatek/mediatek,mt7986-wo-ccif.yaml | 49 ++++++++++ .../arm/mediatek/mediatek,mt7986-wo-dlm.yaml | 50 ++++++++++ 4 files changed, 236 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yamlDocumentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +0
-0
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml properties: · line 33
Quoted 5 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +2
-0@@ -29,6 +29,41 @@ properties: interrupts: maxItems: 1 + memory-region: + minItems: 3
No need for minItems.
Quoted 154 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +89
-0+ maxItems: 3 + description: + phandles to nodes describing reserved memory used by mt7986-wed firmware + (see bindings/reserved-memory/reserved-memory.txt) + + mediatek,wo-ccif: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek wed-wo controller. + + mediatek,wo-boot: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek wed-wo boot interface. + + mediatek,wo-dlm: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek wed-wo rx hw ring. + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt7986-wed + then: + properties: + mediatek,wo-boot: true + mediatek,wo-ccif: true + mediatek,wo-dlm: true + memory-region: true + required: - compatible - reg@@ -49,3 +84,59 @@ examples: interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>; }; }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + wo_emi: wo-emi@4fd00000 { + reg = <0 0x4fd00000 0 0x40000>; + no-map; + }; + + wo_data: wo-data@4fd80000 { + reg = <0 0x4fd80000 0 0x240000>; + no-map; + }; + + wo_ilm: wo-ilm@151e0000 { + reg = <0 0x151e0000 0 0x8000>; + no-map; + }; + }; + + wo_boot: wo-boot@15194000 { + compatible = "mediatek,mt7986-wo-boot","syscon"; + reg = <0 0x15194000 0 0x1000>; + }; + + wo_ccif0: wo-ccif@151a5000 { + compatible = "mediatek,mt7986-wo-ccif","syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + }; + + wo_dlm0: wo-dlm@151e8000 { + compatible = "mediatek,mt7986-wo-dlm"; + reg = <0 0x151e8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + }; + + wed1: wed@1020a000 { + compatible = "mediatek,mt7986-wed","syscon"; + reg = <0 0x15010000 0 0x1000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + + memory-region = <&wo_emi>, <&wo_data>, <&wo_ilm>; + mediatek,wo-ccif = <&wo_ccif0>; + mediatek,wo-boot = <&wo_boot>; + mediatek,wo-dlm = <&wo_dlm0>; + }; + };Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +46
-0@@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-boot.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: + MediaTek Wireless Ethernet Dispatch WO boot controller interface for MT7986 + +maintainers: + - Lorenzo Bianconi <[email protected]> + - Felix Fietkau <[email protected]> + +description: + The mediatek wo-boot provides a configuration interface for WED WO + boot controller on MT7986 soc. + +properties: + compatible: + items: + - enum: + - mediatek,mt7986-wo-boot + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + wo_boot: wo-boot@15194000 { + compatible = "mediatek,mt7986-wo-boot","syscon"; + reg = <0 0x15194000 0 0x1000>; + }; + };Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +0
-0
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml line 5
Quoted 5 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +5
-0@@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-ccif.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
No improvements...
Quoted 29 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +29
-0+ +title: MediaTek Wireless Ethernet Dispatch WO Controller for MT7986 + +maintainers: + - Lorenzo Bianconi <[email protected]> + - Felix Fietkau <[email protected]> + +description: + The mediatek wo-ccif provides a configuration interface for WED WO + controller on MT7986 soc. + +properties: + compatible: + items: + - enum: + - mediatek,mt7986-wo-ccif + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts +
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml line 44
Quoted 10 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +10
-0+additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + wo_ccif0: wo-ccif@151a5000 {
This is still not entirely generic... What is wo-ccif?
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml line 45
Quoted 1 line
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +1
-0+ compatible = "mediatek,mt7986-wo-ccif","syscon";
Missing space.
All comments might apply to other places.
Best regards,
Krzysztof
Lorenzo Bianconi
maintainerRe: [PATCH v2 net-next 2/6] dt-bindings: net: mediatek: add WED RX binding for MT7986 eth driver
Quoted 30 lines · Lorenzo Bianconi
Quoted 5 lines
Document the binding for the RX Wireless Ethernet Dispatch core on the MT7986 ethernet driver used to offload traffic received by WLAN NIC and forwarded to LAN/WAN one.
Signed-off-by Lorenzo Bianconi <[email protected]>Please use
scripts/get_maintainers.plto get a list of necessary people and lists to CC. It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel.Quoted 18 lines
--- .../arm/mediatek/mediatek,mt7622-wed.yaml | 91 +++++++++++++++++++ .../arm/mediatek/mediatek,mt7986-wo-boot.yaml | 46 ++++++++++ .../arm/mediatek/mediatek,mt7986-wo-ccif.yaml | 49 ++++++++++ .../arm/mediatek/mediatek,mt7986-wo-dlm.yaml | 50 ++++++++++ 4 files changed, 236 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yamlDocumentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +0
-0@@ -29,6 +29,41 @@ properties: interrupts: maxItems: 1
Quoted 4 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml properties: · line 33
Quoted 2 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +2
-0+ memory-region: + minItems: 3No need for minItems.
can we specify memory-region and memory-region-names properties like the code below?
memory-region:
items:
- description:
Phandle for the node (wo-emi) used to run firmware EMI region
- description:
Phandle for the node (wo-ilm) used to run firmware ILM region
- description:
Phandle for the node (wo-data) used to run firmware CPU DATA region
memory-region-names:
items:
- const: wo-emi
- const: wo-ilm
- const: wo-data
Regards,
Lorenzo
Quoted 216 lines
Quoted 155 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +89
-0+ maxItems: 3 + description: + phandles to nodes describing reserved memory used by mt7986-wed firmware + (see bindings/reserved-memory/reserved-memory.txt) + + mediatek,wo-ccif: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek wed-wo controller. + + mediatek,wo-boot: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek wed-wo boot interface. + + mediatek,wo-dlm: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek wed-wo rx hw ring. + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt7986-wed + then: + properties: + mediatek,wo-boot: true + mediatek,wo-ccif: true + mediatek,wo-dlm: true + memory-region: true + required: - compatible - reg@@ -49,3 +84,59 @@ examples: interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>; }; }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + wo_emi: wo-emi@4fd00000 { + reg = <0 0x4fd00000 0 0x40000>; + no-map; + }; + + wo_data: wo-data@4fd80000 { + reg = <0 0x4fd80000 0 0x240000>; + no-map; + }; + + wo_ilm: wo-ilm@151e0000 { + reg = <0 0x151e0000 0 0x8000>; + no-map; + }; + }; + + wo_boot: wo-boot@15194000 { + compatible = "mediatek,mt7986-wo-boot","syscon"; + reg = <0 0x15194000 0 0x1000>; + }; + + wo_ccif0: wo-ccif@151a5000 { + compatible = "mediatek,mt7986-wo-ccif","syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + }; + + wo_dlm0: wo-dlm@151e8000 { + compatible = "mediatek,mt7986-wo-dlm"; + reg = <0 0x151e8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + }; + + wed1: wed@1020a000 { + compatible = "mediatek,mt7986-wed","syscon"; + reg = <0 0x15010000 0 0x1000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + + memory-region = <&wo_emi>, <&wo_data>, <&wo_ilm>; + mediatek,wo-ccif = <&wo_ccif0>; + mediatek,wo-boot = <&wo_boot>; + mediatek,wo-dlm = <&wo_dlm0>; + }; + };Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +46
-0@@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-boot.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: + MediaTek Wireless Ethernet Dispatch WO boot controller interface for MT7986 + +maintainers: + - Lorenzo Bianconi <[email protected]> + - Felix Fietkau <[email protected]> + +description: + The mediatek wo-boot provides a configuration interface for WED WO + boot controller on MT7986 soc. + +properties: + compatible: + items: + - enum: + - mediatek,mt7986-wo-boot + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + wo_boot: wo-boot@15194000 { + compatible = "mediatek,mt7986-wo-boot","syscon"; + reg = <0 0x15194000 0 0x1000>; + }; + };Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +0
-0Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml line 5
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Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +5
-0@@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-ccif.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#"No improvements...
Quoted 29 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +29
-0+ +title: MediaTek Wireless Ethernet Dispatch WO Controller for MT7986 + +maintainers: + - Lorenzo Bianconi <[email protected]> + - Felix Fietkau <[email protected]> + +description: + The mediatek wo-ccif provides a configuration interface for WED WO + controller on MT7986 soc. + +properties: + compatible: + items: + - enum: + - mediatek,mt7986-wo-ccif + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts +Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml line 44
Quoted 10 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +10
-0+additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + wo_ccif0: wo-ccif@151a5000 {This is still not entirely generic... What is wo-ccif?
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml line 45
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Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +1
-0+ compatible = "mediatek,mt7986-wo-ccif","syscon";Missing space.
All comments might apply to other places.
Best regards,
Krzysztof
Lorenzo Bianconi
maintainerPATCH v2 3/6 net: ethernet: mtk_wed: introduce wed mcu support
In reply to Lorenzo BianconiIntroduce WED mcu support used to configure WED WO chip. This is a preliminary patch in order to add RX Wireless Ethernet Dispatch available on MT7986 SoC.
Tested-by Daniel Golle <[email protected]>
Co-developed-by Sujuan Chen <[email protected]>
Signed-off-by Sujuan Chen <[email protected]>
Signed-off-by Lorenzo Bianconi <[email protected]>
--- drivers/net/ethernet/mediatek/Makefile | 2 +- drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 362 +++++++++++++++++++ drivers/net/ethernet/mediatek/mtk_wed_regs.h | 1 + drivers/net/ethernet/mediatek/mtk_wed_wo.h | 152 ++++++++ include/linux/soc/mediatek/mtk_wed.h | 29 ++ 5 files changed, 545 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_mcu.c create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_wo.h
drivers/net/ethernet/mediatek/Makefile +1 -1
@@ -5,7 +5,7 @@ obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o -mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o +mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o ifdef CONFIG_DEBUG_FS mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o endif
drivers/net/ethernet/mediatek/mtk_wed_mcu.c new file +362 -0
362 lines not on this page · raw message
drivers/net/ethernet/mediatek/mtk_wed_regs.h +1 -0
@@ -152,6 +152,7 @@ struct mtk_wdma_desc {#define MTK_WED_RING_RX (_n) (0x400 + (_n) * 0x10) +#define MTK_WED_SCR0 0x3c0#define MTK_WED_WPDMA_INT_TRIGGER 0x504#define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE BIT(1)#define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE GENMASK(5, 4)
drivers/net/ethernet/mediatek/mtk_wed_wo.h new file +152 -0
152 lines not on this page · raw message
include/linux/soc/mediatek/mtk_wed.h +29 -0
@@ -11,6 +11,35 @@struct mtk_wed_hw ;struct mtk_wdma_desc ; +enum mtk_wed_wo_cmd { +MTK_WED_WO_CMD_WED_CFG , +MTK_WED_WO_CMD_WED_RX_STAT , +MTK_WED_WO_CMD_RRO_SER , +MTK_WED_WO_CMD_DBG_INFO , +MTK_WED_WO_CMD_DEV_INFO , +MTK_WED_WO_CMD_BSS_INFO , +MTK_WED_WO_CMD_STA_REC , +MTK_WED_WO_CMD_DEV_INFO_DUMP , +MTK_WED_WO_CMD_BSS_INFO_DUMP , +MTK_WED_WO_CMD_STA_REC_DUMP , +MTK_WED_WO_CMD_BA_INFO_DUMP , +MTK_WED_WO_CMD_FBCMD_Q_DUMP , +MTK_WED_WO_CMD_FW_LOG_CTRL , +MTK_WED_WO_CMD_LOG_FLUSH , +MTK_WED_WO_CMD_CHANGE_STATE , +MTK_WED_WO_CMD_CPU_STATS_ENABLE , +MTK_WED_WO_CMD_CPU_STATS_DUMP , +MTK_WED_WO_CMD_EXCEPTION_INIT , +MTK_WED_WO_CMD_PROF_CTRL , +MTK_WED_WO_CMD_STA_BA_DUMP , +MTK_WED_WO_CMD_BA_CTRL_DUMP , +MTK_WED_WO_CMD_RXCNT_CTRL , +MTK_WED_WO_CMD_RXCNT_INFO , +MTK_WED_WO_CMD_SET_CAP , +MTK_WED_WO_CMD_CCIF_RING_DUMP , +MTK_WED_WO_CMD_WED_END +}; +enum mtk_wed_bus_tye {MTK_WED_BUS_PCIE ,MTK_WED_BUS_AXI ,
Signature · 1 line
2.37.3
Lorenzo Bianconi
maintainerPATCH v2 4/6 net: ethernet: mtk_wed: introduce wed wo support
In reply to Lorenzo BianconiIntroduce WO chip support to mtk wed driver. MTK WED WO is used to implement RX Wireless Ethernet Dispatch and offload traffic received by wlan nic to the wired interface.
Tested-by Daniel Golle <[email protected]>
Co-developed-by Sujuan Chen <[email protected]>
Signed-off-by Sujuan Chen <[email protected]>
Signed-off-by Lorenzo Bianconi <[email protected]>
--- drivers/net/ethernet/mediatek/Makefile | 2 +- drivers/net/ethernet/mediatek/mtk_wed.c | 7 +- drivers/net/ethernet/mediatek/mtk_wed.h | 2 + drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 3 +- drivers/net/ethernet/mediatek/mtk_wed_wo.c | 545 ++++++++++++++++++++ drivers/net/ethernet/mediatek/mtk_wed_wo.h | 107 ++++ 6 files changed, 662 insertions(+), 4 deletions(-) create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_wo.c
drivers/net/ethernet/mediatek/Makefile +1 -1
@@ -5,7 +5,7 @@ obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o -mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o +mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o ifdef CONFIG_DEBUG_FS mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o endif
drivers/net/ethernet/mediatek/mtk_wed.c +6 -1
@@ -16,6 +16,7 @@#include "mtk_wed_regs.h" #include "mtk_wed.h" #include "mtk_ppe.h" +#include "mtk_wed_wo.h" #define MTK_PCIE_BASE (n) (0x1a143000 + (n) * 0x2000)
@@ -355,6 +356,8 @@ mtk_wed_detach(struct mtk_wed_device *dev)mtk_wed_free_buffer (dev);mtk_wed_free_tx_rings (dev); +if (hw->version !=1 ) +mtk_wed_wo_deinit (hw);if (dev->wlan.bus_type ==MTK_WED_BUS_PCIE ) {struct device_node *wlan_node;
@@ -878,9 +881,11 @@ mtk_wed_attach(struct mtk_wed_device *dev) }mtk_wed_hw_init_early (dev); -if (hw->hifsys) +if (hw->version ==1 )regmap_update_bits (hw->hifsys,HIFSYS_DMA_AG_MAP ,BIT (hw->index),0 ); +else + ret =mtk_wed_wo_init (hw); out:mutex_unlock (&hw_lock);
drivers/net/ethernet/mediatek/mtk_wed.h +2 -0
@@ -10,6 +10,7 @@#include <linux/netdevice.h> struct mtk_eth ; +struct mtk_wed_wo ;struct mtk_wed_hw {struct device_node *node;
@@ -22,6 +23,7 @@ struct mtk_wed_hw {struct regmap *mirror;struct dentry *debugfs_dir;struct mtk_wed_device *wed_dev; +struct mtk_wed_wo *wed_wo;u32 debugfs_reg;u32 num_flows;u8 version;
drivers/net/ethernet/mediatek/mtk_wed_mcu.c +1 -2
@@ -122,8 +122,7 @@ mtk_wed_mcu_skb_send_msg(struct mtk_wed_wo *wo, struct sk_buff *skb,if (id ==MTK_WED_MODULE_ID_WO ) hdr->flag |=cpu_to_le16 (MTK_WED_WARP_CMD_FLAG_FROM_TO_WO ); -dev_kfree_skb (skb); -return 0 ; +return mtk_wed_wo_queue_tx_skb (wo, &wo->q_tx, skb); } static int
drivers/net/ethernet/mediatek/mtk_wed_wo.c new file +545 -0
545 lines not on this page · raw message
drivers/net/ethernet/mediatek/mtk_wed_wo.h +107 -0
134 lines not on this page · raw message
Signature · 1 line
2.37.3
Lorenzo Bianconi
maintainerPATCH v2 5/6 net: ethernet: mtk_wed: add configure wed wo support
In reply to Lorenzo BianconiEnable RX Wireless Ethernet Dispatch available on MT7986 Soc.
Tested-by Daniel Golle <[email protected]>
Co-developed-by Sujuan Chen <[email protected]>
Signed-off-by Sujuan Chen <[email protected]>
Signed-off-by Lorenzo Bianconi <[email protected]>
--- drivers/net/ethernet/mediatek/mtk_wed.c | 572 +++++++++++++++++-- drivers/net/ethernet/mediatek/mtk_wed.h | 19 + drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 45 +- drivers/net/ethernet/mediatek/mtk_wed_regs.h | 128 ++++- drivers/net/ethernet/mediatek/mtk_wed_wo.h | 28 + include/linux/soc/mediatek/mtk_wed.h | 75 ++- 6 files changed, 816 insertions(+), 51 deletions(-)
drivers/net/ethernet/mediatek/mtk_wed.c +532 -40
@@ -23,6 +23,7 @@#define MTK_WED_PKT_SIZE 1900#define MTK_WED_BUF_SIZE 2048#define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048) +#define MTK_WED_RX_RING_SIZE 1536#define MTK_WED_TX_RING_SIZE 2048#define MTK_WED_WDMA_RING_SIZE 1024
@@ -31,6 +32,10 @@#define MTK_WED_PER_GROUP_PKT 128#define MTK_WED_FBUF_SIZE 128 +#define MTK_WED_MIOD_CNT 16 +#define MTK_WED_FB_CMD_CNT 1024 +#define MTK_WED_RRO_QUE_CNT 8192 +#define MTK_WED_MIOD_ENTRY_CNT 128static struct mtk_wed_hw *hw_list[2 ];static DEFINE_MUTEX (hw_lock);
@@ -65,12 +70,76 @@ wdma_set(struct mtk_wed_device *dev, u32 reg, u32 mask)wdma_m32 (dev, reg,0 , mask); } +static void +wdma_clr (struct mtk_wed_device *dev,u32 reg,u32 mask) +{ +wdma_m32 (dev, reg, mask,0 ); +} + +static u32 +wifi_r32 (struct mtk_wed_device *dev,u32 reg) +{ +return readl (dev->wlan.base + reg); +} + +static void +wifi_w32 (struct mtk_wed_device *dev,u32 reg,u32 val) +{ +writel (val, dev->wlan.base + reg); +} +static u32 mtk_wed_read_reset (struct mtk_wed_device *dev) {return wed_r32 (dev,MTK_WED_RESET ); } +static u32 +mtk_wdma_read_reset (struct mtk_wed_device *dev) +{ +return wdma_r32 (dev,MTK_WDMA_GLO_CFG ); +} + +static void +mtk_wdma_rx_reset (struct mtk_wed_device *dev) +{ +u32 status, mask =MTK_WDMA_GLO_CFG_RX_DMA_BUSY ; +int i; + +wdma_clr (dev,MTK_WDMA_GLO_CFG ,MTK_WDMA_GLO_CFG_RX_DMA_EN ); +if (readx_poll_timeout (mtk_wdma_read_reset, dev, status, + !(status & mask),0 ,1000 )) +dev_err (dev->hw->dev,"rx reset failed\n" ); + +for (i =0 ; i <ARRAY_SIZE (dev->rx_wdma); i++) { +if (dev->rx_wdma[i].desc) +continue ; + +wdma_w32 (dev, +MTK_WDMA_RING_RX (i) +MTK_WED_RING_OFS_CPU_IDX ,0 ); + } +} + +static void +mtk_wdma_tx_reset (struct mtk_wed_device *dev) +{ +u32 status, mask =MTK_WDMA_GLO_CFG_TX_DMA_BUSY ; +int i; + +wdma_clr (dev,MTK_WDMA_GLO_CFG ,MTK_WDMA_GLO_CFG_TX_DMA_EN ); +if (readx_poll_timeout (mtk_wdma_read_reset, dev, status, + !(status & mask),0 ,1000 )) +dev_err (dev->hw->dev,"tx reset failed\n" ); + +for (i =0 ; i <ARRAY_SIZE (dev->tx_wdma); i++) { +if (dev->tx_wdma[i].desc) +continue ; + +wdma_w32 (dev, +MTK_WDMA_RING_TX (i) +MTK_WED_RING_OFS_CPU_IDX ,0 ); + } +} +static void mtk_wed_reset (struct mtk_wed_device *dev,u32 mask) {
@@ -82,6 +151,50 @@ mtk_wed_reset(struct mtk_wed_device *dev, u32 mask)WARN_ON_ONCE (1 ); } +static void +mtk_wed_wo_reset (struct mtk_wed_device *dev) +{ +unsigned long timeout = jiffies +MTK_WOCPU_TIMEOUT ; +struct mtk_wed_wo *wo = dev->hw->wed_wo; +u8 state =MTK_WED_WO_STATE_DISABLE ; +void __iomem *reg; +u32 val; + +mtk_wdma_tx_reset (dev); +mtk_wed_reset (dev,MTK_WED_RESET_WED ); + +mtk_wed_mcu_send_msg (wo,MTK_WED_MODULE_ID_WO , +MTK_WED_WO_CMD_CHANGE_STATE , &state, +sizeof (state), false); +do { + val =wed_r32 (dev, +MTK_WED_SCR0 +4 *MTK_WED_DUMMY_CR_WO_STATUS ); +usleep_range (100 ,200 ); + }while (val !=MTK_WED_WOIF_DISABLE_DONE && + !time_after (jiffies, timeout)); + + reg =ioremap (MTK_WED_WO_CPU_MCUSYS_RESET_ADDR ,4 ); + + val =readl (reg); +switch (dev->hw->index) { +case 0 : + val |=MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK ; +writel (val, reg); + val &= ~MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK ; +writel (val, reg); +break ; +case 1 : + val |=MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK ; +writel (val, reg); + val &= ~MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK ; +writel (val, reg); +break ; +default : +break ; + } +iounmap (reg); +} +static struct mtk_wed_hw *mtk_wed_assign (struct mtk_wed_device *dev) {
@@ -133,16 +246,16 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev)if (!page_list)return -ENOMEM ; - dev->buf_ring.size = ring_size; - dev->buf_ring.pages = page_list; + dev->tx_buf_ring.size = ring_size; + dev->tx_buf_ring.pages = page_list; desc =dma_alloc_coherent (dev->hw->dev, ring_size *sizeof (*desc), &desc_phys,GFP_KERNEL );if (!desc)return -ENOMEM ; - dev->buf_ring.desc = desc; - dev->buf_ring.desc_phys = desc_phys; + dev->tx_buf_ring.desc = desc; + dev->tx_buf_ring.desc_phys = desc_phys;for (i =0 , page_idx =0 ; i < ring_size; i +=MTK_WED_BUF_PER_PAGE ) {dma_addr_t page_phys, buf_phys;
@@ -205,8 +318,8 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev)static void mtk_wed_free_buffer (struct mtk_wed_device *dev) { -struct mtk_wdma_desc *desc = dev->buf_ring.desc; -void **page_list = dev->buf_ring.pages; +struct mtk_wdma_desc *desc = dev->tx_buf_ring.desc; +void **page_list = dev->tx_buf_ring.pages;int page_idx;int i;
@@ -216,7 +329,8 @@ mtk_wed_free_buffer(struct mtk_wed_device *dev)if (!desc) goto free_pagelist; -for (i =0 , page_idx =0 ; i < dev->buf_ring.size; i +=MTK_WED_BUF_PER_PAGE ) { +for (i =0 , page_idx =0 ; i < dev->tx_buf_ring.size; + i +=MTK_WED_BUF_PER_PAGE ) {void *page = page_list[page_idx++];dma_addr_t buf_addr;
@@ -229,13 +343,46 @@ mtk_wed_free_buffer(struct mtk_wed_device *dev)__free_page (page); } -dma_free_coherent (dev->hw->dev, dev->buf_ring.size *sizeof (*desc), - desc, dev->buf_ring.desc_phys); +dma_free_coherent (dev->hw->dev, dev->tx_buf_ring.size *sizeof (*desc), + desc, dev->tx_buf_ring.desc_phys); free_pagelist:kfree (page_list); } +static int +mtk_wed_rx_bm_alloc (struct mtk_wed_device *dev) +{ +struct mtk_rxbm_desc *desc; +dma_addr_t desc_phys; + + dev->rx_buf_ring.size = dev->wlan.rx_nbuf; + desc =dma_alloc_coherent (dev->hw->dev, + dev->wlan.rx_nbuf *sizeof (*desc), + &desc_phys,GFP_KERNEL ); +if (!desc) +return -ENOMEM ; + + dev->rx_buf_ring.desc = desc; + dev->rx_buf_ring.desc_phys = desc_phys; + dev->wlan.init_rx_buf (dev, dev->wlan.rx_npkt); + +return 0 ; +} + +static void +mtk_wed_free_rx_bm (struct mtk_wed_device *dev) +{ +struct mtk_rxbm_desc *desc = dev->rx_buf_ring.desc; + +if (!desc) +return ; + + dev->wlan.release_rx_buf (dev); +dma_free_coherent (dev->hw->dev, dev->rx_buf_ring.size *sizeof (*desc), + desc, dev->rx_buf_ring.desc_phys); +} +static void mtk_wed_free_ring (struct mtk_wed_device *dev,struct mtk_wed_ring *ring) {
@@ -246,6 +393,13 @@ mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring) ring->desc, ring->desc_phys); } +static void +mtk_wed_free_rx_rings (struct mtk_wed_device *dev) +{ +mtk_wed_free_rx_bm (dev); +mtk_wed_free_ring (dev, &dev->rro.ring); +} +static void mtk_wed_free_tx_rings (struct mtk_wed_device *dev) {
@@ -291,6 +445,35 @@ mtk_wed_set_512_support(struct mtk_wed_device *dev, bool enable) } } +#define MTK_WFMDA_RX_DMA_EN BIT(2) +static void +mtk_wed_check_wfdma_rx_fill (struct mtk_wed_device *dev,int idx) +{ +u32 val; +int i; + +for (i =0 ; i <3 ; i++) { +u32 cur_idx; + + cur_idx =wed_r32 (dev, +MTK_WED_WPDMA_RING_RX_DATA (idx) + +MTK_WED_RING_OFS_CPU_IDX ); +if (cur_idx ==MTK_WED_RX_RING_SIZE -1 ) +break ; + +usleep_range (100000 ,200000 ); + } + +if (i ==3 ) { +dev_err (dev->hw->dev,"rx dma enable failed\n" ); +return ; + } + + val =wifi_r32 (dev, dev->wlan.wpdma_rx_glo - dev->wlan.phy_base) | +MTK_WFMDA_RX_DMA_EN ; +wifi_w32 (dev, dev->wlan.wpdma_rx_glo - dev->wlan.phy_base, val); +} +static void mtk_wed_dma_disable (struct mtk_wed_device *dev) {
@@ -304,20 +487,25 @@ mtk_wed_dma_disable(struct mtk_wed_device *dev)MTK_WED_GLO_CFG_TX_DMA_EN | MTK_WED_GLO_CFG_RX_DMA_EN); -wdma_m32 (dev,MTK_WDMA_GLO_CFG , +wdma_clr (dev,MTK_WDMA_GLO_CFG ,MTK_WDMA_GLO_CFG_TX_DMA_EN |MTK_WDMA_GLO_CFG_RX_INFO1_PRERES | -MTK_WDMA_GLO_CFG_RX_INFO2_PRERES ,0 ); +MTK_WDMA_GLO_CFG_RX_INFO2_PRERES );if (dev->hw->version ==1 ) {regmap_write (dev->hw->mirror, dev->hw->index *4 ,0 ); -wdma_m32 (dev,MTK_WDMA_GLO_CFG , -MTK_WDMA_GLO_CFG_RX_INFO3_PRERES ,0 ); +wdma_clr (dev,MTK_WDMA_GLO_CFG , +MTK_WDMA_GLO_CFG_RX_INFO3_PRERES ); }else {wed_clr (dev,MTK_WED_WPDMA_GLO_CFG ,MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC ); +wed_clr (dev,MTK_WED_WPDMA_RX_D_GLO_CFG , +MTK_WED_WPDMA_RX_D_RX_DRV_EN ); +wed_clr (dev,MTK_WED_WDMA_GLO_CFG , +MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK ); +mtk_wed_set_512_support (dev, false); } }
@@ -338,6 +526,13 @@ mtk_wed_stop(struct mtk_wed_device *dev)wdma_w32 (dev,MTK_WDMA_INT_MASK ,0 );wdma_w32 (dev,MTK_WDMA_INT_GRP2 ,0 );wed_w32 (dev,MTK_WED_WPDMA_INT_MASK ,0 ); + +if (dev->hw->version ==1 ) +return ; + +wed_w32 (dev,MTK_WED_EXT_INT_MASK1 ,0 ); +wed_w32 (dev,MTK_WED_EXT_INT_MASK2 ,0 ); +wed_clr (dev,MTK_WED_CTRL ,MTK_WED_CTRL_WED_RX_BM_EN ); } static void
@@ -353,11 +548,21 @@ mtk_wed_detach(struct mtk_wed_device *dev)wdma_w32 (dev,MTK_WDMA_RESET_IDX ,0 );mtk_wed_reset (dev,MTK_WED_RESET_WED ); +if (mtk_wed_get_rx_capa (dev)) { +wdma_clr (dev,MTK_WDMA_GLO_CFG ,MTK_WDMA_GLO_CFG_TX_DMA_EN ); +wdma_w32 (dev,MTK_WDMA_RESET_IDX ,MTK_WDMA_RESET_IDX_TX ); +wdma_w32 (dev,MTK_WDMA_RESET_IDX ,0 ); + }mtk_wed_free_buffer (dev);mtk_wed_free_tx_rings (dev); -if (hw->version !=1 ) + +if (mtk_wed_get_rx_capa (dev)) { +mtk_wed_wo_reset (dev); +mtk_wed_free_rx_rings (dev);mtk_wed_wo_deinit (hw); +mtk_wdma_rx_reset (dev); + }if (dev->wlan.bus_type ==MTK_WED_BUS_PCIE ) {struct device_node *wlan_node;
@@ -434,10 +639,12 @@ mtk_wed_set_wpdma(struct mtk_wed_device *dev) }else {mtk_wed_bus_init (dev); -wed_w32 (dev,MTK_WED_WPDMA_CFG_BASE , dev->wlan.wpdma_int); -wed_w32 (dev,MTK_WED_WPDMA_CFG_INT_MASK , dev->wlan.wpdma_mask); -wed_w32 (dev,MTK_WED_WPDMA_CFG_TX , dev->wlan.wpdma_tx); -wed_w32 (dev,MTK_WED_WPDMA_CFG_TX_FREE , dev->wlan.wpdma_txfree); +wed_w32 (dev,MTK_WED_WPDMA_CFG_BASE , dev->wlan.wpdma_int); +wed_w32 (dev,MTK_WED_WPDMA_CFG_INT_MASK , dev->wlan.wpdma_mask); +wed_w32 (dev,MTK_WED_WPDMA_CFG_TX , dev->wlan.wpdma_tx); +wed_w32 (dev,MTK_WED_WPDMA_CFG_TX_FREE , dev->wlan.wpdma_txfree); +wed_w32 (dev,MTK_WED_WPDMA_RX_GLO_CFG , dev->wlan.wpdma_rx_glo); +wed_w32 (dev,MTK_WED_WPDMA_RX_RING , dev->wlan.wpdma_rx); } }
@@ -487,6 +694,67 @@ mtk_wed_hw_init_early(struct mtk_wed_device *dev) } } +static void +mtk_wed_rx_bm_hw_init (struct mtk_wed_device *dev) +{ +wed_w32 (dev,MTK_WED_RX_BM_RX_DMAD , +FIELD_PREP (MTK_WED_RX_BM_RX_DMAD_SDL0 , dev->wlan.rx_size)); +wed_w32 (dev,MTK_WED_RX_BM_BASE , dev->rx_buf_ring.desc_phys); +wed_w32 (dev,MTK_WED_RX_BM_INIT_PTR ,MTK_WED_RX_BM_INIT_SW_TAIL | +FIELD_PREP (MTK_WED_RX_BM_SW_TAIL , dev->wlan.rx_npkt)); +wed_w32 (dev,MTK_WED_RX_BM_DYN_ALLOC_TH , +FIELD_PREP (MTK_WED_RX_BM_DYN_ALLOC_TH_H ,0xffff )); +wed_set (dev,MTK_WED_CTRL ,MTK_WED_CTRL_WED_RX_BM_EN ); +} + +static void +mtk_wed_rro_hw_init (struct mtk_wed_device *dev) +{ +wed_w32 (dev,MTK_WED_RROQM_MIOD_CFG , +FIELD_PREP (MTK_WED_RROQM_MIOD_MID_DW ,0x70 >>2 ) | +FIELD_PREP (MTK_WED_RROQM_MIOD_MOD_DW ,0x10 >>2 ) | +FIELD_PREP (MTK_WED_RROQM_MIOD_ENTRY_DW , +MTK_WED_MIOD_ENTRY_CNT >>2 )); + +wed_w32 (dev,MTK_WED_RROQM_MIOD_CTRL0 , dev->rro.miod_phys); +wed_w32 (dev,MTK_WED_RROQM_MIOD_CTRL1 , +FIELD_PREP (MTK_WED_RROQM_MIOD_CNT ,MTK_WED_MIOD_CNT )); +wed_w32 (dev,MTK_WED_RROQM_FDBK_CTRL0 , dev->rro.fdbk_phys); +wed_w32 (dev,MTK_WED_RROQM_FDBK_CTRL1 , +FIELD_PREP (MTK_WED_RROQM_FDBK_CNT ,MTK_WED_FB_CMD_CNT )); +wed_w32 (dev,MTK_WED_RROQM_FDBK_CTRL2 ,0 ); +wed_w32 (dev,MTK_WED_RROQ_BASE_L , dev->rro.ring.desc_phys); + +wed_set (dev,MTK_WED_RROQM_RST_IDX , +MTK_WED_RROQM_RST_IDX_MIOD | +MTK_WED_RROQM_RST_IDX_FDBK ); + +wed_w32 (dev,MTK_WED_RROQM_RST_IDX ,0 ); +wed_w32 (dev,MTK_WED_RROQM_MIOD_CTRL2 ,MTK_WED_MIOD_CNT -1 ); +wed_set (dev,MTK_WED_CTRL ,MTK_WED_CTRL_RX_RRO_QM_EN ); +} + +static void +mtk_wed_route_qm_hw_init (struct mtk_wed_device *dev) +{ +wed_w32 (dev,MTK_WED_RESET ,MTK_WED_RESET_RX_ROUTE_QM ); + +for (;;) { +usleep_range (100 ,200 ); +if (!(wed_r32 (dev,MTK_WED_RESET ) &MTK_WED_RESET_RX_ROUTE_QM )) +break ; + } + +/* configure RX_ROUTE_QM */ +wed_clr (dev,MTK_WED_RTQM_GLO_CFG ,MTK_WED_RTQM_Q_RST ); +wed_clr (dev,MTK_WED_RTQM_GLO_CFG ,MTK_WED_RTQM_TXDMAD_FPORT ); +wed_set (dev,MTK_WED_RTQM_GLO_CFG , +FIELD_PREP (MTK_WED_RTQM_TXDMAD_FPORT ,0x3 + dev->hw->index)); +wed_clr (dev,MTK_WED_RTQM_GLO_CFG ,MTK_WED_RTQM_Q_RST ); +/* enable RX_ROUTE_QM */ +wed_set (dev,MTK_WED_CTRL ,MTK_WED_CTRL_RX_ROUTE_QM_EN ); +} +static void mtk_wed_hw_init (struct mtk_wed_device *dev) {
@@ -498,11 +766,11 @@ mtk_wed_hw_init(struct mtk_wed_device *dev)wed_w32 (dev,MTK_WED_TX_BM_CTRL ,MTK_WED_TX_BM_CTRL_PAUSE |FIELD_PREP (MTK_WED_TX_BM_CTRL_VLD_GRP_NUM , - dev->buf_ring.size /128 ) | + dev->tx_buf_ring.size /128 ) |FIELD_PREP (MTK_WED_TX_BM_CTRL_RSV_GRP_NUM ,MTK_WED_TX_RING_SIZE /256 )); -wed_w32 (dev,MTK_WED_TX_BM_BASE , dev->buf_ring.desc_phys); +wed_w32 (dev,MTK_WED_TX_BM_BASE , dev->tx_buf_ring.desc_phys);wed_w32 (dev,MTK_WED_TX_BM_BUF_LEN ,MTK_WED_PKT_SIZE );
@@ -529,9 +797,9 @@ mtk_wed_hw_init(struct mtk_wed_device *dev)wed_w32 (dev,MTK_WED_TX_TKID_CTRL ,MTK_WED_TX_TKID_CTRL_PAUSE |FIELD_PREP (MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM , - dev->buf_ring.size /128 ) | + dev->tx_buf_ring.size /128 ) |FIELD_PREP (MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM , - dev->buf_ring.size /128 )); + dev->tx_buf_ring.size /128 ));wed_w32 (dev,MTK_WED_TX_TKID_DYN_THR ,FIELD_PREP (MTK_WED_TX_TKID_DYN_THR_LO ,0 ) |MTK_WED_TX_TKID_DYN_THR_HI );
@@ -539,18 +807,28 @@ mtk_wed_hw_init(struct mtk_wed_device *dev)mtk_wed_reset (dev,MTK_WED_RESET_TX_BM ); -if (dev->hw->version ==1 ) +if (dev->hw->version ==1 ) {wed_set (dev,MTK_WED_CTRL ,MTK_WED_CTRL_WED_TX_BM_EN |MTK_WED_CTRL_WED_TX_FREE_AGENT_EN ); -else + }else {wed_clr (dev,MTK_WED_TX_TKID_CTRL ,MTK_WED_TX_TKID_CTRL_PAUSE ); +/* rx hw init */ +wed_w32 (dev,MTK_WED_WPDMA_RX_D_RST_IDX , +MTK_WED_WPDMA_RX_D_RST_CRX_IDX | +MTK_WED_WPDMA_RX_D_RST_DRV_IDX ); +wed_w32 (dev,MTK_WED_WPDMA_RX_D_RST_IDX ,0 ); + +mtk_wed_rx_bm_hw_init (dev); +mtk_wed_rro_hw_init (dev); +mtk_wed_route_qm_hw_init (dev); + }wed_clr (dev,MTK_WED_TX_BM_CTRL ,MTK_WED_TX_BM_CTRL_PAUSE ); }static void -mtk_wed_ring_reset (struct mtk_wed_ring *ring,int size) +mtk_wed_ring_reset (struct mtk_wed_ring *ring,int size,bool tx) {void *head = (void *)ring->desc;int i;
@@ -560,7 +838,10 @@ mtk_wed_ring_reset(struct mtk_wed_ring *ring, int size) desc = (struct mtk_wdma_desc *)(head + i * ring->desc_size); desc->buf0 =0 ; - desc->ctrl =cpu_to_le32 (MTK_WDMA_DESC_CTRL_DMA_DONE ); +if (tx) + desc->ctrl =cpu_to_le32 (MTK_WDMA_DESC_CTRL_DMA_DONE ); +else + desc->ctrl =cpu_to_le32 (MTK_WFDMA_DESC_CTRL_TO_HOST ); desc->buf1 =0 ; desc->info =0 ; }
@@ -616,7 +897,8 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev)if (!dev->tx_ring[i].desc)continue ; -mtk_wed_ring_reset (&dev->tx_ring[i],MTK_WED_TX_RING_SIZE ); +mtk_wed_ring_reset (&dev->tx_ring[i],MTK_WED_TX_RING_SIZE , + true); }if (mtk_wed_poll_busy (dev))
@@ -634,6 +916,9 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev)wdma_w32 (dev,MTK_WDMA_RESET_IDX ,MTK_WDMA_RESET_IDX_RX );wdma_w32 (dev,MTK_WDMA_RESET_IDX ,0 ); +if (mtk_wed_get_rx_capa (dev)) +mtk_wdma_rx_reset (dev); +if (busy) {mtk_wed_reset (dev,MTK_WED_RESET_WDMA_INT_AGENT );mtk_wed_reset (dev,MTK_WED_RESET_WDMA_RX_DRV );
@@ -668,12 +953,28 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev) MTK_WED_WPDMA_RESET_IDX_RX);wed_w32 (dev,MTK_WED_WPDMA_RESET_IDX ,0 ); } +} +static int +mtk_wed_rro_ring_alloc (struct mtk_wed_device *dev,struct mtk_wed_ring *ring, +int size) +{ + ring->desc =dma_alloc_coherent (dev->hw->dev, + size *sizeof (*ring->desc), + &ring->desc_phys,GFP_KERNEL ); +if (!ring->desc) +return -ENOMEM ; + + ring->desc_size =sizeof (*ring->desc); + ring->size = size; +memset (ring->desc,0 , size); + +return 0 ; }static int mtk_wed_ring_alloc (struct mtk_wed_device *dev,struct mtk_wed_ring *ring, -int size,u32 desc_size) +int size,u32 desc_size,bool tx) { ring->desc =dma_alloc_coherent (dev->hw->dev, size * desc_size, &ring->desc_phys,GFP_KERNEL );
@@ -682,18 +983,19 @@ mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, ring->desc_size = desc_size; ring->size = size; -mtk_wed_ring_reset (ring, size); +mtk_wed_ring_reset (ring, size, tx);return 0 ; }static int -mtk_wed_wdma_ring_setup (struct mtk_wed_device *dev,int idx,int size) +mtk_wed_wdma_rx_ring_setup (struct mtk_wed_device *dev,int idx,int size) {u32 desc_size =sizeof (struct mtk_wdma_desc ) * dev->hw->version;struct mtk_wed_ring *wdma = &dev->tx_wdma[idx]; -if (mtk_wed_ring_alloc (dev, wdma,MTK_WED_WDMA_RING_SIZE , desc_size)) +if (mtk_wed_ring_alloc (dev, wdma,MTK_WED_WDMA_RING_SIZE , desc_size, + true))return -ENOMEM ; wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
@@ -710,6 +1012,112 @@ mtk_wed_wdma_ring_setup(struct mtk_wed_device *dev, int idx, int size)return 0 ; } +static int +mtk_wed_wdma_tx_ring_setup (struct mtk_wed_device *dev,int idx,int size) +{ +u32 desc_size =sizeof (struct mtk_wdma_desc ) * dev->hw->version; +struct mtk_wed_ring *wdma = &dev->rx_wdma[idx]; + +if (mtk_wed_ring_alloc (dev, wdma,MTK_WED_WDMA_RING_SIZE , desc_size, + true)) +return -ENOMEM ; + +wdma_w32 (dev,MTK_WDMA_RING_TX (idx) +MTK_WED_RING_OFS_BASE , + wdma->desc_phys); +wdma_w32 (dev,MTK_WDMA_RING_TX (idx) +MTK_WED_RING_OFS_COUNT , + size); +wdma_w32 (dev,MTK_WDMA_RING_TX (idx) +MTK_WED_RING_OFS_CPU_IDX ,0 ); +wdma_w32 (dev,MTK_WDMA_RING_TX (idx) +MTK_WED_RING_OFS_DMA_IDX ,0 ); + +if (!idx) { +wed_w32 (dev,MTK_WED_WDMA_RING_TX +MTK_WED_RING_OFS_BASE , + wdma->desc_phys); +wed_w32 (dev,MTK_WED_WDMA_RING_TX +MTK_WED_RING_OFS_COUNT , + size); +wed_w32 (dev,MTK_WED_WDMA_RING_TX +MTK_WED_RING_OFS_CPU_IDX , +0 ); +wed_w32 (dev,MTK_WED_WDMA_RING_TX +MTK_WED_RING_OFS_DMA_IDX , +0 ); + } + +return 0 ; +} + +static int +mtk_wed_rro_alloc (struct mtk_wed_device *dev) +{ +struct device_node *np; +struct resource res; +int ret; + + np =of_parse_phandle (dev->hw->node,"mediatek,wo-dlm" ,0 ); +if (!np) +return -ENODEV ; + + ret =of_address_to_resource (np,0 , &res); +if (ret) +return ret; + + dev->rro.miod_phys = res.start; + dev->rro.fdbk_phys =MTK_WED_MIOD_ENTRY_CNT *MTK_WED_MIOD_CNT + + dev->rro.miod_phys; + +if (mtk_wed_rro_ring_alloc (dev, &dev->rro.ring,MTK_WED_RRO_QUE_CNT )) +return -ENOMEM ; + +return 0 ; +} + +static int +mtk_wed_rro_cfg (struct mtk_wed_device *dev) +{ +struct mtk_wed_wo *wo = dev->hw->wed_wo; +struct { +struct { +u32 base; +u32 cnt; +u32 unit; + } ring[2 ]; +u32 wed; +u8 version; + } req = { + .ring[0 ] = { + .base =MTK_WED_WOCPU_VIEW_MIOD_BASE , + .cnt =MTK_WED_MIOD_CNT , + .unit =MTK_WED_MIOD_ENTRY_CNT , + }, + .ring[1 ] = { + .base =MTK_WED_WOCPU_VIEW_MIOD_BASE + +MTK_WED_MIOD_ENTRY_CNT *MTK_WED_MIOD_CNT , + .cnt =MTK_WED_FB_CMD_CNT , + .unit =4 , + }, + }; + +return mtk_wed_mcu_send_msg (wo,MTK_WED_MODULE_ID_WO , +MTK_WED_WO_CMD_WED_CFG , + &req,sizeof (req), true); +} + +static void +mtk_wed_ppe_check (struct mtk_wed_device *dev,struct sk_buff *skb, +u32 reason,u32 hash) +{ +struct mtk_eth *eth = dev->hw->eth; +struct ethhdr *eh; + +if (!skb) +return ; + +if (reason !=MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED ) +return ; + +skb_set_mac_header (skb,0 ); + eh =eth_hdr (skb); + skb->protocol = eh->h_proto; +mtk_ppe_check_skb (eth->ppe[dev->hw->index], skb, hash); +} +static void mtk_wed_configure_irq (struct mtk_wed_device *dev,u32 irq_mask) {
@@ -732,6 +1140,8 @@ mtk_wed_configure_irq(struct mtk_wed_device *dev, u32 irq_mask)wed_clr (dev,MTK_WED_WDMA_INT_CTRL , wdma_mask); }else { + wdma_mask |=FIELD_PREP (MTK_WDMA_INT_MASK_TX_DONE , +GENMASK (1 ,0 ));/* initail tx interrupt trigger */ wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX, MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
@@ -750,6 +1160,16 @@ mtk_wed_configure_irq(struct mtk_wed_device *dev, u32 irq_mask)FIELD_PREP (MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG , dev->wlan.txfree_tbit)); +wed_w32 (dev,MTK_WED_WPDMA_INT_CTRL_RX , +MTK_WED_WPDMA_INT_CTRL_RX0_EN | +MTK_WED_WPDMA_INT_CTRL_RX0_CLR | +MTK_WED_WPDMA_INT_CTRL_RX1_EN | +MTK_WED_WPDMA_INT_CTRL_RX1_CLR | +FIELD_PREP (MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG , + dev->wlan.rx_tbit[0 ]) | +FIELD_PREP (MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG , + dev->wlan.rx_tbit[1 ])); +wed_w32 (dev,MTK_WED_WDMA_INT_CLR , wdma_mask); wed_set(dev, MTK_WED_WDMA_INT_CTRL, FIELD_PREP(MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL,
@@ -787,9 +1207,15 @@ mtk_wed_dma_enable(struct mtk_wed_device *dev)wdma_set (dev,MTK_WDMA_GLO_CFG ,MTK_WDMA_GLO_CFG_RX_INFO3_PRERES ); }else { +int i; +wed_set (dev,MTK_WED_WPDMA_CTRL ,MTK_WED_WPDMA_CTRL_SDL1_FIXED ); +wed_set (dev,MTK_WED_WDMA_GLO_CFG , +MTK_WED_WDMA_GLO_CFG_TX_DRV_EN | +MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK ); +wed_set (dev,MTK_WED_WPDMA_GLO_CFG ,MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC );
@@ -797,6 +1223,15 @@ mtk_wed_dma_enable(struct mtk_wed_device *dev)wed_clr (dev,MTK_WED_WPDMA_GLO_CFG ,MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV ); + +wed_set (dev,MTK_WED_WPDMA_RX_D_GLO_CFG , +MTK_WED_WPDMA_RX_D_RX_DRV_EN | +FIELD_PREP (MTK_WED_WPDMA_RX_D_RXD_READ_LEN ,0x18 ) | +FIELD_PREP (MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL , +0x2 )); + +for (i =0 ; i <MTK_WED_RX_QUEUES ; i++) +mtk_wed_check_wfdma_rx_fill (dev, i); } }
@@ -807,7 +1242,7 @@ mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)for (i =0 ; i <ARRAY_SIZE (dev->tx_wdma); i++)if (!dev->tx_wdma[i].desc) -mtk_wed_wdma_ring_setup (dev, i,16 ); +mtk_wed_wdma_rx_ring_setup (dev, i,16 );mtk_wed_hw_init (dev);mtk_wed_configure_irq (dev, irq_mask);
@@ -822,7 +1257,19 @@ mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask) val |=BIT (0 ) | (BIT (1 ) * !!dev->hw->index);regmap_write (dev->hw->mirror, dev->hw->index *4 , val); }else { -mtk_wed_set_512_support (dev, true); +/* driver set mid ready and only once */ +wed_w32 (dev,MTK_WED_EXT_INT_MASK1 , +MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY ); +wed_w32 (dev,MTK_WED_EXT_INT_MASK2 , +MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY ); + +wed_r32 (dev,MTK_WED_EXT_INT_MASK1 ); +wed_r32 (dev,MTK_WED_EXT_INT_MASK2 ); + +if (mtk_wed_rro_cfg (dev)) +return ; + +mtk_wed_set_512_support (dev, dev->wlan.wcid_512); }mtk_wed_dma_enable (dev);
@@ -856,7 +1303,7 @@ mtk_wed_attach(struct mtk_wed_device *dev)if (!hw) {module_put (THIS_MODULE ); ret = -ENODEV ; - goto out; + goto unlock; } device = dev->wlan.bus_type ==MTK_WED_BUS_PCIE
@@ -869,15 +1316,24 @@ mtk_wed_attach(struct mtk_wed_device *dev) dev->dev = hw->dev; dev->irq = hw->irq; dev->wdma_idx = hw->index; + dev->version = hw->version;if (hw->eth->dma_dev == hw->eth->dev &&of_dma_is_coherent (hw->eth->dev->of_node))mtk_eth_set_dma_device (hw->eth, hw->dev); ret =mtk_wed_buffer_alloc (dev); -if (ret) { -mtk_wed_detach (dev); +if (ret) goto out; + +if (mtk_wed_get_rx_capa (dev)) { + ret =mtk_wed_rx_bm_alloc (dev); +if (ret) + goto out; + + ret =mtk_wed_rro_alloc (dev); +if (ret) + goto out; }mtk_wed_hw_init_early (dev);
@@ -886,8 +1342,10 @@ mtk_wed_attach(struct mtk_wed_device *dev) BIT(hw->index), 0); else ret =mtk_wed_wo_init (hw); - out: +if (ret) +mtk_wed_detach (dev); +unlock:mutex_unlock (&hw_lock);return ret;
@@ -910,13 +1368,14 @@ mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)* WDMA RX. */ -BUG_ON (idx >=ARRAY_SIZE (dev->tx_ring)); +if (WARN_ON (idx >=ARRAY_SIZE (dev->tx_ring))) +return -EINVAL ;if (mtk_wed_ring_alloc (dev, ring,MTK_WED_TX_RING_SIZE , -sizeof (*ring->desc))) +sizeof (*ring->desc), true))return -ENOMEM ; -if (mtk_wed_wdma_ring_setup (dev, idx,MTK_WED_WDMA_RING_SIZE )) +if (mtk_wed_wdma_rx_ring_setup (dev, idx,MTK_WED_WDMA_RING_SIZE ))return -ENOMEM ; ring->reg_base =MTK_WED_RING_TX (idx);
@@ -960,6 +1419,36 @@ mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)return 0 ; } +static int +mtk_wed_rx_ring_setup (struct mtk_wed_device *dev,int idx,void __iomem *regs) +{ +struct mtk_wed_ring *ring = &dev->rx_ring[idx]; + +if (WARN_ON (idx >=ARRAY_SIZE (dev->rx_ring))) +return -EINVAL ; + +if (mtk_wed_ring_alloc (dev, ring,MTK_WED_RX_RING_SIZE , +sizeof (*ring->desc), false)) +return -ENOMEM ; + +if (mtk_wed_wdma_tx_ring_setup (dev, idx,MTK_WED_WDMA_RING_SIZE )) +return -ENOMEM ; + + ring->reg_base =MTK_WED_RING_RX_DATA (idx); + ring->wpdma = regs; + +/* WPDMA -> WED */ +wpdma_rx_w32 (dev, idx,MTK_WED_RING_OFS_BASE , ring->desc_phys); +wpdma_rx_w32 (dev, idx,MTK_WED_RING_OFS_COUNT ,MTK_WED_RX_RING_SIZE ); + +wed_w32 (dev,MTK_WED_WPDMA_RING_RX_DATA (idx) +MTK_WED_RING_OFS_BASE , + ring->desc_phys); +wed_w32 (dev,MTK_WED_WPDMA_RING_RX_DATA (idx) +MTK_WED_RING_OFS_COUNT , +MTK_WED_RX_RING_SIZE ); + +return 0 ; +} +static u32 mtk_wed_irq_get (struct mtk_wed_device *dev,u32 mask) {
@@ -1056,7 +1545,9 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,static const struct mtk_wed_ops wed_ops = { .attach = mtk_wed_attach, .tx_ring_setup = mtk_wed_tx_ring_setup, + .rx_ring_setup = mtk_wed_rx_ring_setup, .txfree_ring_setup = mtk_wed_txfree_ring_setup, + .msg_update = mtk_wed_mcu_msg_update, .start = mtk_wed_start, .stop = mtk_wed_stop, .reset_dma = mtk_wed_reset_dma,
@@ -1065,6 +1556,7 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, .irq_get = mtk_wed_irq_get, .irq_set_mask = mtk_wed_irq_set_mask, .detach = mtk_wed_detach, + .ppe_check = mtk_wed_ppe_check, };struct device_node *eth_np = eth->dev->of_node;struct platform_device *pdev;
drivers/net/ethernet/mediatek/mtk_wed.h +19 -0
@@ -86,6 +86,24 @@ wpdma_tx_w32(struct mtk_wed_device *dev, int ring, u32 reg, u32 val)writel (val, dev->tx_ring[ring].wpdma + reg); } +static inline u32 +wpdma_rx_r32 (struct mtk_wed_device *dev,int ring,u32 reg) +{ +if (!dev->rx_ring[ring].wpdma) +return 0 ; + +return readl (dev->rx_ring[ring].wpdma + reg); +} + +static inline void +wpdma_rx_w32 (struct mtk_wed_device *dev,int ring,u32 reg,u32 val) +{ +if (!dev->rx_ring[ring].wpdma) +return ; + +writel (val, dev->rx_ring[ring].wpdma + reg); +} +static inline u32 wpdma_txfree_r32 (struct mtk_wed_device *dev,u32 reg) {
@@ -128,6 +146,7 @@ static inline int mtk_wed_flow_add(int index)static inline void mtk_wed_flow_remove (int index) { } +#endif #ifdef CONFIG_DEBUG_FS
drivers/net/ethernet/mediatek/mtk_wed_mcu.c +37 -8
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drivers/net/ethernet/mediatek/mtk_wed_regs.h +126 -2
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drivers/net/ethernet/mediatek/mtk_wed_wo.h +28 -0
@@ -49,6 +49,10 @@ enum { MTK_WED_WARP_CMD_FLAG_FROM_TO_WO = BIT(2), }; +#define MTK_WED_WO_CPU_MCUSYS_RESET_ADDR 0x15194050 +#define MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK 0x20 +#define MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK 0x1 +enum {MTK_WED_WO_REGION_EMI ,MTK_WED_WO_REGION_ILM ,
@@ -56,6 +60,28 @@ enum { __MTK_WED_WO_REGION_MAX, }; +enum mtk_wed_wo_state { +MTK_WED_WO_STATE_UNDEFINED , +MTK_WED_WO_STATE_INIT , +MTK_WED_WO_STATE_ENABLE , +MTK_WED_WO_STATE_DISABLE , +MTK_WED_WO_STATE_HALT , +MTK_WED_WO_STATE_GATING , +MTK_WED_WO_STATE_SER_RESET , +MTK_WED_WO_STATE_WF_RESET , +}; + +enum mtk_wed_wo_done_state { +MTK_WED_WOIF_UNDEFINED , +MTK_WED_WOIF_DISABLE_DONE , +MTK_WED_WOIF_TRIGGER_ENABLE , +MTK_WED_WOIF_ENABLE_DONE , +MTK_WED_WOIF_TRIGGER_GATING , +MTK_WED_WOIF_GATING_DONE , +MTK_WED_WOIF_TRIGGER_HALT , +MTK_WED_WOIF_HALT_DONE , +}; +enum mtk_wed_dummy_cr_idx {MTK_WED_DUMMY_CR_FWDL ,MTK_WED_DUMMY_CR_WO_STATUS ,
@@ -250,6 +276,8 @@ void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo, struct sk_buff *skb);int mtk_wed_mcu_send_msg (struct mtk_wed_wo *wo,int id,int cmd,const void *data,int len,bool wait_resp); +int mtk_wed_mcu_msg_update (struct mtk_wed_device *dev,int id,void *data, +int len);int mtk_wed_mcu_init (struct mtk_wed_wo *wo);int mtk_wed_wo_init (struct mtk_wed_hw *hw);void mtk_wed_wo_deinit (struct mtk_wed_hw *hw);
include/linux/soc/mediatek/mtk_wed.h +74 -1
160 lines not on this page · raw message
Signature · 1 line
2.37.3
Lorenzo Bianconi
maintainerPATCH v2 6/6 net: ethernet: mtk_wed: add rx mib counters
In reply to Lorenzo BianconiIntroduce WED RX MIB counters support available on MT7986a SoC.
Tested-by Daniel Golle <[email protected]>
Co-developed-by Sujuan Chen <[email protected]>
Signed-off-by Sujuan Chen <[email protected]>
Signed-off-by Lorenzo Bianconi <[email protected]>
--- .../net/ethernet/mediatek/mtk_wed_debugfs.c | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+)
drivers/net/ethernet/mediatek/mtk_wed_debugfs.c +87 -0
@@ -2,6 +2,7 @@/* Copyright (C) 2021 Felix Fietkau <[email protected]> */ #include <linux/seq_file.h> +#include <linux/soc/mediatek/mtk_wed.h> #include "mtk_wed.h" #include "mtk_wed_regs.h"
@@ -18,6 +19,8 @@ enum {DUMP_TYPE_WDMA ,DUMP_TYPE_WPDMA_TX ,DUMP_TYPE_WPDMA_TXFREE , +DUMP_TYPE_WPDMA_RX , + DUMP_TYPE_WED_RRO, };#define DUMP_STR (_str) { _str, 0, DUMP_TYPE_STRING }
@@ -36,6 +39,9 @@ enum {#define DUMP_WPDMA_TX_RING (_n) DUMP_RING("WPDMA_TX" #_n, 0, DUMP_TYPE_WPDMA_TX, _n)#define DUMP_WPDMA_TXFREE_RING DUMP_RING("WPDMA_RX1", 0, DUMP_TYPE_WPDMA_TXFREE) +#define DUMP_WPDMA_RX_RING (_n) DUMP_RING("WPDMA_RX" #_n, 0, DUMP_TYPE_WPDMA_RX, _n) +#define DUMP_WED_RRO_RING (_base)DUMP_RING("WED_RRO_MIOD", MTK_##_base, DUMP_TYPE_WED_RRO) +#define DUMP_WED_RRO_FDBK (_base)DUMP_RING("WED_RRO_FDBK", MTK_##_base, DUMP_TYPE_WED_RRO)static void print_reg_val (struct seq_file *s,const char *name,u32 val)
@@ -57,6 +63,7 @@ dump_wed_regs(struct seq_file *s, struct mtk_wed_device *dev, cur > regs ?"\n" :"" , cur->name);continue ; +case DUMP_TYPE_WED_RRO :case DUMP_TYPE_WED : val =wed_r32 (dev, cur->offset);break ;
@@ -69,6 +76,9 @@ dump_wed_regs(struct seq_file *s, struct mtk_wed_device *dev,case DUMP_TYPE_WPDMA_TXFREE : val =wpdma_txfree_r32 (dev, cur->offset);break ; +case DUMP_TYPE_WPDMA_RX : + val =wpdma_rx_r32 (dev, cur->base, cur->offset); +break ; }print_reg_val (s, cur->name, val); }
@@ -132,6 +142,80 @@ wed_txinfo_show(struct seq_file *s, void *data) }DEFINE_SHOW_ATTRIBUTE (wed_txinfo); +static int +wed_rxinfo_show (struct seq_file *s,void *data) +{ +static const struct reg_dump regs[] = { +DUMP_STR ("WPDMA RX" ), +DUMP_WPDMA_RX_RING (0 ), +DUMP_WPDMA_RX_RING (1 ), + +DUMP_STR ("WPDMA RX" ), +DUMP_WED (WED_WPDMA_RX_D_MIB (0 )), +DUMP_WED_RING (WED_WPDMA_RING_RX_DATA (0 )), +DUMP_WED (WED_WPDMA_RX_D_PROCESSED_MIB (0 )), +DUMP_WED (WED_WPDMA_RX_D_MIB (1 )), +DUMP_WED_RING (WED_WPDMA_RING_RX_DATA (1 )), +DUMP_WED (WED_WPDMA_RX_D_PROCESSED_MIB (1 )), +DUMP_WED (WED_WPDMA_RX_D_COHERENT_MIB ), + +DUMP_STR ("WED RX" ), +DUMP_WED_RING (WED_RING_RX_DATA (0 )), +DUMP_WED_RING (WED_RING_RX_DATA (1 )), + +DUMP_STR ("WED RRO" ), +DUMP_WED_RRO_RING (WED_RROQM_MIOD_CTRL0 ), +DUMP_WED (WED_RROQM_MID_MIB ), +DUMP_WED (WED_RROQM_MOD_MIB ), +DUMP_WED (WED_RROQM_MOD_COHERENT_MIB ), +DUMP_WED_RRO_FDBK (WED_RROQM_FDBK_CTRL0 ), +DUMP_WED (WED_RROQM_FDBK_IND_MIB ), +DUMP_WED (WED_RROQM_FDBK_ENQ_MIB ), +DUMP_WED (WED_RROQM_FDBK_ANC_MIB ), +DUMP_WED (WED_RROQM_FDBK_ANC2H_MIB ), + +DUMP_STR ("WED Route QM" ), +DUMP_WED (WED_RTQM_R2H_MIB (0 )), +DUMP_WED (WED_RTQM_R2Q_MIB (0 )), +DUMP_WED (WED_RTQM_Q2H_MIB (0 )), +DUMP_WED (WED_RTQM_R2H_MIB (1 )), +DUMP_WED (WED_RTQM_R2Q_MIB (1 )), +DUMP_WED (WED_RTQM_Q2H_MIB (1 )), +DUMP_WED (WED_RTQM_Q2N_MIB ), +DUMP_WED (WED_RTQM_Q2B_MIB ), +DUMP_WED (WED_RTQM_PFDBK_MIB ), + +DUMP_STR ("WED WDMA TX" ), +DUMP_WED (WED_WDMA_TX_MIB ), +DUMP_WED_RING (WED_WDMA_RING_TX ), + +DUMP_STR ("WDMA TX" ), +DUMP_WDMA (WDMA_GLO_CFG ), +DUMP_WDMA_RING (WDMA_RING_TX (0 )), +DUMP_WDMA_RING (WDMA_RING_TX (1 )), + +DUMP_STR ("WED RX BM" ), +DUMP_WED (WED_RX_BM_BASE ), +DUMP_WED (WED_RX_BM_RX_DMAD ), +DUMP_WED (WED_RX_BM_PTR ), +DUMP_WED (WED_RX_BM_TKID_MIB ), +DUMP_WED (WED_RX_BM_BLEN ), +DUMP_WED (WED_RX_BM_STS ), +DUMP_WED (WED_RX_BM_INTF2 ), +DUMP_WED (WED_RX_BM_INTF ), +DUMP_WED (WED_RX_BM_ERR_STS ), + }; +struct mtk_wed_hw *hw = s->private; +struct mtk_wed_device *dev = hw->wed_dev; + +if (!dev) +return 0 ; + +dump_wed_regs (s, dev, regs,ARRAY_SIZE (regs)); + +return 0 ; +} +DEFINE_SHOW_ATTRIBUTE (wed_rxinfo);static int mtk_wed_reg_set (void *data,u64 val)
@@ -175,4 +259,7 @@ void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw)debugfs_create_u32 ("regidx" ,0600 , dir, &hw->debugfs_reg);debugfs_create_file_unsafe ("regval" ,0600 , dir, hw, &fops_regval);debugfs_create_file_unsafe ("txinfo" ,0400 , dir, hw, &wed_txinfo_fops); +if (hw->version !=1 ) +debugfs_create_file_unsafe ("rxinfo" ,0400 , dir, hw, + &wed_rxinfo_fops); }
Signature · 1 line
2.37.3