introduce WED RX support to MT7986 SoC

Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet Dispatch to offload traffic received by the wlan interface to lan/wan one.

Co-developed-by Sujuan Chen <[email protected]>

Signed-off-by Sujuan Chen <[email protected]>

Signed-off-by Lorenzo Bianconi <[email protected]>

---
  arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 75 +++++++++++++++++++++++
  1 file changed, 75 insertions(+)

arch/arm64/boot/dts/mediatek/mt7986a.dtsi +0 -0

index 72e0d9722e07..b0a593c6020e 100644

Il 03/11/22 10:28, Lorenzo Bianconi ha scritto:

Quoted 7 lines

Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet Dispatch to offload traffic received by the wlan interface to lan/wan one.

Co-developed-by Sujuan Chen <[email protected]>

Signed-off-by Sujuan Chen <[email protected]>

Signed-off-by Lorenzo Bianconi <[email protected]>

Hello Lorenzo,
thanks for the patch! However, there's something to improve...

Quoted 8 lines

---
  arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 75 +++++++++++++++++++++++
  1 file changed, 75 insertions(+)

arch/arm64/boot/dts/mediatek/mt7986a.dtsi +0 -0

index 72e0d9722e07..b0a593c6020e 100644

..snip..

arch/arm64/boot/dts/mediatek/mt7986a.dtsi ethsys: syscon@15000000 { · line 256

Quoted 6 lines

arch/arm64/boot/dts/mediatek/mt7986a.dtsi +2 -0

@@ -226,6 +252,12 @@ ethsys: syscon@15000000 {
  			 reg = <0 0x15000000 0 0x1000>;
  			 #clock-cells = <1>;
  			 #reset-cells = <1>;
+
+			ethsysrst: reset-controller {

That's not right. It works, yes, but your ethsys rightfully declares #reset-cells, because it is supposed to also be a reset controller (even though I don't see any reset controller registering action in clk-mt7986-eth.c).

Please document the ethernet reset in the appropriate dt-bindings header and register the reset controller in clk-mt7986-eth.c.

Finally, you won't need any "ti,syscon-reset" node, and resets will look like

	resets = <&ethsys MT7986_ETHSYS_SOMETHING_SWRST>;

If you need any hint about how to do that, please check clk-mt8195-infra_ao.c.

Regards,
Angelo

Il 03/11/22 10:28, Lorenzo Bianconi ha scritto:

Quoted 7 lines

Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet Dispatch to offload traffic received by the wlan interface to lan/wan one.

Co-developed-by Sujuan Chen <[email protected]>

Signed-off-by Sujuan Chen <[email protected]>

Signed-off-by Lorenzo Bianconi <[email protected]>

Hello Lorenzo,

thanks for the patch! However, there's something to improve...

Quoted 8 lines

---
  arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 75 +++++++++++++++++++++++
  1 file changed, 75 insertions(+)

arch/arm64/boot/dts/mediatek/mt7986a.dtsi +0 -0

index 72e0d9722e07..b0a593c6020e 100644

..snip..

arch/arm64/boot/dts/mediatek/mt7986a.dtsi ethsys: syscon@15000000 { · line 256

Quoted 6 lines

arch/arm64/boot/dts/mediatek/mt7986a.dtsi +2 -0

@@ -226,6 +252,12 @@ ethsys: syscon@15000000 {
  			 reg = <0 0x15000000 0 0x1000>;
  			 #clock-cells = <1>;
  			 #reset-cells = <1>;
+
+			ethsysrst: reset-controller {

That's not right. It works, yes, but your ethsys rightfully declares #reset-cells, because it is supposed to also be a reset controller (even though I don't see any reset controller registering action in clk-mt7986-eth.c).

Please document the ethernet reset in the appropriate dt-bindings header and register the reset controller in clk-mt7986-eth.c.

Finally, you won't need any "ti,syscon-reset" node, and resets will look like

	resets = <&ethsys MT7986_ETHSYS_SOMETHING_SWRST>;

If you need any hint about how to do that, please check clk-mt8195-infra_ao.c.

Regards,
Angelo

Quoted 10 lines

Il 03/11/22 10:28, Lorenzo Bianconi ha scritto:

Quoted 7 lines

Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet Dispatch to offload traffic received by the wlan interface to lan/wan one.

Co-developed-by Sujuan Chen <[email protected]>

Signed-off-by Sujuan Chen <[email protected]>

Signed-off-by Lorenzo Bianconi <[email protected]>

Hello Lorenzo,

Hi Angelo,

Quoted 29 lines

thanks for the patch! However, there's something to improve...

Quoted 8 lines

---
   arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 75 +++++++++++++++++++++++
   1 file changed, 75 insertions(+)

arch/arm64/boot/dts/mediatek/mt7986a.dtsi +0 -0

index 72e0d9722e07..b0a593c6020e 100644

..snip..

arch/arm64/boot/dts/mediatek/mt7986a.dtsi ethsys: syscon@15000000 { · line 256

Quoted 6 lines

arch/arm64/boot/dts/mediatek/mt7986a.dtsi +2 -0

@@ -226,6 +252,12 @@ ethsys: syscon@15000000 {
   			 reg = <0 0x15000000 0 0x1000>;
   			 #clock-cells = <1>;
   			 #reset-cells = <1>;
+
+			ethsysrst: reset-controller {

That's not right. It works, yes, but your ethsys rightfully declares #reset-cells, because it is supposed to also be a reset controller (even though I don't see any reset controller registering action in clk-mt7986-eth.c).

Please document the ethernet reset in the appropriate dt-bindings header and register the reset controller in clk-mt7986-eth.c.

Finally, you won't need any "ti,syscon-reset" node, and resets will look like

Quoted 3 lines

	resets = <&ethsys MT7986_ETHSYS_SOMETHING_SWRST>;

If you need any hint about how to do that, please check clk-mt8195-infra_ao.c.

reviewing the code I think we do not have any mt7986-eth reset line consumer at the moment, since:
- mtk_eth_soc driver rely on syscon for resetting the chip writing directly in the register in ethsys_reset()

- we do not rely on reset api in wed wo code.

I think we can just drop reset support in ethsys/wo-dlm nodes at the moment (since it is not used in this series) and convert the driver to reset api as soon as we have proper support in clk-mt7986-eth.c (AFAIU sam will work on it).

Document the binding for the RX Wireless Ethernet Dispatch core on the MT7986 ethernet driver used to offload traffic received by WLAN NIC and forwarded to LAN/WAN one.

Signed-off-by Lorenzo Bianconi <[email protected]>

---
 .../arm/mediatek/mediatek,mt7622-wed.yaml     | 62 ++++++++++++++++++-
 .../arm/mediatek/mediatek,mt7986-wo-boot.yaml | 47 ++++++++++++++
 .../arm/mediatek/mediatek,mt7986-wo-ccif.yaml | 50 +++++++++++++++
 .../arm/mediatek/mediatek,mt7986-wo-dlm.yaml  | 50 +++++++++++++++
 4 files changed, 206 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +0 -0

index 84fb0a146b6e..9e34c5d15cec 100644

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +5 -0

+      - description:
+          Phandle for the node used to run firmware ILM region
+      - description:
+          Phandle for the node used to run firmware CPU DATA region
+

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +15 -0

+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: mediatek,mt7622-wed
+    then:
+      properties:
+        memory-region-names: false
+        memory-region: false
+        mediatek,wo-boot: false
+        mediatek,wo-ccif: false
+        mediatek,wo-dlm: false
+
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +6 -0

@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-boot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +31 -0

+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt7986-wo-boot
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_boot: syscon@15194000 {
+        compatible = "mediatek,mt7986-wo-boot", "syscon";
+        reg = <0 0x15194000 0 0x1000>;
+      };
+    };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +5 -0

new file mode 100644
index 000000000000..6357a206587a
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-ccif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +35 -0

+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt7986-wo-ccif
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_ccif0: syscon@151a5000 {
+        compatible = "mediatek,mt7986-wo-ccif", "syscon";
+        reg = <0 0x151a5000 0 0x1000>;
+        interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+      };
+    };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file +34 -0

new file mode 100644
index 000000000000..a499956d9e07
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-dlm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Wireless Ethernet Dispatch WO hw rx ring interface for MT7986
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-dlm provides a configuration interface for WED WO
+  rx ring on MT7986 soc.
+
+properties:
+  compatible:
+    const: mediatek,mt7986-wo-dlm
+
+  reg:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - resets
+  - reset-names

Quoted 15 lines

Document the binding for the RX Wireless Ethernet Dispatch core on the MT7986 ethernet driver used to offload traffic received by WLAN NIC and forwarded to LAN/WAN one.

Signed-off-by Lorenzo Bianconi <[email protected]>

---
 .../arm/mediatek/mediatek,mt7622-wed.yaml     | 62 ++++++++++++++++++-
 .../arm/mediatek/mediatek,mt7986-wo-boot.yaml | 47 ++++++++++++++
 .../arm/mediatek/mediatek,mt7986-wo-ccif.yaml | 50 +++++++++++++++
 .../arm/mediatek/mediatek,mt7986-wo-dlm.yaml  | 50 +++++++++++++++
 4 files changed, 206 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml line 5

Quoted 12 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +2 -2

index 84fb0a146b6e..9e34c5d15cec 100644
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#

Split the cleanups from essential/functional changes.

Quoted 8 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +0 -0

 title: MediaTek Wireless Ethernet Dispatch Controller for MT7622
 

@@ -29,6 +29,50 @@ properties:
   interrupts:
     maxItems: 1
 

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml properties: · line 35

Quoted 4 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +4 -0

+  memory-region:
+    items:
+      - description:
+          Phandle for the node used to run firmware EMI region

Merge above two lines. Drop "phandle for the node used to run"

Quoted 10 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +9 -0

+      - description:
+          Phandle for the node used to run firmware ILM region
+      - description:
+          Phandle for the node used to run firmware CPU DATA region
+
+  memory-region-names:
+    items:
+      - const: wo-emi
+      - const: wo-ilm

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml properties: · line 50

Quoted 6 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +6 -0

+      - const: wo-data
+
+  mediatek,wo-ccif:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the mediatek wed-wo controller.

Drop "Phandle to". Same in other cases.

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml properties: · line 60

Quoted 11 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +10 -0

+
+  mediatek,wo-boot:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the mediatek wed-wo boot interface.
+
+  mediatek,wo-dlm:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the mediatek wed-wo rx hw ring.

rx->RX?
hw->HW?

Quoted 25 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +16 -1

+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: mediatek,mt7622-wed
+    then:
+      properties:
+        memory-region-names: false
+        memory-region: false
+        mediatek,wo-boot: false
+        mediatek,wo-ccif: false
+        mediatek,wo-dlm: false
+
 required:
   - compatible
   - reg

@@ -44,8 +88,20 @@ examples:
       #address-cells = <2>;
       #size-cells = <2>;
       wed0: wed@1020a000 {
-        compatible = "mediatek,mt7622-wed","syscon";
+        compatible = "mediatek,mt7622-wed", "syscon";

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml examples: · line 96

Quoted 5 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +2 -0

         reg = <0 0x1020a000 0 0x1000>;
         interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;
       };
+
+      wed1: wed@15010000 {

That's a separate example. - |
Drop wed1 label.

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml examples: · line 97

Quoted 2 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +1 -0

+        compatible = "mediatek,mt7986-wed", "syscon";

And where is the compatible added?

Quoted 10 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +9 -0

+        reg = <0 0x15010000 0 0x1000>;
+        interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+
+        memory-region = <&wo_emi>, <&wo_data>, <&wo_ilm>;
+        memory-region-names = "wo-emi", "wo-ilm", "wo-data";
+        mediatek,wo-ccif = <&wo_ccif0>;
+        mediatek,wo-boot = <&wo_boot>;
+        mediatek,wo-dlm = <&wo_dlm0>;
+      };
     };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml

Quoted 5 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +0 -0

new file mode 100644
index 000000000000..6c3c514c48ef

arm is only for top-level stuff. Choose appropriate subsystem, soc as last resort.

Quoted 12 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +10 -0

@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-boot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title:
+  MediaTek Wireless Ethernet Dispatch WO boot controller interface for MT7986
+
+maintainers:

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml line 16

Quoted 6 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +6 -0

+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-boot provides a configuration interface for WED WO
+  boot controller on MT7986 soc.

And what is "WED WO boot controller?

Quoted 43 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +31 -0

+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt7986-wo-boot
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_boot: syscon@15194000 {
+        compatible = "mediatek,mt7986-wo-boot", "syscon";
+        reg = <0 0x15194000 0 0x1000>;
+      };
+    };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +5 -0

new file mode 100644
index 000000000000..6357a206587a
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-ccif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml line 15

Quoted 10 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +10 -0

+
+title: MediaTek Wireless Ethernet Dispatch WO controller interface for MT7986
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-ccif provides a configuration interface for WED WO
+  controller on MT7986 soc.

All previous comments apply.

Quoted 80 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +35 -0

+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt7986-wo-ccif
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_ccif0: syscon@151a5000 {
+        compatible = "mediatek,mt7986-wo-ccif", "syscon";
+        reg = <0 0x151a5000 0 0x1000>;
+        interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+      };
+    };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file +39 -0

new file mode 100644
index 000000000000..a499956d9e07
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-dlm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Wireless Ethernet Dispatch WO hw rx ring interface for MT7986
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-dlm provides a configuration interface for WED WO
+  rx ring on MT7986 soc.
+
+properties:
+  compatible:
+    const: mediatek,mt7986-wo-dlm
+
+  reg:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml line 44

Quoted 5 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file +5 -0

+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_dlm0: wo-dlm@151e8000 {

Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

Best regards,
Krzysztof

Quoted 8 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml

Quoted 5 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +0 -0

new file mode 100644
index 000000000000..6c3c514c48ef

arm is only for top-level stuff. Choose appropriate subsystem, soc as last resort.

these chips are used only for networking so is net folder fine?

Quoted 13 lines

Quoted 13 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +10 -0

@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-boot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title:
+  MediaTek Wireless Ethernet Dispatch WO boot controller interface for MT7986
+
+maintainers:

Quoted 8 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml line 16

Quoted 6 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +6 -0

+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-boot provides a configuration interface for WED WO
+  boot controller on MT7986 soc.

And what is "WED WO boot controller?

WED WO is a chip used for networking packet processing offloaded to the Soc (e.g. packet reordering). WED WO boot is the memory used to store start address of wo firmware. Anyway I will let Sujuan comment on this.

Quoted 137 lines

Quoted 44 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +31 -0

+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt7986-wo-boot
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_boot: syscon@15194000 {
+        compatible = "mediatek,mt7986-wo-boot", "syscon";
+        reg = <0 0x15194000 0 0x1000>;
+      };
+    };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +5 -0

new file mode 100644
index 000000000000..6357a206587a
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-ccif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml line 15

Quoted 10 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +10 -0

+
+title: MediaTek Wireless Ethernet Dispatch WO controller interface for MT7986
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-ccif provides a configuration interface for WED WO
+  controller on MT7986 soc.

All previous comments apply.

Quoted 80 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +35 -0

+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt7986-wo-ccif
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_ccif0: syscon@151a5000 {
+        compatible = "mediatek,mt7986-wo-ccif", "syscon";
+        reg = <0 0x151a5000 0 0x1000>;
+        interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+      };
+    };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file +39 -0

new file mode 100644
index 000000000000..a499956d9e07
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-dlm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Wireless Ethernet Dispatch WO hw rx ring interface for MT7986
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-dlm provides a configuration interface for WED WO
+  rx ring on MT7986 soc.
+
+properties:
+  compatible:
+    const: mediatek,mt7986-wo-dlm
+
+  reg:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |

Quoted 8 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml line 44

Quoted 5 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file +5 -0

+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_dlm0: wo-dlm@151e8000 {

Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

DLM is a chip used to store the data rx ring of wo firmware. I do not have a better node name (naming is always hard). Can you please suggest a better name?

Quoted 5 lines

Quoted 5 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml

Quoted 5 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +0 -0

new file mode 100644
index 000000000000..6c3c514c48ef

Quoted 5 lines

Quoted 3 lines

arm is only for top-level stuff. Choose appropriate subsystem, soc as last resort.

these chips are used only for networking so is net folder fine?

So this is some MMIO and no actual device? Then rather soc.

Quoted 23 lines

Quoted 22 lines

Quoted 10 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +6 -0

@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-boot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml line 16

Quoted 10 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +10 -0

+title:
+  MediaTek Wireless Ethernet Dispatch WO boot controller interface for MT7986
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-boot provides a configuration interface for WED WO
+  boot controller on MT7986 soc.

And what is "WED WO boot controller?

Quoted 3 lines

WED WO is a chip used for networking packet processing offloaded to the Soc (e.g. packet reordering). WED WO boot is the memory used to store start address of wo firmware. Anyway I will let Sujuan comment on this.

A bit more should be in description.

Quoted 147 lines

Quoted 146 lines

Quoted 45 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +31 -0

+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt7986-wo-boot
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_boot: syscon@15194000 {
+        compatible = "mediatek,mt7986-wo-boot", "syscon";
+        reg = <0 0x15194000 0 0x1000>;
+      };
+    };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +5 -0

new file mode 100644
index 000000000000..6357a206587a
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-ccif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml line 15

Quoted 10 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +10 -0

+
+title: MediaTek Wireless Ethernet Dispatch WO controller interface for MT7986
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-ccif provides a configuration interface for WED WO
+  controller on MT7986 soc.

All previous comments apply.

Quoted 75 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +35 -0

+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt7986-wo-ccif
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_ccif0: syscon@151a5000 {
+        compatible = "mediatek,mt7986-wo-ccif", "syscon";
+        reg = <0 0x151a5000 0 0x1000>;
+        interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+      };
+    };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file +34 -0

new file mode 100644
index 000000000000..a499956d9e07
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-dlm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Wireless Ethernet Dispatch WO hw rx ring interface for MT7986
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-dlm provides a configuration interface for WED WO
+  rx ring on MT7986 soc.
+
+properties:
+  compatible:
+    const: mediatek,mt7986-wo-dlm
+
+  reg:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - resets
+  - reset-names

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml line 44

Quoted 10 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file +10 -0

+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_dlm0: wo-dlm@151e8000 {

Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

Quoted 2 lines

DLM is a chip used to store the data rx ring of wo firmware. I do not have a better node name (naming is always hard). Can you please suggest a better name?

The problem is that you added three new devices which seem to be for the same device - WED. It looks like some hacky way of avoid proper hardware description - let's model everything as MMIO and syscons...

For such model - register addresses exposed as separate devices - I do not have appropriate name, but the real problem is not in the name. It's in the hardware description.

Best regards,
Krzysztof

Quoted 6 lines · Lorenzo Bianconi

Quoted 5 lines

Quoted 5 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml

Quoted 5 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +0 -0

new file mode 100644
index 000000000000..6c3c514c48ef

Regarding "mediatek,mt7986-wed" compatible string it has been added to mt7986a.dtsi in the commit below:

commit 00b9903996b3e1e287c748928606d738944e45de

Author: Lorenzo Bianconi <[email protected]>
Date:   Tue Sep 20 12:11:13 2022 +0200

arm64: dts: mediatek: mt7986: add support for Wireless Ethernet Dispatch

Quoted 7 lines

Quoted 5 lines

Quoted 3 lines

arm is only for top-level stuff. Choose appropriate subsystem, soc as last resort.

these chips are used only for networking so is net folder fine?

So this is some MMIO and no actual device? Then rather soc.

ack, I will move them there

Quoted 23 lines

Quoted 23 lines

Quoted 22 lines

Quoted 10 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +6 -0

@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-boot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml line 16

Quoted 10 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +10 -0

+title:
+  MediaTek Wireless Ethernet Dispatch WO boot controller interface for MT7986
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-boot provides a configuration interface for WED WO
+  boot controller on MT7986 soc.

And what is "WED WO boot controller?

Quoted 5 lines

Quoted 3 lines

WED WO is a chip used for networking packet processing offloaded to the Soc (e.g. packet reordering). WED WO boot is the memory used to store start address of wo firmware. Anyway I will let Sujuan comment on this.

A bit more should be in description.

I will let Sujuan adding more details (since I do not have them :))

Quoted 150 lines

Quoted 149 lines

Quoted 138 lines

Quoted 45 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +31 -0

+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt7986-wo-boot
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_boot: syscon@15194000 {
+        compatible = "mediatek,mt7986-wo-boot", "syscon";
+        reg = <0 0x15194000 0 0x1000>;
+      };
+    };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +5 -0

new file mode 100644
index 000000000000..6357a206587a
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-ccif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml line 15

Quoted 10 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +10 -0

+
+title: MediaTek Wireless Ethernet Dispatch WO controller interface for MT7986
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-ccif provides a configuration interface for WED WO
+  controller on MT7986 soc.

All previous comments apply.

Quoted 80 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +35 -0

+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt7986-wo-ccif
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_ccif0: syscon@151a5000 {
+        compatible = "mediatek,mt7986-wo-ccif", "syscon";
+        reg = <0 0x151a5000 0 0x1000>;
+        interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+      };
+    };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file +39 -0

new file mode 100644
index 000000000000..a499956d9e07
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-dlm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Wireless Ethernet Dispatch WO hw rx ring interface for MT7986
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-dlm provides a configuration interface for WED WO
+  rx ring on MT7986 soc.
+
+properties:
+  compatible:
+    const: mediatek,mt7986-wo-dlm
+
+  reg:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |

Quoted 8 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml line 44

Quoted 5 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file +5 -0

+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_dlm0: wo-dlm@151e8000 {

Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

DLM is a chip used to store the data rx ring of wo firmware. I do not have a better node name (naming is always hard). Can you please suggest a better name?

Quoted 3 lines

The problem is that you added three new devices which seem to be for the same device - WED. It looks like some hacky way of avoid proper hardware description - let's model everything as MMIO and syscons...

is it fine to use syscon as node name even if we do not declare it in compatible string for dlm?

Quoted 211 lines

Quoted 6 lines · Lorenzo Bianconi

Quoted 5 lines

Quoted 5 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml

Quoted 5 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +0 -0

new file mode 100644
index 000000000000..6c3c514c48ef

Regarding "mediatek,mt7986-wed" compatible string it has been added to mt7986a.dtsi in the commit below:

commit 00b9903996b3e1e287c748928606d738944e45de

Author: Lorenzo Bianconi <[email protected]>
Date:   Tue Sep 20 12:11:13 2022 +0200

arm64: dts: mediatek: mt7986: add support for Wireless Ethernet Dispatch

Quoted 7 lines

Quoted 5 lines

Quoted 3 lines

arm is only for top-level stuff. Choose appropriate subsystem, soc as last resort.

these chips are used only for networking so is net folder fine?

So this is some MMIO and no actual device? Then rather soc.

ack, I will move them there

Quoted 23 lines

Quoted 23 lines

Quoted 22 lines

Quoted 10 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +6 -0

@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-boot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml line 16

Quoted 10 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +10 -0

+title:
+  MediaTek Wireless Ethernet Dispatch WO boot controller interface for MT7986
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-boot provides a configuration interface for WED WO
+  boot controller on MT7986 soc.

And what is "WED WO boot controller?

Quoted 5 lines

Quoted 3 lines

WED WO is a chip used for networking packet processing offloaded to the Soc (e.g. packet reordering). WED WO boot is the memory used to store start address of wo firmware. Anyway I will let Sujuan comment on this.

A bit more should be in description.

I will let Sujuan adding more details (since I do not have them :))

Quoted 153 lines

Quoted 147 lines

Quoted 138 lines

Quoted 45 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +31 -0

+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt7986-wo-boot
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_boot: syscon@15194000 {
+        compatible = "mediatek,mt7986-wo-boot", "syscon";
+        reg = <0 0x15194000 0 0x1000>;
+      };
+    };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +5 -0

new file mode 100644
index 000000000000..6357a206587a
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-ccif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml line 15

Quoted 10 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +10 -0

+
+title: MediaTek Wireless Ethernet Dispatch WO controller interface for MT7986
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-ccif provides a configuration interface for WED WO
+  controller on MT7986 soc.

All previous comments apply.

Quoted 80 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +35 -0

+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt7986-wo-ccif
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_ccif0: syscon@151a5000 {
+        compatible = "mediatek,mt7986-wo-ccif", "syscon";
+        reg = <0 0x151a5000 0 0x1000>;
+        interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+      };
+    };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file +39 -0

new file mode 100644
index 000000000000..a499956d9e07
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-dlm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Wireless Ethernet Dispatch WO hw rx ring interface for MT7986
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-dlm provides a configuration interface for WED WO
+  rx ring on MT7986 soc.
+
+properties:
+  compatible:
+    const: mediatek,mt7986-wo-dlm
+
+  reg:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |

Quoted 8 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml line 44

Quoted 5 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file +5 -0

+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_dlm0: wo-dlm@151e8000 {

Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

Quoted 2 lines

DLM is a chip used to store the data rx ring of wo firmware. I do not have a better node name (naming is always hard). Can you please suggest a better name?

The problem is that you added three new devices which seem to be for the same device - WED. It looks like some hacky way of avoid proper hardware description - let's model everything as MMIO and syscons...

Quoted 3 lines

is it fine to use syscon as node name even if we do not declare it in compatible string for dlm?

No, rather not. It's a shortcut and if used without actual syscon it would be confusing. You could still call it system-controller, though.

Best regards,
Krzysztof

Quoted 70 lines · Lorenzo Bianconi

Quoted 12 lines · Lorenzo Bianconi

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diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,m t7986-wo-boot.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,m t7986-wo-boot.yaml
new file mode 100644
index 000000000000..6c3c514c48ef
--- /dev/null
+++
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,m t7986-wo-boot.yaml

Regarding "mediatek,mt7986-wed" compatible string it has been added to
mt7986a.dtsi in the commit below:

commit 00b9903996b3e1e287c748928606d738944e45de

Author: Lorenzo Bianconi <[email protected]>
Date:   Tue Sep 20 12:11:13 2022 +0200

arm64: dts: mediatek: mt7986: add support for Wireless Ethernet Dispatch

Quoted 8 lines

Quoted 6 lines

Quoted 4 lines

arm is only for top-level stuff. Choose appropriate subsystem, soc as
last resort.

these chips are used only for networking so is net folder fine?

So this is some MMIO and no actual device? Then rather soc.

ack, I will move them there

Quoted 35 lines

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Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +4 -0

@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: 

https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-boot.yaml*__;Iw!!CTRNKA9wMg0ARbw!zwfPbJpcAbOIOvolZM17U38coXpSGcUDmLW5g8m4760Crj_jruCb42rt9lXOq8svAEM$

+$schema:
https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!zwfPbJpcAbOIOvolZM17U38coXpSGcUDmLW5g8m4760Crj_jruCb42rt9lXOpl37_FI$

Quoted 15 lines

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Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +3 -0

+
+title:
+  MediaTek Wireless Ethernet Dispatch WO boot controller

interface for MT7986

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +7 -0

+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-boot provides a configuration interface

Quoted 2 lines

for WED WO
+ boot controller on MT7986 soc.

And what is "WED WO boot controller?

WED WO is a chip used for networking packet processing offloaded to the Soc
(e.g. packet reordering). WED WO boot is the memory used to store start address
of wo firmware. Anyway I will let Sujuan comment on this.

Quoted 4 lines

Quoted 1 line

A bit more should be in description.

I will let Sujuan adding more details (since I do not have them :))

Quoted 162 lines

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Quoted 65 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +31 -0

+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt7986-wo-boot
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_boot: syscon@15194000 {
+        compatible = "mediatek,mt7986-wo-boot", "syscon";
+        reg = <0 0x15194000 0 0x1000>;
+      };
+    };

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,m t7986-wo-ccif.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,m t7986-wo-ccif.yaml
new file mode 100644
index 000000000000..6357a206587a
--- /dev/null
+++
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,m t7986-wo-ccif.yaml

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +4 -0

@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: 

https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-ccif.yaml*__;Iw!!CTRNKA9wMg0ARbw!zwfPbJpcAbOIOvolZM17U38coXpSGcUDmLW5g8m4760Crj_jruCb42rt9lXO3mf70UY$

+$schema:
https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!zwfPbJpcAbOIOvolZM17U38coXpSGcUDmLW5g8m4760Crj_jruCb42rt9lXOpl37_FI$

(quoted diff) +2 -0

+
+title: MediaTek Wireless Ethernet Dispatch WO controller

interface for MT7986

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +7 -0

+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-ccif provides a configuration interface

Quoted 2 lines

for WED WO
+ controller on MT7986 soc.

All previous comments apply.

Quoted 92 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file +35 -0

+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt7986-wo-ccif
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_ccif0: syscon@151a5000 {
+        compatible = "mediatek,mt7986-wo-ccif", "syscon";
+        reg = <0 0x151a5000 0 0x1000>;
+        interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+      };
+    };

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,m t7986-wo-dlm.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,m t7986-wo-dlm.yaml
new file mode 100644
index 000000000000..a499956d9e07
--- /dev/null
+++
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,m t7986-wo-dlm.yaml

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +4 -0

@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: 

https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-dlm.yaml*__;Iw!!CTRNKA9wMg0ARbw!zwfPbJpcAbOIOvolZM17U38coXpSGcUDmLW5g8m4760Crj_jruCb42rt9lXOVVd58hA$

+$schema:
https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!zwfPbJpcAbOIOvolZM17U38coXpSGcUDmLW5g8m4760Crj_jruCb42rt9lXOpl37_FI$

(quoted diff) +2 -0

+
+title: MediaTek Wireless Ethernet Dispatch WO hw rx ring

interface for MT7986

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file +7 -0

+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+  - Felix Fietkau <[email protected]>
+
+description:
+  The mediatek wo-dlm provides a configuration interface

for WED WO

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file +25 -0

+  rx ring on MT7986 soc.
+
+properties:
+  compatible:
+    const: mediatek,mt7986-wo-dlm
+
+  reg:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |

Quoted 8 lines

Quoted 8 lines

Quoted 8 lines

Quoted 8 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml line 44

Quoted 5 lines

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file +5 -0

+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      wo_dlm0: wo-dlm@151e8000 {

Node names should be generic.

Quoted 13 lines

Quoted 7 lines

Quoted 6 lines

Quoted 1 line

DLM is a chip used to store the data rx ring of wo firmware. I do not have a
better node name (naming is always hard). Can you please suggest a better name?

Quoted 5 lines

The problem is that you added three new devices which seem to be for the
same device - WED. It looks like some hacky way of avoid proper hardware
description - let's model everything as MMIO and syscons...

Quoted 4 lines

is it fine to use syscon as node name even if we do not declare it in compatible
string for dlm?

No, rather not. It's a shortcut and if used without actual syscon it would be confusing. You could still call it system-controller, though.

Best regards,
Krzysztof

From: Sujuan Chen <[email protected]>

Introduce WED mcu support used to configure WED WO chip. This is a preliminary patch in order to add RX Wireless Ethernet Dispatch available on MT7986 SoC.

Tested-by Daniel Golle <[email protected]>

Co-developed-by Lorenzo Bianconi <[email protected]>

Signed-off-by Lorenzo Bianconi <[email protected]>

Signed-off-by Sujuan Chen <[email protected]>

---
  drivers/net/ethernet/mediatek/Makefile       |   2 +-
  drivers/net/ethernet/mediatek/mtk_wed_mcu.c  | 364 +++++++++++++++++++
  drivers/net/ethernet/mediatek/mtk_wed_regs.h |   1 +
  drivers/net/ethernet/mediatek/mtk_wed_wo.h   | 152 ++++++++
  include/linux/soc/mediatek/mtk_wed.h         |  29 ++
  5 files changed, 547 insertions(+), 1 deletion(-)

create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_mcu.c create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_wo.h

drivers/net/ethernet/mediatek/Makefile +1 -1

index 45ba0970504a..d4bdefa77159 100644
@@ -5,7 +5,7 @@
 
  obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
  mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
-mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o
+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o
  ifdef CONFIG_DEBUG_FS
  mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
  endif

drivers/net/ethernet/mediatek/mtk_wed_mcu.c new file +0 -0

new file mode 100644
index 000000000000..20987eecfb52

drivers/net/ethernet/mediatek/mtk_wed_mcu.c new file +9 -0

+
+int mtk_wed_mcu_init(struct mtk_wed_wo *wo)
+{
+	u32 val;
+	int ret;
+
+	skb_queue_head_init(&wo->mcu.res_q);
+	init_waitqueue_head(&wo->mcu.wait);
+	mutex_init(&wo->mcu.mutex);

drivers/net/ethernet/mediatek/mtk_wed_mcu.c new file +6 -0

+
+	return val ? -EBUSY : 0;
+}
+
+MODULE_FIRMWARE(MT7986_FIRMWARE_WO0);
+MODULE_FIRMWARE(MT7986_FIRMWARE_WO1);

drivers/net/ethernet/mediatek/mtk_wed_regs.h +1 -0

index e270fb336143..c940b3bb215b 100644
@@ -152,6 +152,7 @@ struct mtk_wdma_desc {
 
  #define MTK_WED_RING_RX(_n)				(0x400 + (_n) * 0x10)
 
+#define MTK_WED_SCR0					0x3c0
  #define MTK_WED_WPDMA_INT_TRIGGER			0x504
  #define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE		BIT(1)
  #define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE		GENMASK(5, 4)

drivers/net/ethernet/mediatek/mtk_wed_wo.h new file +0 -0

new file mode 100644
index 000000000000..2ef3ccdec5bf
@@ -0,0 +1,152 @@

drivers/net/ethernet/mediatek/mtk_wed_wo.h new file +10 -0

+#define MTK_WO_MCU_CFG_LS_HW_VER_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x000)
+#define MTK_WO_MCU_CFG_LS_FW_VER_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x004)
+#define MTK_WO_MCU_CFG_LS_CFG_DBG1_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x00c)
+#define MTK_WO_MCU_CFG_LS_CFG_DBG2_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x010)
+#define MTK_WO_MCU_CFG_LS_WF_MCCR_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x014)
+#define MTK_WO_MCU_CFG_LS_WF_MCCR_SET_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x018)
+#define MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x01c)
+#define MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x050)
+#define MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x060)
+#define MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x064)

Il 03/11/22 10:28, Lorenzo Bianconi ha scritto:

Quoted 37 lines

From: Sujuan Chen <[email protected]>

Introduce WED mcu support used to configure WED WO chip. This is a preliminary patch in order to add RX Wireless Ethernet Dispatch available on MT7986 SoC.

Tested-by Daniel Golle <[email protected]>

Co-developed-by Lorenzo Bianconi <[email protected]>

Signed-off-by Lorenzo Bianconi <[email protected]>

Signed-off-by Sujuan Chen <[email protected]>

---
  drivers/net/ethernet/mediatek/Makefile       |   2 +-
  drivers/net/ethernet/mediatek/mtk_wed_mcu.c  | 364 +++++++++++++++++++
  drivers/net/ethernet/mediatek/mtk_wed_regs.h |   1 +
  drivers/net/ethernet/mediatek/mtk_wed_wo.h   | 152 ++++++++
  include/linux/soc/mediatek/mtk_wed.h         |  29 ++
  5 files changed, 547 insertions(+), 1 deletion(-)

create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_mcu.c create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_wo.h

drivers/net/ethernet/mediatek/Makefile +1 -1

index 45ba0970504a..d4bdefa77159 100644
@@ -5,7 +5,7 @@
  obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
  mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
-mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o
+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o
  ifdef CONFIG_DEBUG_FS
  mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
  endif

drivers/net/ethernet/mediatek/mtk_wed_mcu.c new file +0 -0

new file mode 100644
index 000000000000..20987eecfb52

..snip..

Quoted 13 lines

drivers/net/ethernet/mediatek/mtk_wed_mcu.c new file +13 -0

+
+int mtk_wed_mcu_init(struct mtk_wed_wo *wo)
+{
+	u32 val;
+	int ret;
+
+	skb_queue_head_init(&wo->mcu.res_q);
+	init_waitqueue_head(&wo->mcu.wait);
+	mutex_init(&wo->mcu.mutex);
+
+	ret = mtk_wed_mcu_load_firmware(wo);
+	if (ret)
+		return ret;

drivers/net/ethernet/mediatek/mtk_wed_mcu.c line 358

Quoted 6 lines

drivers/net/ethernet/mediatek/mtk_wed_mcu.c new file +6 -0

+
+	do {
+		/* get dummy cr */
+		val = wed_r32(wo->hw->wed_dev,
+			      MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL);
+	} while (val && !time_after(jiffies, jiffies + MTK_FW_DL_TIMEOUT));

Here you can use readx_poll_timeout() instead: please do so.

Quoted 23 lines

drivers/net/ethernet/mediatek/mtk_wed_mcu.c new file +6 -0

+
+	return val ? -EBUSY : 0;
+}
+
+MODULE_FIRMWARE(MT7986_FIRMWARE_WO0);
+MODULE_FIRMWARE(MT7986_FIRMWARE_WO1);

drivers/net/ethernet/mediatek/mtk_wed_regs.h +1 -0

index e270fb336143..c940b3bb215b 100644
@@ -152,6 +152,7 @@ struct mtk_wdma_desc {
  #define MTK_WED_RING_RX(_n)				(0x400 + (_n) * 0x10)
+#define MTK_WED_SCR0					0x3c0
  #define MTK_WED_WPDMA_INT_TRIGGER			0x504
  #define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE		BIT(1)
  #define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE		GENMASK(5, 4)

drivers/net/ethernet/mediatek/mtk_wed_wo.h new file +0 -0

new file mode 100644
index 000000000000..2ef3ccdec5bf
@@ -0,0 +1,152 @@

..snip..

drivers/net/ethernet/mediatek/mtk_wed_wo.h line 67

Quoted 2 lines

drivers/net/ethernet/mediatek/mtk_wed_wo.h new file +2 -0

+
+#define MTK_WO_MCU_CFG_LS_BASE				0 /* XXX: 0x15194000 */

Since that definition is zero, you can safely remove it: like so, the ones following will be a bit more readable.

Quoted 11 lines

drivers/net/ethernet/mediatek/mtk_wed_wo.h new file +10 -0

+#define MTK_WO_MCU_CFG_LS_HW_VER_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x000)
+#define MTK_WO_MCU_CFG_LS_FW_VER_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x004)
+#define MTK_WO_MCU_CFG_LS_CFG_DBG1_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x00c)
+#define MTK_WO_MCU_CFG_LS_CFG_DBG2_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x010)
+#define MTK_WO_MCU_CFG_LS_WF_MCCR_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x014)
+#define MTK_WO_MCU_CFG_LS_WF_MCCR_SET_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x018)
+#define MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x01c)
+#define MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x050)
+#define MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x060)
+#define MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x064)

..snip..

drivers/net/ethernet/mediatek/mtk_wed_wo.h line 133

Quoted 7 lines

drivers/net/ethernet/mediatek/mtk_wed_wo.h new file +7 -0

+
+static inline int
+mtk_wed_mcu_check_msg(struct mtk_wed_wo *wo, struct sk_buff *skb)
+{
+	struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data;
+
+	if (hdr->version)

	if (hdr->version || skb->len < sizeof(*hdr) || skb->len != le16_to_cpu(hdr->length))
		return -EINVAL;

drivers/net/ethernet/mediatek/mtk_wed_wo.h line 144

Quoted 13 lines

drivers/net/ethernet/mediatek/mtk_wed_wo.h new file +11 -0

+		return -EINVAL;
+
+	if (skb->len < sizeof(*hdr))
+		return -EINVAL;
+
+	if (skb->len != le16_to_cpu(hdr->length))
+		return -EINVAL;
+
+	return 0;
+}
+

Regards,
Angelo

From: Sujuan Chen <[email protected]>

Introduce WED mcu support used to configure WED WO chip. This is a preliminary patch in order to add RX Wireless Ethernet Dispatch available on MT7986 SoC.

Tested-by Daniel Golle <[email protected]>

Co-developed-by Lorenzo Bianconi <[email protected]>

Signed-off-by Lorenzo Bianconi <[email protected]>

Signed-off-by Sujuan Chen <[email protected]>

---
 drivers/net/ethernet/mediatek/Makefile       |   2 +-
 drivers/net/ethernet/mediatek/mtk_wed_mcu.c  | 364 +++++++++++++++++++
 drivers/net/ethernet/mediatek/mtk_wed_regs.h |   1 +
 drivers/net/ethernet/mediatek/mtk_wed_wo.h   | 152 ++++++++
 include/linux/soc/mediatek/mtk_wed.h         |  29 ++
 5 files changed, 547 insertions(+), 1 deletion(-)
 create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_mcu.c
 create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_wo.h

drivers/net/ethernet/mediatek/Makefile +1 -1

index 45ba0970504a..d4bdefa77159 100644
@@ -5,7 +5,7 @@
 
 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
 mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
-mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o
+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o
 ifdef CONFIG_DEBUG_FS
 mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
 endif

drivers/net/ethernet/mediatek/mtk_wed_mcu.c new file +305 -0

new file mode 100644
index 000000000000..20987eecfb52
@@ -0,0 +1,364 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (C) 2022 MediaTek Inc.
+ *
+ * Author: Lorenzo Bianconi <[email protected]>
+ *	   Sujuan Chen <[email protected]>
+ */
+
+#include <linux/firmware.h>
+#include <linux/of_address.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/mfd/syscon.h>
+#include <linux/soc/mediatek/mtk_wed.h>
+
+#include "mtk_wed_regs.h"
+#include "mtk_wed_wo.h"
+#include "mtk_wed.h"
+
+static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
+{
+	u32 val;
+
+	if (regmap_read(wo->boot, reg, &val))
+		val = ~0;
+
+	return val;
+}
+
+static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
+{
+	regmap_write(wo->boot, reg, val);
+}
+
+static struct sk_buff *
+mtk_wed_mcu_msg_alloc(const void *data, int data_len)
+{
+	int length = sizeof(struct mtk_wed_mcu_hdr) + data_len;
+	struct sk_buff *skb;
+
+	skb = alloc_skb(length, GFP_KERNEL);
+	if (!skb)
+		return NULL;
+
+	memset(skb->head, 0, length);
+	skb_reserve(skb, sizeof(struct mtk_wed_mcu_hdr));
+	if (data && data_len)
+		skb_put_data(skb, data, data_len);
+
+	return skb;
+}
+
+static struct sk_buff *
+mtk_wed_mcu_get_response(struct mtk_wed_wo *wo, unsigned long expires)
+{
+	if (!time_is_after_jiffies(expires))
+		return NULL;
+
+	wait_event_timeout(wo->mcu.wait, !skb_queue_empty(&wo->mcu.res_q),
+			   expires - jiffies);
+	return skb_dequeue(&wo->mcu.res_q);
+}
+
+void mtk_wed_mcu_rx_event(struct mtk_wed_wo *wo, struct sk_buff *skb)
+{
+	skb_queue_tail(&wo->mcu.res_q, skb);
+	wake_up(&wo->mcu.wait);
+}
+
+void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo,
+				      struct sk_buff *skb)
+{
+	struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data;
+
+	switch (hdr->cmd) {
+	case MTK_WED_WO_EVT_LOG_DUMP: {
+		const char *msg = (const char *)(skb->data + sizeof(*hdr));
+
+		dev_notice(wo->hw->dev, "%s\n", msg);
+		break;
+	}
+	case MTK_WED_WO_EVT_PROFILING: {
+		struct mtk_wed_wo_log_info *info;
+		u32 count = (skb->len - sizeof(*hdr)) / sizeof(*info);
+		int i;
+
+		info = (struct mtk_wed_wo_log_info *)(skb->data + sizeof(*hdr));
+		for (i = 0 ; i < count ; i++)
+			dev_notice(wo->hw->dev,
+				   "SN:%u latency: total=%u, rro:%u, mod:%u\n",
+				   le32_to_cpu(info[i].sn),
+				   le32_to_cpu(info[i].total),
+				   le32_to_cpu(info[i].rro),
+				   le32_to_cpu(info[i].mod));
+		break;
+	}
+	case MTK_WED_WO_EVT_RXCNT_INFO:
+		break;
+	default:
+		break;
+	}
+
+	dev_kfree_skb(skb);
+}
+
+static int
+mtk_wed_mcu_skb_send_msg(struct mtk_wed_wo *wo, struct sk_buff *skb,
+			 int id, int cmd, u16 *wait_seq, bool wait_resp)
+{
+	struct mtk_wed_mcu_hdr *hdr;
+
+	/* TODO: make it dynamic based on cmd */
+	wo->mcu.timeout = 20 * HZ;
+
+	hdr = (struct mtk_wed_mcu_hdr *)skb_push(skb, sizeof(*hdr));
+	hdr->cmd = cmd;
+	hdr->length = cpu_to_le16(skb->len);
+
+	if (wait_resp && wait_seq) {
+		u16 seq = ++wo->mcu.seq;
+
+		if (!seq)
+			seq = ++wo->mcu.seq;
+		*wait_seq = seq;
+
+		hdr->flag |= cpu_to_le16(MTK_WED_WARP_CMD_FLAG_NEED_RSP);
+		hdr->seq = cpu_to_le16(seq);
+	}
+	if (id == MTK_WED_MODULE_ID_WO)
+		hdr->flag |= cpu_to_le16(MTK_WED_WARP_CMD_FLAG_FROM_TO_WO);
+
+	dev_kfree_skb(skb);
+	return 0;
+}
+
+static int
+mtk_wed_mcu_parse_response(struct mtk_wed_wo *wo, struct sk_buff *skb,
+			   int cmd, int seq)
+{
+	struct mtk_wed_mcu_hdr *hdr;
+
+	if (!skb) {
+		dev_err(wo->hw->dev, "Message %08x (seq %d) timeout\n",
+			cmd, seq);
+		return -ETIMEDOUT;
+	}
+
+	hdr = (struct mtk_wed_mcu_hdr *)skb->data;
+	if (le16_to_cpu(hdr->seq) != seq)
+		return -EAGAIN;
+
+	skb_pull(skb, sizeof(*hdr));
+	switch (cmd) {
+	case MTK_WED_WO_CMD_RXCNT_INFO:
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd,
+			 const void *data, int len, bool wait_resp)
+{
+	unsigned long expires;
+	struct sk_buff *skb;
+	u16 seq;
+	int ret;
+
+	skb = mtk_wed_mcu_msg_alloc(data, len);
+	if (!skb)
+		return -ENOMEM;
+
+	mutex_lock(&wo->mcu.mutex);
+
+	ret = mtk_wed_mcu_skb_send_msg(wo, skb, id, cmd, &seq, wait_resp);
+	if (ret || !wait_resp)
+		goto unlock;
+
+	expires = jiffies + wo->mcu.timeout;
+	do {
+		skb = mtk_wed_mcu_get_response(wo, expires);
+		ret = mtk_wed_mcu_parse_response(wo, skb, cmd, seq);
+		dev_kfree_skb(skb);
+	} while (ret == -EAGAIN);
+
+unlock:
+	mutex_unlock(&wo->mcu.mutex);
+
+	return ret;
+}
+
+static int
+mtk_wed_get_memory_region(struct mtk_wed_wo *wo,
+			  struct mtk_wed_wo_memory_region *region)
+{
+	struct reserved_mem *rmem;
+	struct device_node *np;
+	int index;
+
+	index = of_property_match_string(wo->hw->node, "memory-region-names",
+					 region->name);
+	if (index < 0)
+		return index;
+
+	np = of_parse_phandle(wo->hw->node, "memory-region", index);
+	if (!np)
+		return -ENODEV;
+
+	rmem = of_reserved_mem_lookup(np);
+	of_node_put(np);
+
+	if (!rmem)
+		return -ENODEV;
+
+	region->phy_addr = rmem->base;
+	region->size = rmem->size;
+	region->addr = devm_ioremap(wo->hw->dev, region->phy_addr, region->size);
+	if (!region->addr)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int
+mtk_wed_mcu_run_firmware(struct mtk_wed_wo *wo, const struct firmware *fw,
+			 struct mtk_wed_wo_memory_region *region)
+{
+	const u8 *first_region_ptr, *region_ptr, *trailer_ptr, *ptr = fw->data;
+	const struct mtk_wed_fw_trailer *trailer;
+	const struct mtk_wed_fw_region *fw_region;
+
+	trailer_ptr = fw->data + fw->size - sizeof(*trailer);
+	trailer = (const struct mtk_wed_fw_trailer *)trailer_ptr;
+	region_ptr = trailer_ptr - trailer->num_region * sizeof(*fw_region);
+	first_region_ptr = region_ptr;
+
+	while (region_ptr < trailer_ptr) {
+		u32 length;
+
+		fw_region = (const struct mtk_wed_fw_region *)region_ptr;
+		length = le32_to_cpu(fw_region->len);
+
+		if (region->phy_addr != le32_to_cpu(fw_region->addr))
+			goto next;
+
+		if (region->size < length)
+			goto next;
+
+		if (first_region_ptr < ptr + length)
+			goto next;
+
+		if (region->shared && region->consumed)
+			return 0;
+
+		if (!region->shared || !region->consumed) {
+			memcpy_toio(region->addr, ptr, length);
+			region->consumed = true;
+			return 0;
+		}
+next:
+		region_ptr += sizeof(*fw_region);
+		ptr += length;
+	}
+
+	return -EINVAL;
+}
+
+static int
+mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo)
+{
+	static struct mtk_wed_wo_memory_region mem_region[] = {
+		[MTK_WED_WO_REGION_EMI] = {
+			.name = "wo-emi",
+		},
+		[MTK_WED_WO_REGION_ILM] = {
+			.name = "wo-ilm",
+		},
+		[MTK_WED_WO_REGION_DATA] = {
+			.name = "wo-data",
+			.shared = true,
+		},
+	};
+	const struct mtk_wed_fw_trailer *trailer;
+	const struct firmware *fw;
+	const char *fw_name;
+	u32 val, boot_cr;
+	int ret, i;
+
+	/* load firmware region metadata */
+	for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
+		ret = mtk_wed_get_memory_region(wo, &mem_region[i]);
+		if (ret)
+			return ret;
+	}
+
+	wo->boot = syscon_regmap_lookup_by_phandle(wo->hw->node,
+						   "mediatek,wo-boot");
+	if (IS_ERR_OR_NULL(wo->boot))
+		return PTR_ERR(wo->boot);
+
+	/* set dummy cr */
+	wed_w32(wo->hw->wed_dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL,
+		wo->hw->index + 1);
+
+	/* load firmware */
+	fw_name = wo->hw->index ? MT7986_FIRMWARE_WO1 : MT7986_FIRMWARE_WO0;

drivers/net/ethernet/mediatek/mtk_wed_mcu.c new file +49 -0

+		 trailer->chip_id, trailer->num_region);
+
+	for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
+		ret = mtk_wed_mcu_run_firmware(wo, fw, &mem_region[i]);
+		if (ret)
+			goto out;
+	}
+
+	/* set the start address */
+	boot_cr = wo->hw->index ? MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR
+				: MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
+	wo_w32(wo, boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
+	/* wo firmware reset */
+	wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
+
+	val = wo_r32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR);
+	val |= wo->hw->index ? MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK
+			     : MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK;
+	wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
+out:
+	release_firmware(fw);
+
+	return ret;
+}
+
+int mtk_wed_mcu_init(struct mtk_wed_wo *wo)
+{
+	u32 val;
+	int ret;
+
+	skb_queue_head_init(&wo->mcu.res_q);
+	init_waitqueue_head(&wo->mcu.wait);
+	mutex_init(&wo->mcu.mutex);
+
+	ret = mtk_wed_mcu_load_firmware(wo);
+	if (ret)
+		return ret;
+
+	do {
+		/* get dummy cr */
+		val = wed_r32(wo->hw->wed_dev,
+			      MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL);
+	} while (val && !time_after(jiffies, jiffies + MTK_FW_DL_TIMEOUT));
+
+	return val ? -EBUSY : 0;
+}
+
+MODULE_FIRMWARE(MT7986_FIRMWARE_WO0);
+MODULE_FIRMWARE(MT7986_FIRMWARE_WO1);

drivers/net/ethernet/mediatek/mtk_wed_regs.h +1 -0

index e270fb336143..c940b3bb215b 100644
@@ -152,6 +152,7 @@ struct mtk_wdma_desc {
 
 #define MTK_WED_RING_RX(_n)				(0x400 + (_n) * 0x10)
 
+#define MTK_WED_SCR0					0x3c0
 #define MTK_WED_WPDMA_INT_TRIGGER			0x504
 #define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE		BIT(1)
 #define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE		GENMASK(5, 4)

drivers/net/ethernet/mediatek/mtk_wed_wo.h new file +152 -0

new file mode 100644
index 000000000000..2ef3ccdec5bf
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (C) 2022 Lorenzo Bianconi <[email protected]>  */
+
+#ifndef __MTK_WED_WO_H
+#define __MTK_WED_WO_H
+
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+
+struct mtk_wed_hw;
+
+struct mtk_wed_mcu_hdr {
+	/* DW0 */
+	u8 version;
+	u8 cmd;
+	__le16 length;
+
+	/* DW1 */
+	__le16 seq;
+	__le16 flag;
+
+	/* DW2 */
+	__le32 status;
+
+	/* DW3 */
+	u8 rsv[20];
+};
+
+struct mtk_wed_wo_log_info {
+	__le32 sn;
+	__le32 total;
+	__le32 rro;
+	__le32 mod;
+};
+
+enum mtk_wed_wo_event {
+	MTK_WED_WO_EVT_LOG_DUMP		= 0x1,
+	MTK_WED_WO_EVT_PROFILING	= 0x2,
+	MTK_WED_WO_EVT_RXCNT_INFO	= 0x3,
+};
+
+#define MTK_WED_MODULE_ID_WO		1
+#define MTK_FW_DL_TIMEOUT		(4 * HZ)
+#define MTK_WOCPU_TIMEOUT		(2 * HZ)
+
+enum {
+	MTK_WED_WARP_CMD_FLAG_RSP		= BIT(0),
+	MTK_WED_WARP_CMD_FLAG_NEED_RSP		= BIT(1),
+	MTK_WED_WARP_CMD_FLAG_FROM_TO_WO	= BIT(2),
+};
+
+enum {
+	MTK_WED_WO_REGION_EMI,
+	MTK_WED_WO_REGION_ILM,
+	MTK_WED_WO_REGION_DATA,
+	__MTK_WED_WO_REGION_MAX,
+};
+
+enum mtk_wed_dummy_cr_idx {
+	MTK_WED_DUMMY_CR_FWDL,
+	MTK_WED_DUMMY_CR_WO_STATUS,
+};
+
+#define MT7986_FIRMWARE_WO0	"mediatek/mt7986_wo_0.bin"
+#define MT7986_FIRMWARE_WO1	"mediatek/mt7986_wo_1.bin"
+
+#define MTK_WO_MCU_CFG_LS_BASE				0 /* XXX: 0x15194000 */
+#define MTK_WO_MCU_CFG_LS_HW_VER_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x000)
+#define MTK_WO_MCU_CFG_LS_FW_VER_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x004)
+#define MTK_WO_MCU_CFG_LS_CFG_DBG1_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x00c)
+#define MTK_WO_MCU_CFG_LS_CFG_DBG2_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x010)
+#define MTK_WO_MCU_CFG_LS_WF_MCCR_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x014)
+#define MTK_WO_MCU_CFG_LS_WF_MCCR_SET_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x018)
+#define MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x01c)
+#define MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x050)
+#define MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x060)
+#define MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x064)
+
+#define MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK	BIT(5)
+#define MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK	BIT(0)
+
+struct mtk_wed_wo_memory_region {
+	const char *name;
+	void __iomem *addr;
+	phys_addr_t phy_addr;
+	u32 size;
+	bool shared:1;
+	bool consumed:1;
+};
+
+struct mtk_wed_fw_region {
+	__le32 decomp_crc;
+	__le32 decomp_len;
+	__le32 decomp_blk_sz;
+	u8 rsv0[4];
+	__le32 addr;
+	__le32 len;
+	u8 feature_set;
+	u8 rsv1[15];
+} __packed;
+
+struct mtk_wed_fw_trailer {
+	u8 chip_id;
+	u8 eco_code;
+	u8 num_region;
+	u8 format_ver;
+	u8 format_flag;
+	u8 rsv[2];
+	char fw_ver[10];
+	char build_date[15];
+	u32 crc;
+};
+
+struct mtk_wed_wo {
+	struct mtk_wed_hw *hw;
+	struct regmap *boot;
+
+	struct {
+		struct mutex mutex;
+		int timeout;
+		u16 seq;
+
+		struct sk_buff_head res_q;
+		wait_queue_head_t wait;
+	} mcu;
+};
+
+static inline int
+mtk_wed_mcu_check_msg(struct mtk_wed_wo *wo, struct sk_buff *skb)
+{
+	struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data;
+
+	if (hdr->version)
+		return -EINVAL;
+
+	if (skb->len < sizeof(*hdr))
+		return -EINVAL;
+
+	if (skb->len != le16_to_cpu(hdr->length))
+		return -EINVAL;
+
+	return 0;
+}
+
+void mtk_wed_mcu_rx_event(struct mtk_wed_wo *wo, struct sk_buff *skb);
+void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo,
+				      struct sk_buff *skb);
+int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd,
+			 const void *data, int len, bool wait_resp);
+int mtk_wed_mcu_init(struct mtk_wed_wo *wo);
+
+#endif /* __MTK_WED_WO_H */

include/linux/soc/mediatek/mtk_wed.h +29 -0

index 4450c8b7a1cb..2cc2f1e43ba9 100644
@@ -11,6 +11,35 @@
 struct mtk_wed_hw;
 struct mtk_wdma_desc;
 
+enum mtk_wed_wo_cmd {
+	MTK_WED_WO_CMD_WED_CFG,
+	MTK_WED_WO_CMD_WED_RX_STAT,
+	MTK_WED_WO_CMD_RRO_SER,
+	MTK_WED_WO_CMD_DBG_INFO,
+	MTK_WED_WO_CMD_DEV_INFO,
+	MTK_WED_WO_CMD_BSS_INFO,
+	MTK_WED_WO_CMD_STA_REC,
+	MTK_WED_WO_CMD_DEV_INFO_DUMP,
+	MTK_WED_WO_CMD_BSS_INFO_DUMP,
+	MTK_WED_WO_CMD_STA_REC_DUMP,
+	MTK_WED_WO_CMD_BA_INFO_DUMP,
+	MTK_WED_WO_CMD_FBCMD_Q_DUMP,
+	MTK_WED_WO_CMD_FW_LOG_CTRL,
+	MTK_WED_WO_CMD_LOG_FLUSH,
+	MTK_WED_WO_CMD_CHANGE_STATE,
+	MTK_WED_WO_CMD_CPU_STATS_ENABLE,
+	MTK_WED_WO_CMD_CPU_STATS_DUMP,
+	MTK_WED_WO_CMD_EXCEPTION_INIT,
+	MTK_WED_WO_CMD_PROF_CTRL,
+	MTK_WED_WO_CMD_STA_BA_DUMP,
+	MTK_WED_WO_CMD_BA_CTRL_DUMP,
+	MTK_WED_WO_CMD_RXCNT_CTRL,
+	MTK_WED_WO_CMD_RXCNT_INFO,
+	MTK_WED_WO_CMD_SET_CAP,
+	MTK_WED_WO_CMD_CCIF_RING_DUMP,
+	MTK_WED_WO_CMD_WED_END
+};
+
 enum mtk_wed_bus_tye {
 	MTK_WED_BUS_PCIE,
 	MTK_WED_BUS_AXI,

Signature · 1 line

2.38.1

Hi Lorenzo,

I found a potential typo in the print output during probe. See below.

Quoted 354 lines · Lorenzo Bianconi

From: Sujuan Chen <[email protected]>

Introduce WED mcu support used to configure WED WO chip. This is a preliminary patch in order to add RX Wireless Ethernet Dispatch available on MT7986 SoC.

Tested-by Daniel Golle <[email protected]>

Co-developed-by Lorenzo Bianconi <[email protected]>

Signed-off-by Lorenzo Bianconi <[email protected]>

Signed-off-by Sujuan Chen <[email protected]>

---
 drivers/net/ethernet/mediatek/Makefile       |   2 +-
 drivers/net/ethernet/mediatek/mtk_wed_mcu.c  | 364 +++++++++++++++++++
 drivers/net/ethernet/mediatek/mtk_wed_regs.h |   1 +
 drivers/net/ethernet/mediatek/mtk_wed_wo.h   | 152 ++++++++
 include/linux/soc/mediatek/mtk_wed.h         |  29 ++
 5 files changed, 547 insertions(+), 1 deletion(-)
 create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_mcu.c
 create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_wo.h

drivers/net/ethernet/mediatek/Makefile +1 -1

index 45ba0970504a..d4bdefa77159 100644
@@ -5,7 +5,7 @@
 
 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
 mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
-mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o
+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o
 ifdef CONFIG_DEBUG_FS
 mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
 endif

drivers/net/ethernet/mediatek/mtk_wed_mcu.c new file +315 -0

new file mode 100644
index 000000000000..20987eecfb52
@@ -0,0 +1,364 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (C) 2022 MediaTek Inc.
+ *
+ * Author: Lorenzo Bianconi <[email protected]>
+ *	   Sujuan Chen <[email protected]>
+ */
+
+#include <linux/firmware.h>
+#include <linux/of_address.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/mfd/syscon.h>
+#include <linux/soc/mediatek/mtk_wed.h>
+
+#include "mtk_wed_regs.h"
+#include "mtk_wed_wo.h"
+#include "mtk_wed.h"
+
+static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
+{
+	u32 val;
+
+	if (regmap_read(wo->boot, reg, &val))
+		val = ~0;
+
+	return val;
+}
+
+static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
+{
+	regmap_write(wo->boot, reg, val);
+}
+
+static struct sk_buff *
+mtk_wed_mcu_msg_alloc(const void *data, int data_len)
+{
+	int length = sizeof(struct mtk_wed_mcu_hdr) + data_len;
+	struct sk_buff *skb;
+
+	skb = alloc_skb(length, GFP_KERNEL);
+	if (!skb)
+		return NULL;
+
+	memset(skb->head, 0, length);
+	skb_reserve(skb, sizeof(struct mtk_wed_mcu_hdr));
+	if (data && data_len)
+		skb_put_data(skb, data, data_len);
+
+	return skb;
+}
+
+static struct sk_buff *
+mtk_wed_mcu_get_response(struct mtk_wed_wo *wo, unsigned long expires)
+{
+	if (!time_is_after_jiffies(expires))
+		return NULL;
+
+	wait_event_timeout(wo->mcu.wait, !skb_queue_empty(&wo->mcu.res_q),
+			   expires - jiffies);
+	return skb_dequeue(&wo->mcu.res_q);
+}
+
+void mtk_wed_mcu_rx_event(struct mtk_wed_wo *wo, struct sk_buff *skb)
+{
+	skb_queue_tail(&wo->mcu.res_q, skb);
+	wake_up(&wo->mcu.wait);
+}
+
+void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo,
+				      struct sk_buff *skb)
+{
+	struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data;
+
+	switch (hdr->cmd) {
+	case MTK_WED_WO_EVT_LOG_DUMP: {
+		const char *msg = (const char *)(skb->data + sizeof(*hdr));
+
+		dev_notice(wo->hw->dev, "%s\n", msg);
+		break;
+	}
+	case MTK_WED_WO_EVT_PROFILING: {
+		struct mtk_wed_wo_log_info *info;
+		u32 count = (skb->len - sizeof(*hdr)) / sizeof(*info);
+		int i;
+
+		info = (struct mtk_wed_wo_log_info *)(skb->data + sizeof(*hdr));
+		for (i = 0 ; i < count ; i++)
+			dev_notice(wo->hw->dev,
+				   "SN:%u latency: total=%u, rro:%u, mod:%u\n",
+				   le32_to_cpu(info[i].sn),
+				   le32_to_cpu(info[i].total),
+				   le32_to_cpu(info[i].rro),
+				   le32_to_cpu(info[i].mod));
+		break;
+	}
+	case MTK_WED_WO_EVT_RXCNT_INFO:
+		break;
+	default:
+		break;
+	}
+
+	dev_kfree_skb(skb);
+}
+
+static int
+mtk_wed_mcu_skb_send_msg(struct mtk_wed_wo *wo, struct sk_buff *skb,
+			 int id, int cmd, u16 *wait_seq, bool wait_resp)
+{
+	struct mtk_wed_mcu_hdr *hdr;
+
+	/* TODO: make it dynamic based on cmd */
+	wo->mcu.timeout = 20 * HZ;
+
+	hdr = (struct mtk_wed_mcu_hdr *)skb_push(skb, sizeof(*hdr));
+	hdr->cmd = cmd;
+	hdr->length = cpu_to_le16(skb->len);
+
+	if (wait_resp && wait_seq) {
+		u16 seq = ++wo->mcu.seq;
+
+		if (!seq)
+			seq = ++wo->mcu.seq;
+		*wait_seq = seq;
+
+		hdr->flag |= cpu_to_le16(MTK_WED_WARP_CMD_FLAG_NEED_RSP);
+		hdr->seq = cpu_to_le16(seq);
+	}
+	if (id == MTK_WED_MODULE_ID_WO)
+		hdr->flag |= cpu_to_le16(MTK_WED_WARP_CMD_FLAG_FROM_TO_WO);
+
+	dev_kfree_skb(skb);
+	return 0;
+}
+
+static int
+mtk_wed_mcu_parse_response(struct mtk_wed_wo *wo, struct sk_buff *skb,
+			   int cmd, int seq)
+{
+	struct mtk_wed_mcu_hdr *hdr;
+
+	if (!skb) {
+		dev_err(wo->hw->dev, "Message %08x (seq %d) timeout\n",
+			cmd, seq);
+		return -ETIMEDOUT;
+	}
+
+	hdr = (struct mtk_wed_mcu_hdr *)skb->data;
+	if (le16_to_cpu(hdr->seq) != seq)
+		return -EAGAIN;
+
+	skb_pull(skb, sizeof(*hdr));
+	switch (cmd) {
+	case MTK_WED_WO_CMD_RXCNT_INFO:
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd,
+			 const void *data, int len, bool wait_resp)
+{
+	unsigned long expires;
+	struct sk_buff *skb;
+	u16 seq;
+	int ret;
+
+	skb = mtk_wed_mcu_msg_alloc(data, len);
+	if (!skb)
+		return -ENOMEM;
+
+	mutex_lock(&wo->mcu.mutex);
+
+	ret = mtk_wed_mcu_skb_send_msg(wo, skb, id, cmd, &seq, wait_resp);
+	if (ret || !wait_resp)
+		goto unlock;
+
+	expires = jiffies + wo->mcu.timeout;
+	do {
+		skb = mtk_wed_mcu_get_response(wo, expires);
+		ret = mtk_wed_mcu_parse_response(wo, skb, cmd, seq);
+		dev_kfree_skb(skb);
+	} while (ret == -EAGAIN);
+
+unlock:
+	mutex_unlock(&wo->mcu.mutex);
+
+	return ret;
+}
+
+static int
+mtk_wed_get_memory_region(struct mtk_wed_wo *wo,
+			  struct mtk_wed_wo_memory_region *region)
+{
+	struct reserved_mem *rmem;
+	struct device_node *np;
+	int index;
+
+	index = of_property_match_string(wo->hw->node, "memory-region-names",
+					 region->name);
+	if (index < 0)
+		return index;
+
+	np = of_parse_phandle(wo->hw->node, "memory-region", index);
+	if (!np)
+		return -ENODEV;
+
+	rmem = of_reserved_mem_lookup(np);
+	of_node_put(np);
+
+	if (!rmem)
+		return -ENODEV;
+
+	region->phy_addr = rmem->base;
+	region->size = rmem->size;
+	region->addr = devm_ioremap(wo->hw->dev, region->phy_addr, region->size);
+	if (!region->addr)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int
+mtk_wed_mcu_run_firmware(struct mtk_wed_wo *wo, const struct firmware *fw,
+			 struct mtk_wed_wo_memory_region *region)
+{
+	const u8 *first_region_ptr, *region_ptr, *trailer_ptr, *ptr = fw->data;
+	const struct mtk_wed_fw_trailer *trailer;
+	const struct mtk_wed_fw_region *fw_region;
+
+	trailer_ptr = fw->data + fw->size - sizeof(*trailer);
+	trailer = (const struct mtk_wed_fw_trailer *)trailer_ptr;
+	region_ptr = trailer_ptr - trailer->num_region * sizeof(*fw_region);
+	first_region_ptr = region_ptr;
+
+	while (region_ptr < trailer_ptr) {
+		u32 length;
+
+		fw_region = (const struct mtk_wed_fw_region *)region_ptr;
+		length = le32_to_cpu(fw_region->len);
+
+		if (region->phy_addr != le32_to_cpu(fw_region->addr))
+			goto next;
+
+		if (region->size < length)
+			goto next;
+
+		if (first_region_ptr < ptr + length)
+			goto next;
+
+		if (region->shared && region->consumed)
+			return 0;
+
+		if (!region->shared || !region->consumed) {
+			memcpy_toio(region->addr, ptr, length);
+			region->consumed = true;
+			return 0;
+		}
+next:
+		region_ptr += sizeof(*fw_region);
+		ptr += length;
+	}
+
+	return -EINVAL;
+}
+
+static int
+mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo)
+{
+	static struct mtk_wed_wo_memory_region mem_region[] = {
+		[MTK_WED_WO_REGION_EMI] = {
+			.name = "wo-emi",
+		},
+		[MTK_WED_WO_REGION_ILM] = {
+			.name = "wo-ilm",
+		},
+		[MTK_WED_WO_REGION_DATA] = {
+			.name = "wo-data",
+			.shared = true,
+		},
+	};
+	const struct mtk_wed_fw_trailer *trailer;
+	const struct firmware *fw;
+	const char *fw_name;
+	u32 val, boot_cr;
+	int ret, i;
+
+	/* load firmware region metadata */
+	for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
+		ret = mtk_wed_get_memory_region(wo, &mem_region[i]);
+		if (ret)
+			return ret;
+	}
+
+	wo->boot = syscon_regmap_lookup_by_phandle(wo->hw->node,
+						   "mediatek,wo-boot");
+	if (IS_ERR_OR_NULL(wo->boot))
+		return PTR_ERR(wo->boot);
+
+	/* set dummy cr */
+	wed_w32(wo->hw->wed_dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL,
+		wo->hw->index + 1);
+
+	/* load firmware */
+	fw_name = wo->hw->index ? MT7986_FIRMWARE_WO1 : MT7986_FIRMWARE_WO0;
+	ret = request_firmware(&fw, fw_name, wo->hw->dev);
+	if (ret)
+		return ret;
+
+	trailer = (void *)(fw->data + fw->size -
+			   sizeof(struct mtk_wed_fw_trailer));
+	dev_info(wo->hw->dev,
+		 "MTK WED WO Firmware Version: %.10s, Build Time: %.15s\n",
+		 trailer->fw_ver, trailer->build_date);
+	dev_info(wo->hw->dev, "MTK WED WO Chid ID %02x Region %d\n",

(quoted diff) +1 -1

-Chid
+Chip

?

Quoted 265 lines

drivers/net/ethernet/mediatek/mtk_wed_mcu.c new file +49 -0

+		 trailer->chip_id, trailer->num_region);
+
+	for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
+		ret = mtk_wed_mcu_run_firmware(wo, fw, &mem_region[i]);
+		if (ret)
+			goto out;
+	}
+
+	/* set the start address */
+	boot_cr = wo->hw->index ? MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR
+				: MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
+	wo_w32(wo, boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
+	/* wo firmware reset */
+	wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
+
+	val = wo_r32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR);
+	val |= wo->hw->index ? MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK
+			     : MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK;
+	wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
+out:
+	release_firmware(fw);
+
+	return ret;
+}
+
+int mtk_wed_mcu_init(struct mtk_wed_wo *wo)
+{
+	u32 val;
+	int ret;
+
+	skb_queue_head_init(&wo->mcu.res_q);
+	init_waitqueue_head(&wo->mcu.wait);
+	mutex_init(&wo->mcu.mutex);
+
+	ret = mtk_wed_mcu_load_firmware(wo);
+	if (ret)
+		return ret;
+
+	do {
+		/* get dummy cr */
+		val = wed_r32(wo->hw->wed_dev,
+			      MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL);
+	} while (val && !time_after(jiffies, jiffies + MTK_FW_DL_TIMEOUT));
+
+	return val ? -EBUSY : 0;
+}
+
+MODULE_FIRMWARE(MT7986_FIRMWARE_WO0);
+MODULE_FIRMWARE(MT7986_FIRMWARE_WO1);

drivers/net/ethernet/mediatek/mtk_wed_regs.h +1 -0

index e270fb336143..c940b3bb215b 100644
@@ -152,6 +152,7 @@ struct mtk_wdma_desc {
 
 #define MTK_WED_RING_RX(_n)				(0x400 + (_n) * 0x10)
 
+#define MTK_WED_SCR0					0x3c0
 #define MTK_WED_WPDMA_INT_TRIGGER			0x504
 #define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE		BIT(1)
 #define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE		GENMASK(5, 4)

drivers/net/ethernet/mediatek/mtk_wed_wo.h new file +152 -0

new file mode 100644
index 000000000000..2ef3ccdec5bf
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (C) 2022 Lorenzo Bianconi <[email protected]>  */
+
+#ifndef __MTK_WED_WO_H
+#define __MTK_WED_WO_H
+
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+
+struct mtk_wed_hw;
+
+struct mtk_wed_mcu_hdr {
+	/* DW0 */
+	u8 version;
+	u8 cmd;
+	__le16 length;
+
+	/* DW1 */
+	__le16 seq;
+	__le16 flag;
+
+	/* DW2 */
+	__le32 status;
+
+	/* DW3 */
+	u8 rsv[20];
+};
+
+struct mtk_wed_wo_log_info {
+	__le32 sn;
+	__le32 total;
+	__le32 rro;
+	__le32 mod;
+};
+
+enum mtk_wed_wo_event {
+	MTK_WED_WO_EVT_LOG_DUMP		= 0x1,
+	MTK_WED_WO_EVT_PROFILING	= 0x2,
+	MTK_WED_WO_EVT_RXCNT_INFO	= 0x3,
+};
+
+#define MTK_WED_MODULE_ID_WO		1
+#define MTK_FW_DL_TIMEOUT		(4 * HZ)
+#define MTK_WOCPU_TIMEOUT		(2 * HZ)
+
+enum {
+	MTK_WED_WARP_CMD_FLAG_RSP		= BIT(0),
+	MTK_WED_WARP_CMD_FLAG_NEED_RSP		= BIT(1),
+	MTK_WED_WARP_CMD_FLAG_FROM_TO_WO	= BIT(2),
+};
+
+enum {
+	MTK_WED_WO_REGION_EMI,
+	MTK_WED_WO_REGION_ILM,
+	MTK_WED_WO_REGION_DATA,
+	__MTK_WED_WO_REGION_MAX,
+};
+
+enum mtk_wed_dummy_cr_idx {
+	MTK_WED_DUMMY_CR_FWDL,
+	MTK_WED_DUMMY_CR_WO_STATUS,
+};
+
+#define MT7986_FIRMWARE_WO0	"mediatek/mt7986_wo_0.bin"
+#define MT7986_FIRMWARE_WO1	"mediatek/mt7986_wo_1.bin"
+
+#define MTK_WO_MCU_CFG_LS_BASE				0 /* XXX: 0x15194000 */
+#define MTK_WO_MCU_CFG_LS_HW_VER_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x000)
+#define MTK_WO_MCU_CFG_LS_FW_VER_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x004)
+#define MTK_WO_MCU_CFG_LS_CFG_DBG1_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x00c)
+#define MTK_WO_MCU_CFG_LS_CFG_DBG2_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x010)
+#define MTK_WO_MCU_CFG_LS_WF_MCCR_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x014)
+#define MTK_WO_MCU_CFG_LS_WF_MCCR_SET_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x018)
+#define MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x01c)
+#define MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x050)
+#define MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x060)
+#define MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x064)
+
+#define MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK	BIT(5)
+#define MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK	BIT(0)
+
+struct mtk_wed_wo_memory_region {
+	const char *name;
+	void __iomem *addr;
+	phys_addr_t phy_addr;
+	u32 size;
+	bool shared:1;
+	bool consumed:1;
+};
+
+struct mtk_wed_fw_region {
+	__le32 decomp_crc;
+	__le32 decomp_len;
+	__le32 decomp_blk_sz;
+	u8 rsv0[4];
+	__le32 addr;
+	__le32 len;
+	u8 feature_set;
+	u8 rsv1[15];
+} __packed;
+
+struct mtk_wed_fw_trailer {
+	u8 chip_id;
+	u8 eco_code;
+	u8 num_region;
+	u8 format_ver;
+	u8 format_flag;
+	u8 rsv[2];
+	char fw_ver[10];
+	char build_date[15];
+	u32 crc;
+};
+
+struct mtk_wed_wo {
+	struct mtk_wed_hw *hw;
+	struct regmap *boot;
+
+	struct {
+		struct mutex mutex;
+		int timeout;
+		u16 seq;
+
+		struct sk_buff_head res_q;
+		wait_queue_head_t wait;
+	} mcu;
+};
+
+static inline int
+mtk_wed_mcu_check_msg(struct mtk_wed_wo *wo, struct sk_buff *skb)
+{
+	struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data;
+
+	if (hdr->version)
+		return -EINVAL;
+
+	if (skb->len < sizeof(*hdr))
+		return -EINVAL;
+
+	if (skb->len != le16_to_cpu(hdr->length))
+		return -EINVAL;
+
+	return 0;
+}
+
+void mtk_wed_mcu_rx_event(struct mtk_wed_wo *wo, struct sk_buff *skb);
+void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo,
+				      struct sk_buff *skb);
+int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd,
+			 const void *data, int len, bool wait_resp);
+int mtk_wed_mcu_init(struct mtk_wed_wo *wo);
+
+#endif /* __MTK_WED_WO_H */

include/linux/soc/mediatek/mtk_wed.h +29 -0

index 4450c8b7a1cb..2cc2f1e43ba9 100644
@@ -11,6 +11,35 @@
 struct mtk_wed_hw;
 struct mtk_wdma_desc;
 
+enum mtk_wed_wo_cmd {
+	MTK_WED_WO_CMD_WED_CFG,
+	MTK_WED_WO_CMD_WED_RX_STAT,
+	MTK_WED_WO_CMD_RRO_SER,
+	MTK_WED_WO_CMD_DBG_INFO,
+	MTK_WED_WO_CMD_DEV_INFO,
+	MTK_WED_WO_CMD_BSS_INFO,
+	MTK_WED_WO_CMD_STA_REC,
+	MTK_WED_WO_CMD_DEV_INFO_DUMP,
+	MTK_WED_WO_CMD_BSS_INFO_DUMP,
+	MTK_WED_WO_CMD_STA_REC_DUMP,
+	MTK_WED_WO_CMD_BA_INFO_DUMP,
+	MTK_WED_WO_CMD_FBCMD_Q_DUMP,
+	MTK_WED_WO_CMD_FW_LOG_CTRL,
+	MTK_WED_WO_CMD_LOG_FLUSH,
+	MTK_WED_WO_CMD_CHANGE_STATE,
+	MTK_WED_WO_CMD_CPU_STATS_ENABLE,
+	MTK_WED_WO_CMD_CPU_STATS_DUMP,
+	MTK_WED_WO_CMD_EXCEPTION_INIT,
+	MTK_WED_WO_CMD_PROF_CTRL,
+	MTK_WED_WO_CMD_STA_BA_DUMP,
+	MTK_WED_WO_CMD_BA_CTRL_DUMP,
+	MTK_WED_WO_CMD_RXCNT_CTRL,
+	MTK_WED_WO_CMD_RXCNT_INFO,
+	MTK_WED_WO_CMD_SET_CAP,
+	MTK_WED_WO_CMD_CCIF_RING_DUMP,
+	MTK_WED_WO_CMD_WED_END
+};
+
 enum mtk_wed_bus_tye {
 	MTK_WED_BUS_PCIE,
 	MTK_WED_BUS_AXI,

Signature · 1 line

2.38.1