arm64: zynqmp: Misc zynqmp changes

TI DP83867 is using strapping based on MIO pins. Tristate setup can influce PHY address. That's why switch description with ethernet-phy-id compatible string which enable calling reset. PHY itself setups phy address after power up or reset.

Phy reset is done via gpio.

Signed-off-by Michal Simek <[email protected]>

---

Checkpatch is reporting issue
warning: DT compatible string "ethernet-phy-id2000.a231" appears un-documented but it should be fully aligned with Documentation/devicetree/bindings/net/ethernet-phy.yaml

---
 .../boot/dts/xilinx/zynqmp-zcu102-revA.dts    | 23 +++++++++++------
 .../boot/dts/xilinx/zynqmp-zcu102-revB.dts    | 25 +++++++++++--------
 .../boot/dts/xilinx/zynqmp-zcu104-revA.dts    | 22 ++++++++++------
 .../boot/dts/xilinx/zynqmp-zcu104-revC.dts    | 22 ++++++++++------
 .../boot/dts/xilinx/zynqmp-zcu106-revA.dts    | 22 ++++++++++------
 .../boot/dts/xilinx/zynqmp-zcu111-revA.dts    | 22 ++++++++++------
 6 files changed, 90 insertions(+), 46 deletions(-)

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +2 -1

index 13c43324f1d2..c193579400cf 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU102 RevA
  *
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -200,13 +201,19 @@ &gem3 {
 	phy-mode = "rgmii-id";

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +12 -0

+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@21 {
+			#phy-cells = <1>;
+			compatible = "ethernet-phy-id2000.a231";
+			reg = <21>;
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
 	};
 };
 

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts +15 -10

index f7d718ff116b..00b930f20718 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU102 RevB
  *
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -16,16 +17,20 @@ / {
 
 &gem3 {
 	phy-handle = <&phyc>;
-	phyc: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
-		/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
+	mdio: mdio {
+		phyc: ethernet-phy@c {
+			#phy-cells = <0x1>;
+			compatible = "ethernet-phy-id2000.a231";
+			reg = <0xc>;
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
+		/* Cleanup from RevA */
+		/delete-node/ ethernet-phy@21;
 	};
-	/* Cleanup from RevA */
-	/delete-node/ ethernet-phy@21;
 };
 
 /* Fix collision with u61 */

arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +15 -7

index 485585c491f4..11c1eaef9f53 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU104
  *
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -109,12 +110,19 @@ &gem3 {
 	phy-mode = "rgmii-id";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@c {
+			#phy-cells = <1>;
+			compatible = "ethernet-phy-id2000.a231";
+			reg = <0xc>;
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
 	};
 };
 

arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +15 -7

index 44ec9edd2452..c06c138fa3e5 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU104
  *
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -114,12 +115,19 @@ &gem3 {
 	phy-mode = "rgmii-id";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@c {
+			#phy-cells = <1>;
+			compatible = "ethernet-phy-id2000.a231";
+			reg = <0xc>;
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
 	};
 };
 

arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +15 -7

index 09773b7200f8..52cdec33f190 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU106
  *
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -212,12 +213,19 @@ &gem3 {
 	phy-mode = "rgmii-id";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@c {
+			#phy-cells = <1>;
+			reg = <0xc>;
+			compatible = "ethernet-phy-id2000.a231";
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
 	};
 };
 

arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +15 -7

index e0305dcbb010..699cc9ce7898 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU111
  *
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -172,12 +173,19 @@ &gem3 {
 	phy-mode = "rgmii-id";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@c {
+			#phy-cells = <1>;
+			compatible = "ethernet-phy-id2000.a231";
+			reg = <0xc>;
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;
+		};
 	};
 };
 

Hi Michal,

Thank you for the patch.

Quoted 1 line · Michal Simek

TI DP83867 is using strapping based on MIO pins. Tristate setup can influce

Quoted 3 lines

PHY address. That's why switch description with ethernet-phy-id compatible string which enable calling reset. PHY itself setups phy address after power up or reset.

I'm sorry but I don't understand this :-(

Quoted 39 lines

Phy reset is done via gpio.

Signed-off-by Michal Simek <[email protected]>

---

Checkpatch is reporting issue
warning: DT compatible string "ethernet-phy-id2000.a231" appears un-documented but it should be fully aligned with Documentation/devicetree/bindings/net/ethernet-phy.yaml

---
  .../boot/dts/xilinx/zynqmp-zcu102-revA.dts    | 23 +++++++++++------
  .../boot/dts/xilinx/zynqmp-zcu102-revB.dts    | 25 +++++++++++--------
  .../boot/dts/xilinx/zynqmp-zcu104-revA.dts    | 22 ++++++++++------
  .../boot/dts/xilinx/zynqmp-zcu104-revC.dts    | 22 ++++++++++------
  .../boot/dts/xilinx/zynqmp-zcu106-revA.dts    | 22 ++++++++++------
  .../boot/dts/xilinx/zynqmp-zcu111-revA.dts    | 22 ++++++++++------
  6 files changed, 90 insertions(+), 46 deletions(-)

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +2 -3

index 13c43324f1d2..c193579400cf 100644
@@ -2,7 +2,8 @@
  /*
   * dts file for Xilinx ZynqMP ZCU102 RevA
   *
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * Michal Simek <[email protected]>
   */

@@ -200,13 +201,19 @@ &gem3 {
  	phy-mode = "rgmii-id";
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@21 {
-		reg = <21>;

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts &gem3 { · line 204

Quoted 6 lines

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +1 -5

-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
-		/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
+	mdio: mdio {

The "mdio" label isn't needed. Same below.

From: Ashok Reddy Soma <[email protected]>

As per design, all input/rx pins should have fast slew rate and 12mA drive strength.

Rest all pins should be slow slew rate and 4mA drive strength. Fix usb nodes as per this and remove setting of slow slew rate for all the usb group pins.

Signed-off-by Ashok Reddy Soma <[email protected]>

Signed-off-by Michal Simek <[email protected]>

---

 .../arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso |  8 ++++++--
 .../arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso |  8 ++++++--
 .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts     |  8 ++++++--
 .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts     |  8 ++++++--
 arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts   | 13 ++++++++++---
 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts   |  5 ++++-
 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts   |  6 ++++--
 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts   |  6 ++++--
 arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts   |  5 ++++-
 arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts   |  5 ++++-
 10 files changed, 54 insertions(+), 18 deletions(-)

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +6 -2

index b610e65e0cdf..2f7a17ec58b4 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for KV260 revA Carrier Card
  *
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2020 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * SD level shifter:
  * "A" – A01 board un-modified (NXP)

@@ -259,19 +260,22 @@ mux {
 	pinctrl_usb0_default: usb0-default {
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			"MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 
 		mux {

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +6 -2

index a52dafbfd59e..4695e0e3714f 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for KV260 revA Carrier Card
  *
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2020 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -242,19 +243,22 @@ mux {
 	pinctrl_usb0_default: usb0-default {
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			"MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 
 		mux {

arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +6 -2

index f89ef2afcd9e..5fa9604f05d1 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP zc1751-xm015-dc1
  *
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -187,19 +188,22 @@ mux {
 
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			       "MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
 

arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +6 -2

index 938b76bd0527..a2031187d9b3 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP zc1751-xm016-dc2
  *
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -281,19 +282,22 @@ mux {
 
 		conf {
 			groups = "usb1_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO64", "MIO65", "MIO67";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
 			       "MIO72", "MIO73", "MIO74", "MIO75";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
 

arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +10 -3

index c74bc3ff703b..2dd552cf51fb 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU100 revC
  *
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  * Nathalie Chan King Choy

@@ -423,19 +424,22 @@ mux {
 
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			       "MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
 

@@ -447,19 +451,22 @@ mux {
 
 		conf {
 			groups = "usb1_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO64", "MIO65", "MIO67";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
 			       "MIO72", "MIO73", "MIO74", "MIO75";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
 };

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +4 -1

index c193579400cf..78043d9de7cc 100644
@@ -783,19 +783,22 @@ mux {
 
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			       "MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
 

arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +4 -2

index 11c1eaef9f53..c1779c88ec34 100644
@@ -410,20 +410,22 @@ mux {
 
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
-			drive-strength = <12>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			       "MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
 };

arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +4 -2

index c06c138fa3e5..b857c1950496 100644
@@ -422,20 +422,22 @@ mux {
 
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
-			drive-strength = <12>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			       "MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
 };

arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +4 -1

index 52cdec33f190..e4e09afbdc1a 100644
@@ -794,19 +794,22 @@ mux {
 
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			       "MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
 

arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +4 -1

index 699cc9ce7898..791b2ac9fbdb 100644
@@ -660,19 +660,22 @@ mux {
 
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			       "MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
 

Hi Michal,

Thank you for the patch.

Quoted 4 lines · Michal Simek

From: Ashok Reddy Soma <[email protected]>

As per design, all input/rx pins should have fast slew rate and 12mA drive strength.

Why does the slow rate and drive strength matter for input pins ?

From: Amit Kumar Mahapatra <[email protected]>

All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4.
This would enable the spi-nor framework to issue 1-4-4 write commands instead of 1-1-1. This will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line.

Signed-off-by Amit Kumar Mahapatra <[email protected]>

Signed-off-by Michal Simek <[email protected]>

---

 arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts      | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts      | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts      | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts      | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts      | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts      | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts      | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts      | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts      | 2 +-
 11 files changed, 11 insertions(+), 11 deletions(-)

arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +1 -1

index 34412304d09f..dcc17e3ea961 100644
@@ -85,7 +85,7 @@ flash@0 { /* MT25QU512A */
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <40000000>; /* 40MHz */
 		partition@0 {

arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +1 -1

index f1598527e5ec..4d301ea0bdcb 100644
@@ -44,7 +44,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};

arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +1 -1

index 04efa1683eaa..485a7b21157a 100644
@@ -45,7 +45,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};

arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts +1 -1

index e971ba8c1418..676b8550a625 100644
@@ -47,7 +47,7 @@ &qspi {
 	flash@0 {
 		compatible = "m25p80", "jedec,spi-nor";
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <108000000>;
 	};

arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +1 -1

index 5fa9604f05d1..35fe7857459a 100644
@@ -355,7 +355,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};

arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +1 -1

index 6e0106bf1294..311cb2f81c7b 100644
@@ -173,7 +173,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>; /* also DUAL configuration possible */
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +1 -1

index 78043d9de7cc..5b6403865541 100644
@@ -957,7 +957,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};

arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +1 -1

index c1779c88ec34..a74a2061431a 100644
@@ -444,7 +444,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};

arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +1 -1

index b857c1950496..73972d83ed4d 100644
@@ -456,7 +456,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};

arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +1 -1

index e4e09afbdc1a..5a54d066db86 100644
@@ -964,7 +964,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};

arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +1 -1

index 791b2ac9fbdb..3b37df98700c 100644
@@ -794,7 +794,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};

The commit 53ba1b2bdaf7 ("arm64: dts: zynqmp: Add mode-pin GPIO controller DT node") added usb phy reset over bootmode pins by default on usb0 only. zcu100 is using usb0 as peripheral and usb1 as host. Unfortunately reset line is shared for both usb ulpi phys but usb_rst_b is connected to usb5744 hub which is used only in host mode. Especially this chip requires reset to operate properly that's why better assign gpio reset to usb1 instead of usb0.

Signed-off-by Michal Simek <[email protected]>

---

  arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 ++
  1 file changed, 2 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +1 -0

index 2dd552cf51fb..c99abb99efcb 100644
@@ -552,6 +552,7 @@ &usb0 {
  	pinctrl-0 = <&pinctrl_usb0_default>;
  	phy-names = "usb3-phy";
  	phys = <&psgtr 2 PHY_TYPE_USB3 0 0>;
+	/delete-property/ reset-gpios;
  };
 
  &dwc3_0 {

From: Radhey Shyam Pandey <[email protected]>

Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache node and let each CPU point to it.

Signed-off-by Radhey Shyam Pandey <[email protected]>

Signed-off-by Michal Simek <[email protected]>

---

 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +3 -0

index bb0d0be30aa0..c2d80c7967e9 100644
@@ -33,6 +33,7 @@ cpu0: cpu@0 {
 			operating-points-v2 = <&cpu_opp_table>;
 			reg = <0x0>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu1: cpu@1 {

@@ -42,6 +43,7 @@ cpu1: cpu@1 {
 			reg = <0x1>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu2: cpu@2 {

@@ -51,6 +53,7 @@ cpu2: cpu@2 {
 			reg = <0x2>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu3: cpu@3 {

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +2 -0

+			compatible = "cache";
+			cache-level = <2>;
 		};
 
 		idle-states {

Hi Michal,

Thank you for the patch.

On Tue, May 02, 2023 at 03:35:33PM +0200, Michal Simek wrote:

Quoted 5 lines

From: Radhey Shyam Pandey <[email protected]>

Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache node and let each CPU point to it.

The commit message should focus on how this change brings the DT in line with the hardware, not on what the Linux kernel does.

Quoted 35 lines

Signed-off-by Radhey Shyam Pandey <[email protected]>

Signed-off-by Michal Simek <[email protected]>

---

  arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 9 +++++++++
  1 file changed, 9 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +3 -0

index bb0d0be30aa0..c2d80c7967e9 100644
@@ -33,6 +33,7 @@ cpu0: cpu@0 {
  			operating-points-v2 = <&cpu_opp_table>;
  			reg = <0x0>;
  			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
  		};
 
  		cpu1: cpu@1 {

@@ -42,6 +43,7 @@ cpu1: cpu@1 {
  			reg = <0x1>;
  			operating-points-v2 = <&cpu_opp_table>;
  			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
  		};
 
  		cpu2: cpu@2 {

@@ -51,6 +53,7 @@ cpu2: cpu@2 {
  			reg = <0x2>;
  			operating-points-v2 = <&cpu_opp_table>;
  			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
  		};
 

arch/arm64/boot/dts/xilinx/zynqmp.dtsi cpu3: cpu@3 { · line 69

Quoted 9 lines

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +4 -0

  		cpu3: cpu@3 {

@@ -60,6 +63,12 @@ cpu3: cpu@3 {
  			reg = <0x3>;
  			operating-points-v2 = <&cpu_opp_table>;
  			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
+		};
+
+		L2: l2-cache {

Shouldn't labels be lower-case ?

Quoted 9 lines · Laurent Pinchart

Quoted 5 lines · Michal Simek

From: Radhey Shyam Pandey <[email protected]>

Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache node and let each CPU point to it.

The commit message should focus on how this change brings the DT in line with the hardware, not on what the Linux kernel does.

ok.

Quoted 34 lines

Quoted 34 lines

Signed-off-by Radhey Shyam Pandey <[email protected]>

Signed-off-by Michal Simek <[email protected]>

---

  arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 9 +++++++++
  1 file changed, 9 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +3 -0

index bb0d0be30aa0..c2d80c7967e9 100644
@@ -33,6 +33,7 @@ cpu0: cpu@0 {
  			operating-points-v2 = <&cpu_opp_table>;
  			reg = <0x0>;
  			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
  		};
 
  		cpu1: cpu@1 {

@@ -42,6 +43,7 @@ cpu1: cpu@1 {
  			reg = <0x1>;
  			operating-points-v2 = <&cpu_opp_table>;
  			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
  		};
 
  		cpu2: cpu@2 {

@@ -51,6 +53,7 @@ cpu2: cpu@2 {
  			reg = <0x2>;
  			operating-points-v2 = <&cpu_opp_table>;
  			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
  		};
 

Quoted 11 lines

arch/arm64/boot/dts/xilinx/zynqmp.dtsi cpu3: cpu@3 { · line 69

Quoted 9 lines

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +4 -0

  		cpu3: cpu@3 {

@@ -60,6 +63,12 @@ cpu3: cpu@3 {
  			reg = <0x3>;
  			operating-points-v2 = <&cpu_opp_table>;
  			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
+		};
+
+		L2: l2-cache {

Shouldn't labels be lower-case ?

Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:220: L2_0:
l2-cache { Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:241:
L2_100: l2-cache { Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:257:
L2_200: l2-cache { Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:273:
L2_300: l2-cache { Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:289:
L2_400: l2-cache { Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:305:
L2_500: l2-cache { Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:321:
L2_600: l2-cache { Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:337:
L2_700: l2-cache { Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml:116:
L2_0: l2-cache { Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml:151:
L2_1: l2-cache { Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml:77:

              L2_0: l2-cache {

And in dt spec - 6.2 chapter uppercase letter is valid chars for DTS labels.

Address in node name should match with the first reg property in DT.

Signed-off-by Michal Simek <[email protected]>

---

 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +1 -1

index c2d80c7967e9..61c7045eb992 100644
@@ -135,7 +135,7 @@ zynqmp_ipi: zynqmp_ipi {
 		#size-cells = <2>;
 		ranges;
 
-		ipi_mailbox_pmu1: mailbox@ff990400 {
+		ipi_mailbox_pmu1: mailbox@ff9905c0 {
 			reg = <0x0 0xff9905c0 0x0 0x20>,
 			      <0x0 0xff9905e0 0x0 0x20>,
 			      <0x0 0xff990e80 0x0 0x20>,

Hi Michal,

Thank you for the patch.

Quoted 3 lines · Michal Simek

Address in node name should match with the first reg property in DT.

Signed-off-by Michal Simek <[email protected]>

Reviewed-by Laurent Pinchart <[email protected]>

From: Radhey Shyam Pandey <[email protected]>

Explicitly specify interrupt affinity to avoid HW perfevents need to guess. This avoids the following error upon linux boot:
armv8-pmu pmu: hw perfevents: no interrupt-affinity property, guessing.

Signed-off-by Radhey Shyam Pandey <[email protected]>

Signed-off-by Michal Simek <[email protected]>

---

 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +4 -0

index 61c7045eb992..a117294dc890 100644
@@ -161,6 +161,10 @@ pmu {
 			     <0 144 4>,
 			     <0 145 4>,
 			     <0 146 4>;
+		interrupt-affinity = <&cpu0>,
+				     <&cpu1>,
+				     <&cpu2>,
+				     <&cpu3>;
 	};
 
 	psci {

From: Radhey Shyam Pandey <[email protected]>

Explicitly specify interrupt affinity to avoid HW perfevents need to guess. This avoids the following error upon linux boot:
armv8-pmu pmu: hw perfevents: no interrupt-affinity property, guessing.

Signed-off-by Radhey Shyam Pandey <[email protected]>

Signed-off-by Michal Simek <[email protected]>

---

  arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++
  1 file changed, 4 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +0 -0

index 61c7045eb992..a117294dc890 100644

Quoted 23 lines · Michal Simek

From: Radhey Shyam Pandey <[email protected]>

Explicitly specify interrupt affinity to avoid HW perfevents need to guess. This avoids the following error upon linux boot:
armv8-pmu pmu: hw perfevents: no interrupt-affinity property, guessing.

Signed-off-by Radhey Shyam Pandey <[email protected]>

Signed-off-by Michal Simek <[email protected]>

---

  arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++

  1 file changed, 4 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +1 -0

index 61c7045eb992..a117294dc890 100644
@@ -161,6 +161,10 @@ pmu {
                    <0 144 4>,
                    <0 145 4>,
                    <0 146 4>;
+        interrupt-affinity = <&cpu0>,

arch/arm64/boot/dts/xilinx/zynqmp.dtsi pmu { · line 170

Quoted 5 lines

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +3 -0

+                     <&cpu1>,
+                     <&cpu2>,
+                     <&cpu3>;
       };
       psci {

Applied.
M

From: Sai Krishna Potthuri <[email protected]>

Add "resets" property to sdhci nodes. Resets property is used to reset the SD host controller when dynamic configuration support is enabled.

Signed-off-by Sai Krishna Potthuri <[email protected]>

Signed-off-by Michal Simek <[email protected]>

---

 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++
 1 file changed, 2 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +2 -0

index a117294dc890..7bd3e816226a 100644
@@ -755,6 +755,7 @@ sdhci0: mmc@ff160000 {
 			#clock-cells = <1>;
 			clock-output-names = "clk_out_sd0", "clk_in_sd0";
 			power-domains = <&zynqmp_firmware PD_SD_0>;
+			resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;
 		};
 
 		sdhci1: mmc@ff170000 {

@@ -768,6 +769,7 @@ sdhci1: mmc@ff170000 {
 			#clock-cells = <1>;
 			clock-output-names = "clk_out_sd1", "clk_in_sd1";
 			power-domains = <&zynqmp_firmware PD_SD_1>;
+			resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;
 		};
 
 		smmu: iommu@fd800000 {

Hi Michal,

Thank you for the patch.

Quoted 2 lines · Michal Simek

From: Sai Krishna Potthuri <[email protected]>

Quoted 5 lines

Add "resets" property to sdhci nodes. Resets property is used to reset the SD host controller when dynamic configuration support is enabled.

Signed-off-by Sai Krishna Potthuri <[email protected]>

Signed-off-by Michal Simek <[email protected]>

Reviewed-by Laurent Pinchart <[email protected]>

There are couple of IPs which are enabled in origin HW design which are missing in SOM dt. Add them to match default setup.

Signed-off-by Michal Simek <[email protected]>

---

  .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts    | 95 +++++++++++++++++++
  1 file changed, 95 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +85 -0

index dcc17e3ea961..3862168fa026 100644
@@ -288,6 +288,101 @@ &gpio {
  			  "", "", "", ""; /* 170 - 173 */
  };
 
+&zynqmp_dpsub {
+	status = "okay";
+};
+
+&rtc {
+	status = "okay";
+};
+
+&lpd_dma_chan1 {
+	status = "okay";
+};
+
+&lpd_dma_chan2 {
+	status = "okay";
+};
+
+&lpd_dma_chan3 {
+	status = "okay";
+};
+
+&lpd_dma_chan4 {
+	status = "okay";
+};
+
+&lpd_dma_chan5 {
+	status = "okay";
+};
+
+&lpd_dma_chan6 {
+	status = "okay";
+};
+
+&lpd_dma_chan7 {
+	status = "okay";
+};
+
+&lpd_dma_chan8 {
+	status = "okay";
+};
+
+&fpd_dma_chan1 {
+	status = "okay";
+};
+
+&fpd_dma_chan2 {
+	status = "okay";
+};
+
+&fpd_dma_chan3 {
+	status = "okay";
+};
+
+&fpd_dma_chan4 {
+	status = "okay";
+};
+
+&fpd_dma_chan5 {
+	status = "okay";
+};
+
+&fpd_dma_chan6 {
+	status = "okay";
+};
+
+&fpd_dma_chan7 {
+	status = "okay";
+};
+
+&fpd_dma_chan8 {
+	status = "okay";
+};
+
  &gpu {
  	status = "okay";
  };
+
+&lpd_watchdog {
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};
+
+&cpu_opp_table {
+	opp00 {
+		opp-hz = /bits/ 64 <1333333333>;
+	};

From: Srinivas Neeli <[email protected]>

BTN_MISC looks like the most reasonable option for this button. Button is used by firmware to indicate (after reset, power up) that user wants to do firmware upgrade via firmware update utility.
For bootloader or OS is this just user button which is worth to have it mapped.
Also button can be used as a wakeup source and pressing it for more time can generate more chars that's why also adding wakeup-source and autorepeat properties.

Signed-off-by Srinivas Neeli <[email protected]>

Signed-off-by Michal Simek <[email protected]>

---

  arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 3 +++
  1 file changed, 3 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +0 -0

index 3862168fa026..340a5c43a8b6 100644

With limited low level configuration done via psu-init only IPs connected on SOM are initialized and configured. All IPs connected to carrier card are not initialized. There is a need to do proper reset, pin configuration and also clock setting.
The patch targets the last part which is setting up proper clock for EMMC on production SOMs and SD on kv260-revB.

Signed-off-by Michal Simek <[email protected]>

---

  arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi       | 5 ++++-
  arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 1 +
  arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 1 +
  arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts    | 1 +
  4 files changed, 7 insertions(+), 1 deletion(-)

arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +4 -1

index 5e7e1bf5b811..681885c9bcbb 100644
@@ -2,7 +2,8 @@
  /*
   * Clock specification for Xilinx ZynqMP
   *
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * Michal Simek <[email protected]>
   */

@@ -185,10 +186,12 @@ &sata {
 
  &sdhci0 {
  	clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
+	assigned-clocks = <&zynqmp_clk SDIO0_REF>;
  };
 
  &sdhci1 {
  	clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
+	assigned-clocks = <&zynqmp_clk SDIO1_REF>;
  };
 
  &spi0 {

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +1 -0

index 2f7a17ec58b4..cb4a5126c4ec 100644
@@ -133,6 +133,7 @@ &sdhci1 { /* on CC with tuned parameters */
  	no-1-8-v;
  	disable-wp;
  	xlnx,mio-bank = <1>;
+	assigned-clock-rates = <187498123>;
  };
 
  &gem3 { /* required by spec */

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +1 -0

index 4695e0e3714f..31bc120dee49 100644
@@ -116,6 +116,7 @@ &sdhci1 { /* on CC with tuned parameters */
  	clk-phase-sd-hs = <126>, <60>;
  	clk-phase-uhs-sdr25 = <120>, <60>;
  	clk-phase-uhs-ddr50 = <126>, <48>;
+	assigned-clock-rates = <187498123>;
  };
 
  &gem3 { /* required by spec */

arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +0 -0

index 340a5c43a8b6..d3c6a9feb114 100644

From: Amit Kumar Mahapatra <[email protected]>

Update MTD partitions of Kria device trees to allocate 128KB of QSPI memory for secure OS. Increased "SHA256" partition size & changed starting address of "User" partition to accommodate the new partition "Secure OS Storage"

Signed-off-by Amit Kumar Mahapatra <[email protected]>

Signed-off-by Michal Simek <[email protected]>

---

  arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 12 ++++++++----
  1 file changed, 8 insertions(+), 4 deletions(-)

arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +3 -3

index d3c6a9feb114..5fbc2fbd2638 100644
@@ -83,7 +83,7 @@ &uart1 { /* MIO36/MIO37 */
 
  &qspi { /* MIO 0-5 - U143 */
  	status = "okay";
-	flash@0 { /* MT25QU512A */
+	spi_flash: flash@0 { /* MT25QU512A */
  		compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
  		#address-cells = <1>;
  		#size-cells = <1>;

@@ -161,13 +161,17 @@ partition@2220000 {
  		};
  		partition@2240000 {
  			label = "SHA256";
-			reg = <0x2240000 0x10000>; /* 256B but 64KB sector */
+			reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
  			read-only;
  			lock;
  		};
-		partition@2250000 {
+		partition@2280000 {

Using label helps with better chip identification.

Signed-off-by Michal Simek <[email protected]>

---

  arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 4 ++++
  1 file changed, 4 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +0 -0

index cb3e5c06fdc5..c206021cccf7 100644

Production SOM has emmc on it and make sense to describe pin description to be able use EMMC if it is not configured via psu_init.
(Still some regs are not handled but this is one step in that direction)

Signed-off-by Michal Simek <[email protected]>

---

  .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts    | 20 +++++++++++++++++++
  1 file changed, 20 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +18 -0

index c206021cccf7..e284979fd7b1 100644
@@ -14,6 +14,7 @@
  #include <dt-bindings/input/input.h>
  #include <dt-bindings/gpio/gpio.h>
  #include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
 
  / {
  	model = "ZynqMP SM-K26 Rev1/B/A";

@@ -85,6 +86,23 @@ &uart1 { /* MIO36/MIO37 */
  	status = "okay";
  };
 
+&pinctrl0 {
+	status = "okay";
+	pinctrl_sdhci0_default: sdhci0-default {
+		conf {
+			groups = "sdio0_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+			bias-disable;
+		};
+
+		mux {
+			groups = "sdio0_0_grp";
+			function = "sdio0";
+		};
+	};
+};
+
  &qspi { /* MIO 0-5 - U143 */
  	status = "okay";
  	spi_flash: flash@0 { /* MT25QU512A */

From: Piyush Mehta <[email protected]>

The board zynqmp-zc1751-xm016-dc2 support only USB2.0 that's why remove USB3.0 DT configuration.

Signed-off-by Piyush Mehta <[email protected]>

Signed-off-by Michal Simek <[email protected]>

---

  arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 --
  1 file changed, 2 deletions(-)

arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +0 -0

index a2031187d9b3..9e7564235b69 100644

Use ethernet-phy-id compatible string to properly describe phy reset on kv260 boards. Previous description wasn't correct because reset was done for mdio bus to operate and it was in this case used for different purpose which was eth phy reset. With ethernet-phy-id phy reset happens only for the phy via phy framework.

Signed-off-by Michal Simek <[email protected]>

---

  arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 6 ++++--
  arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 6 ++++--
  2 files changed, 8 insertions(+), 4 deletions(-)

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +4 -2

index cb4a5126c4ec..817d756142ab 100644
@@ -146,16 +146,18 @@ &gem3 { /* required by spec */
  	mdio: mdio {
  		#address-cells = <1>;
  		#size-cells = <0>;
-		reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
-		reset-delay-us = <2>;
 
  		phy0: ethernet-phy@1 {
  			#phy-cells = <1>;
  			reg = <1>;
+			compatible = "ethernet-phy-id2000.a231";
  			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
  			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
  			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  			ti,dp83867-rxctrl-strap-quirk;
+			reset-assert-us = <100>;
+			reset-deassert-us = <280>;
+			reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
  		};
  	};
  };

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +1 -2

index 31bc120dee49..e07cec231ee0 100644
@@ -129,16 +129,18 @@ &gem3 { /* required by spec */
  	mdio: mdio {
  		#address-cells = <1>;
  		#size-cells = <0>;
-		reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
-		reset-delay-us = <2>;
 
  		phy0: ethernet-phy@1 {
  			#phy-cells = <1>;
  			reg = <1>;
+			compatible = "ethernet-phy-id2000.a231";

Clocks are coming from shared HW design where these frequencies should be aligned with PLL setup.

Signed-off-by Michal Simek <[email protected]>

---

  arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi       | 4 ++++
  arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 ++
  arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 ++
  3 files changed, 8 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +4 -0

index 681885c9bcbb..581221fdadf1 100644
@@ -248,10 +248,14 @@ &xilinx_ams {
 
  &zynqmp_dpdma {
  	clocks = <&zynqmp_clk DPDMA_REF>;
+	assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
  };
 
  &zynqmp_dpsub {
  	clocks = <&zynqmp_clk TOPSW_LSBUS>,
  		 <&zynqmp_clk DP_AUDIO_REF>,
  		 <&zynqmp_clk DP_VIDEO_REF>;
+	assigned-clocks = <&zynqmp_clk DP_STC_REF>,
+			  <&zynqmp_clk DP_AUDIO_REF>,
+			  <&zynqmp_clk DP_VIDEO_REF>;  /* rpll, rpll, vpll */
  };

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +2 -0

index 817d756142ab..4f18b3efcced 100644
@@ -99,10 +99,12 @@ &zynqmp_dpsub {
  	status = "disabled";
  	phy-names = "dp-phy0", "dp-phy1";
  	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
  };
 
  &zynqmp_dpdma {
  	status = "okay";
+	assigned-clock-rates = <600000000>;
  };
 
  &usb0 {

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +0 -0

index e07cec231ee0..77bc806b15a1 100644
@@ -80,10 +80,12 @@ &zynqmp_dpsub {
  	status = "disabled";
  	phy-names = "dp-phy0", "dp-phy1";

DP DMA is already enabled that's why there is no reason to keep DP disabled.

Signed-off-by Michal Simek <[email protected]>

---

  arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 +-
  arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +1 -1

index 4f18b3efcced..776444714fad 100644
@@ -96,7 +96,7 @@ &sata {
  };
 
  &zynqmp_dpsub {
-	status = "disabled";
+	status = "okay";
  	phy-names = "dp-phy0", "dp-phy1";
  	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
  	assigned-clock-rates = <27000000>, <25000000>, <300000000>;

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +0 -0

index 77bc806b15a1..78d082a11492 100644

Fix child node names to be aligned with commit 39dd2d1e251d ("dt-bindings:
iio: adc: Add Xilinx AMS binding documentation") which requires names as ams-ps@ and ams-pl@.

Signed-off-by Michal Simek <[email protected]>

---

 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +2 -2

index 7bd3e816226a..d01d4334c95f 100644
@@ -955,13 +955,13 @@ xilinx_ams: ams@ffa50000 {
 			#io-channel-cells = <1>;
 			ranges = <0 0 0xffa50800 0x800>;
 
-			ams_ps: ams_ps@0 {
+			ams_ps: ams-ps@0 {
 				compatible = "xlnx,zynqmp-ams-ps";
 				status = "disabled";
 				reg = <0x0 0x400>;
 			};
 
-			ams_pl: ams_pl@400 {
+			ams_pl: ams-pl@400 {
 				compatible = "xlnx,zynqmp-ams-pl";
 				status = "disabled";
 				reg = <0x400 0x400>;

Hi Michal,

Thank you for the patch.

Quoted 5 lines · Michal Simek

Fix child node names to be aligned with commit 39dd2d1e251d ("dt-bindings:
iio: adc: Add Xilinx AMS binding documentation") which requires names as ams-ps@ and ams-pl@.

Signed-off-by Michal Simek <[email protected]>

Reviewed-by Laurent Pinchart <[email protected]>

AMS is used for monitoring system. Used for measuring voltages and especially temperatures. Origin interface is IIO but via iio-hwmon it can be moved to hwmon framework too (done for SOM and zcu100).

Signed-off-by Michal Simek <[email protected]>

---

  .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts    | 26 +++++++++++++++++++
  .../boot/dts/xilinx/zynqmp-zcu100-revC.dts    | 17 ++++++++++++
  .../boot/dts/xilinx/zynqmp-zcu102-revA.dts    | 12 +++++++++
  .../boot/dts/xilinx/zynqmp-zcu104-revA.dts    | 12 +++++++++
  .../boot/dts/xilinx/zynqmp-zcu104-revC.dts    | 12 +++++++++
  5 files changed, 79 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +26 -0

index e284979fd7b1..78ff6a9b3144 100644
@@ -76,6 +76,20 @@ ds36-led {
  			default-state = "on";
  		};
  	};
+
+	ams {
+		compatible = "iio-hwmon";
+		io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
+			<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
+			<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
+			<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
+			<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
+			<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
+			<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
+			<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
+			<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
+			<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
+	};
  };
 
  &modepin_gpio {

@@ -327,6 +341,18 @@ &gpio {
  			  "", "", "", ""; /* 170 - 173 */
  };
 
+&xilinx_ams {
+	status = "okay";
+};
+
+&ams_ps {
+	status = "okay";
+};
+
+&ams_pl {
+	status = "okay";
+};
+
  &zynqmp_dpsub {
  	status = "okay";
  };

arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +17 -0

index c99abb99efcb..c8be41d77cb9 100644
@@ -59,6 +59,15 @@ switch-4 {
  		};
  	};
 
+	iio-hwmon {
+		compatible = "iio-hwmon";
+		io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
+			      <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
+			      <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
+			      <&xilinx_ams 9>, <&xilinx_ams 10>,
+			      <&xilinx_ams 11>, <&xilinx_ams 12>;
+	};
+
  	leds {
  		compatible = "gpio-leds";
  		led-ds2 {

@@ -581,6 +590,14 @@ &watchdog0 {
  	status = "okay";
  };
 
+&xilinx_ams {
+	status = "okay";
+};
+
+&ams_ps {
+	status = "okay";
+};
+
  &zynqmp_dpdma {
  	status = "okay";
  };

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +12 -0

index 5b6403865541..b2e1f3581f6b 100644
@@ -1027,6 +1027,18 @@ &watchdog0 {
  	status = "okay";
  };
 
+&xilinx_ams {
+	status = "okay";
+};
+
+&ams_ps {
+	status = "okay";
+};
+
+&ams_pl {
+	status = "okay";
+};
+
  &zynqmp_dpdma {
  	status = "okay";
  };

arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +12 -0

index a74a2061431a..1f30c37c2e03 100644
@@ -511,6 +511,18 @@ &watchdog0 {
  	status = "okay";
  };
 
+&xilinx_ams {
+	status = "okay";
+};
+
+&ams_ps {
+	status = "okay";
+};
+
+&ams_pl {
+	status = "okay";
+};
+
  &zynqmp_dpdma {
  	status = "okay";
  };

arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +5 -0

index 73972d83ed4d..474744278b97 100644
@@ -523,6 +523,18 @@ &watchdog0 {
  	status = "okay";
  };
 
+&xilinx_ams {
+	status = "okay";
+};
+
+&ams_ps {

SD card is connected with 4 data lines which should be described properly.

Signed-off-by Michal Simek <[email protected]>

---

  arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 1 +
  arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 1 +
  2 files changed, 2 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +1 -0

index 776444714fad..dcc51b3adab0 100644
@@ -136,6 +136,7 @@ &sdhci1 { /* on CC with tuned parameters */
  	disable-wp;
  	xlnx,mio-bank = <1>;
  	assigned-clock-rates = <187498123>;
+	bus-width = <4>;
  };
 
  &gem3 { /* required by spec */

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +0 -0

index 78d082a11492..3384df3d5920 100644

bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT. That's why add it also to Linux to be aligned with bootloader requirement.

Signed-off-by Michal Simek <[email protected]>

---

---
  arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi    |  6 ++++++
  arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts |  3 +++
  arch/arm64/boot/dts/xilinx/zynqmp.dtsi            | 12 ++++++++++++
  3 files changed, 21 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +6 -0

index 581221fdadf1..719ea5d5ae88 100644
@@ -11,30 +11,35 @@
  #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
  / {
  	pss_ref_clk: pss_ref_clk {
+		bootph-all;
  		compatible = "fixed-clock";
  		#clock-cells = <0>;
  		clock-frequency = <33333333>;
  	};
 
  	video_clk: video_clk {
+		bootph-all;
  		compatible = "fixed-clock";
  		#clock-cells = <0>;
  		clock-frequency = <27000000>;
  	};
 
  	pss_alt_ref_clk: pss_alt_ref_clk {
+		bootph-all;
  		compatible = "fixed-clock";
  		#clock-cells = <0>;
  		clock-frequency = <0>;
  	};
 
  	gt_crx_ref_clk: gt_crx_ref_clk {
+		bootph-all;
  		compatible = "fixed-clock";
  		#clock-cells = <0>;
  		clock-frequency = <108000000>;
  	};
 
  	aux_ref_clk: aux_ref_clk {
+		bootph-all;
  		compatible = "fixed-clock";
  		#clock-cells = <0>;
  		clock-frequency = <27000000>;

@@ -43,6 +48,7 @@ aux_ref_clk: aux_ref_clk {
 
  &zynqmp_firmware {
  	zynqmp_clk: clock-controller {
+		bootph-all;
  		#clock-cells = <1>;
  		compatible = "xlnx,zynqmp-clk";
  		clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,

arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +3 -0

index 78ff6a9b3144..8afdf4408a78 100644
@@ -243,17 +243,20 @@ tpm@0 { /* slm9670 - U144 */
 
  &i2c1 {
  	status = "okay";
+	bootph-all;
  	clock-frequency = <400000>;
  	scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
  	sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
 
  	eeprom: eeprom@50 { /* u46 - also at address 0x58 */
+		bootph-all;
  		compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
  		reg = <0x50>;
  		/* WP pin EE_WP_EN connected to slg7x644092@68 */
  	};
 
  	eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
+		bootph-all;
  		compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
  		reg = <0x51>;
  	};

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +11 -0

index d01d4334c95f..51b8349dcacd 100644
@@ -127,6 +127,7 @@ rproc_1_fw_image: memory@3ef00000 {
  	};
 
  	zynqmp_ipi: zynqmp_ipi {
+		bootph-all;
  		compatible = "xlnx,zynqmp-ipi-mailbox";
  		interrupt-parent = <&gic>;
  		interrupts = <0 35 4>;

@@ -136,6 +137,7 @@ zynqmp_ipi: zynqmp_ipi {
  		ranges;
 
  		ipi_mailbox_pmu1: mailbox@ff9905c0 {
+			bootph-all;
  			reg = <0x0 0xff9905c0 0x0 0x20>,
  			      <0x0 0xff9905e0 0x0 0x20>,
  			      <0x0 0xff990e80 0x0 0x20>,

@@ -152,6 +154,7 @@ ipi_mailbox_pmu1: mailbox@ff9905c0 {
  	dcc: dcc {
  		compatible = "arm,dcc";
  		status = "disabled";
+		bootph-all;
  	};
 
  	pmu {

@@ -177,8 +180,10 @@ zynqmp_firmware: zynqmp-firmware {
  			compatible = "xlnx,zynqmp-firmware";
  			#power-domain-cells = <1>;
  			method = "smc";
+			bootph-all;
 
  			zynqmp_power: zynqmp-power {
+				bootph-all;
  				compatible = "xlnx,zynqmp-power";
  				interrupt-parent = <&gic>;
  				interrupts = <0 35 4>;

@@ -258,6 +263,7 @@ r5f-1 {
 
  	amba: axi {
  		compatible = "simple-bus";
+		bootph-all;
  		#address-cells = <2>;
  		#size-cells = <2>;
  		ranges;

@@ -699,6 +705,7 @@ pcie_intc: legacy-interrupt-controller {
  		};
 
  		qspi: spi@ff0f0000 {
+			bootph-all;
  			compatible = "xlnx,zynqmp-qspi-1.0";
  			status = "disabled";
  			clock-names = "ref_clk", "pclk";

@@ -745,6 +752,7 @@ sata: ahci@fd0c0000 {
  		};
 
  		sdhci0: mmc@ff160000 {
+			bootph-all;
  			compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
  			status = "disabled";
  			interrupt-parent = <&gic>;

@@ -759,6 +767,7 @@ sdhci0: mmc@ff160000 {
  		};
 
  		sdhci1: mmc@ff170000 {
+			bootph-all;
  			compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
  			status = "disabled";
  			interrupt-parent = <&gic>;

@@ -851,6 +860,7 @@ ttc3: timer@ff140000 {
  		};
 
  		uart0: serial@ff000000 {
+			bootph-all;
  			compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
  			status = "disabled";
  			interrupt-parent = <&gic>;

@@ -861,6 +871,7 @@ uart0: serial@ff000000 {
  		};
 
  		uart1: serial@ff010000 {
+			bootph-all;
  			compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
  			status = "disabled";
  			interrupt-parent = <&gic>;

Hi,

the series is syncing the latest dt changes based on board status and the latest DT schema.
The patches are based on
https://lore.kernel.org/all/[email protected]/

Thanks,
Michal

Amit Kumar Mahapatra (2):
arm64: zynqmp: Set qspi tx-buswidth to 4
arm64: zynqmp: Add mtd partition for secure OS storage area

Ashok Reddy Soma (1):
arm64: zynqmp: Fix usb node drive strength and slew rate

Michal Simek (15):
arm64: zynqmp: Describe TI phy as ethernet-phy-id
arm64: zynqmp: Fix usb reset over bootmode pins on zcu100
arm64: zynqmp: Sync node name address with reg (mailbox)
arm64: zynqmp: Add dmas, dp, rtc, watchdogs and opp nodes for SOM
arm64: zynqmp: Use assigned-clock-rates for setting up SD clock in SOM
arm64: zynqmp: Used fixed-partitions for QSPI in k26
arm64: zynqmp: Add gpio labels for modepin gpio
arm64: zynqmp: Add pinctrl emmc description to SM-K26
arm64: zynqmp: Switch to ethernet-phy-id in kv260
arm64: zynqmp: Setup clock for DP and DPDMA
arm64: zynqmp: Enable DP driver for SOMs
arm64: zynqmp: Rename ams_ps/pl node names
arm64: zynqmp: Enable AMS on SOM and other zcu10x boards
arm64: zynqmp: Describe bus-width for SD card on KV260
arm64: zynqmp: Add phase tags marking

Piyush Mehta (1):

   arm64: zynqmp: Disable USB3.0 for zc1751-xm016-dc2

Radhey Shyam Pandey (2):
arm64: zynqmp: Add L2 cache nodes
arm64: zynqmp: Add pmu interrupt-affinity

Sai Krishna Potthuri (1):
arm64: zynqmp: Add resets property to sdhci nodes

Srinivas Neeli (1):
arm64: zynqmp: Add linux,code for gpio button

  .../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi |  15 +-
  .../boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso |  20 +-
  .../boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso |  20 +-
  .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts    | 321 +++++++++++++-----
  .../boot/dts/xilinx/zynqmp-zc1232-revA.dts    |   2 +-
  .../boot/dts/xilinx/zynqmp-zc1254-revA.dts    |   2 +-
  .../boot/dts/xilinx/zynqmp-zc1275-revA.dts    |   2 +-
  .../dts/xilinx/zynqmp-zc1751-xm015-dc1.dts    |  10 +-
  .../dts/xilinx/zynqmp-zc1751-xm016-dc2.dts    |  10 +-
  .../dts/xilinx/zynqmp-zc1751-xm018-dc4.dts    |   2 +-
  .../boot/dts/xilinx/zynqmp-zcu100-revC.dts    |  32 +-

  .../boot/dts/xilinx/zynqmp-zcu102-revA.dts    |  42 ++-
  .../boot/dts/xilinx/zynqmp-zcu102-revB.dts    |  25 +-
  .../boot/dts/xilinx/zynqmp-zcu104-revA.dts    |  42 ++-
  .../boot/dts/xilinx/zynqmp-zcu104-revC.dts    |  42 ++-
  .../boot/dts/xilinx/zynqmp-zcu106-revA.dts    |  29 +-
  .../boot/dts/xilinx/zynqmp-zcu111-revA.dts    |  29 +-
  arch/arm64/boot/dts/xilinx/zynqmp.dtsi        |  33 +-
  18 files changed, 513 insertions(+), 165 deletions(-)