Add Support for Orange Pi 5
Subsystems (2)
v3 cover Add Support for Orange Pi 5
Hi,
These series add initial support for Orange Pi 5 and SFC node for RK3588S.
Changes in v3:
* Remove cap-mmc-highspeed property from sdmmc.
* Make vcc_1v1_nldo_s3 an alias of dcdc-reg6 and add regulator-max-microvolt, regulator-min-microvolt properties.
* Make press-threshold-microvolt 1800 for recovery button.
* Remove assigned-clocks from sfc node.
* Drop some properties from sfc node in orangepi5 devicetree.
* Move snps reset properties to rgmii_phy1.
Changes in v2:
* Fix CHECK_DTBS warnings and add dtb to makefile.
* Remove assigned-clock-rates from sfc node and fix wrong interrupts property.
* Remove non-existent adc buttons and add button-recovery instead.
* Remove backlight_1, backlight, vcc12v_dcin, vcc5v0_usbdcin, vcc5v0_usb, combophy_avdd0v85, combophy_avdd1v8, sata0, u2phy0, u2phy0_otg nodes.
* Rename vcc3v3_pcie2x1l2 to vcc3v3_pcie20, vbus5v0_typec to vbus_typec.
* Remove regulator-always-on property from vcc_3v3_sd_s0 and vcc3v3_pcie20.
Muhammed Efe Cetin (3):
dt-bindings: arm: rockchip: Add Orange Pi 5 board
arm64: dts: rockchip: Add sfc node to rk3588s
arm64: dts: rockchip: Add Orange Pi 5
.../devicetree/bindings/arm/rockchip.yaml | 5 + arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588s-orangepi-5.dts | 673 ++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 11 + 4 files changed, 690 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
Signature · 1 line
2.41.0
PATCH v3 1/3 dt-bindings: arm: rockchip: Add Orange Pi 5 board
Add Orange Pi 5 SBC from Xunlong.
--- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+)
Documentation/devicetree/bindings/arm/rockchip.yaml +5 -0
@@ -877,6 +877,11 @@ properties: - xunlong,orangepi-r1-plus-lts - const: rockchip,rk3328 + - description: Xunlong Orange Pi 5 + items: + - const: xunlong,orangepi-5 + - const: rockchip,rk3588s + - description: Zkmagic A95X Z2 items: - const: zkmagic,a95x-z2
Signature · 1 line
2.41.0
Re: [PATCH v3 1/3] dt-bindings: arm: rockchip: Add Orange Pi 5 board
Quoted 13 lines · Muhammed Efe Cetin
Add Orange Pi 5 SBC from Xunlong.
Signed-off-by Muhammed Efe Cetin <[email protected]>--- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+)Documentation/devicetree/bindings/arm/rockchip.yaml +0
-0
Documentation/devicetree/bindings/arm/rockchip.yaml properties: · line 884
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Documentation/devicetree/bindings/arm/rockchip.yaml +5
-0@@ -877,6 +877,11 @@ properties: - xunlong,orangepi-r1-plus-lts - const: rockchip,rk3328 + - description: Xunlong Orange Pi 5 + items: + - const: xunlong,orangepi-5 + - const: rockchip,rk3588s +
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Documentation/devicetree/bindings/arm/rockchip.yaml +0
-0- description: Zkmagic A95X Z2 items: - const: zkmagic,a95x-z2Signature · 1 line
2.41.0
Signature · 2 lines
Best regards, Dhruva Gole <[email protected]>
PATCH v3 2/3 arm64: dts: rockchip: Add sfc node to rk3588s
In reply to Muhammed Efe CetinAdd sfc node to rk3588s.dtsi from downstream kernel.
--- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)
arch/arm64/boot/dts/rockchip/rk3588s.dtsi +11 -0
@@ -1424,6 +1424,17 @@ sata-port@0 { }; }; + sfc: spi@fe2b0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sdmmc: mmc@fe2c0000 { compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe2c0000 0x0 0x4000>;
Signature · 1 line
2.41.0
Re: [PATCH v3 2/3] arm64: dts: rockchip: Add sfc node to rk3588s
Quoted 1 line · Muhammed Efe Cetin
Add sfc node to
rk3588s.dtsifrom downstream kernel.
For those with lesser context, can you please mention what SFC means? I did a quick grep on the compatible and that's how I got to know it's a Serial Flash Controller
Also, not sure what you mean by downstream kernel, where is it located? Why did you feel the need to mention it while upstreaming this patch? Please can you provide more context or drop the downstream part altogether?
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Signed-off-by Muhammed Efe Cetin <[email protected]>--- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)arch/arm64/boot/dts/rockchip/rk3588s.dtsi +1
-0@@ -1424,6 +1424,17 @@ sata-port@0 { }; }; + sfc: spi@fe2b0000 {
arch/arm64/boot/dts/rockchip/rk3588s.dtsi sata-port@0 { · line 1437
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arch/arm64/boot/dts/rockchip/rk3588s.dtsi +10
-0+ compatible = "rockchip,sfc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +
Otherwise, looks okay.
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arch/arm64/boot/dts/rockchip/rk3588s.dtsi +0
-0sdmmc: mmc@fe2c0000 { compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe2c0000 0x0 0x4000>;Signature · 1 line
2.41.0
Signature · 7 lines
Best regards, Dhruva Gole <[email protected]> _______________________________________________ Linux-rockchip mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-rockchip
PATCH v3 3/3 arm64: dts: rockchip: Add Orange Pi 5
In reply to Muhammed Efe CetinAdd initial support for OPi5 that includes support for USB2, PCIe2, Sata, Sdmmc, SPI Flash, PMIC.
--- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588s-orangepi-5.dts | 673 ++++++++++++++++++ 2 files changed, 674 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
arch/arm64/boot/dts/rockchip/Makefile +1 -0
@@ -105,3 +105,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts new file +673 -0
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Signature · 1 line
2.41.0
Re: [PATCH v3 3/3] arm64: dts: rockchip: Add Orange Pi 5
Hi,
Quoted 11 lines · Muhammed Efe Cetin
Add initial support for OPi5 that includes support for USB2, PCIe2, Sata, Sdmmc, SPI Flash, PMIC.
Signed-off-by Muhammed Efe Cetin <[email protected]>Reviewed-by Ondřej Jirman <[email protected]>--- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588s-orangepi-5.dts | 673 ++++++++++++++++++ 2 files changed, 674 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
...
Can you provide some sort of documentation on how I can build and boot the kernel on this board? I was unable to use the upstream arm64 defconfig with this exact series applied to boot the board.
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arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts new file +6
-0+ +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; +
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts line 231
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arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts new file +10
-0+ hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source;
Are you able to actually use rtc as a wakeup source? I tried this on a downstream kernel that I mention below..
rtcwake -s 10 -m mem
didn't actually seem to wake the device from deepsleep after 10 seconds. Do you know what other pins I can use as wakeup sources?
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts line 237
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arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts new file +6
-0+ }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22";
Just wondering, can you please give some logs of the board with eth working? The image that I have from opi seems to fail eth? As in I am not able to see any ip address. here are the logs:
https://gist.github.com/DhruvaG2000/eda2762e35013c8d5ac9f37e818103a3
...
Signature · 2 lines
Best regards, Dhruva Gole <[email protected]>
Re: [PATCH v3 3/3] arm64: dts: rockchip: Add Orange Pi 5
Hello,
Quoted 14 lines · Dhruva Gole
Hi,
Quoted 11 lines · Muhammed Efe Cetin
Add initial support for OPi5 that includes support for USB2, PCIe2, Sata, Sdmmc, SPI Flash, PMIC.
Signed-off-by Muhammed Efe Cetin <[email protected]>Reviewed-by Ondřej Jirman <[email protected]>--- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588s-orangepi-5.dts | 673 ++++++++++++++++++ 2 files changed, 674 insertions(+)create mode 100644
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
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...
Can you provide some sort of documentation on how I can build and boot the kernel on this board? I was unable to use the upstream arm64 defconfig with this exact series applied to boot the board.
What was wrong when you tried to compile & boot the board? Can you provide some logs?
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arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts new file +6
-0+ +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; +arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts line 231
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arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts new file +10
-0+ hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source;Are you able to actually use rtc as a wakeup source? I tried this on a downstream kernel that I mention below..
Quoted 4 lines
rtcwake -s 10 -m mem
didn't actually seem to wake the device from deepsleep after 10 seconds. Do you know what other pins I can use as wakeup sources?
No, i've not tried it before.
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arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts line 237
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arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts new file +6
-0+ }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22";Just wondering, can you please give some logs of the board with eth working? The image that I have from opi seems to fail eth? As in I am not able to see any ip address. here are the logs:
Unfortunately the board is not near me currently. However, i was able to use GMAC ethernet in both the upstreram and downstream kernels. Did you try any images other than Orange Pi ones?
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Linux-rockchip mailing list
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Re: [PATCH v3 3/3] arm64: dts: rockchip: Add Orange Pi 5
Hello,
Quoted 17 lines · Muhammed Efe Cetin
Hello,
Quoted 14 lines · Dhruva Gole
Hi,
Quoted 11 lines · Muhammed Efe Cetin
Add initial support for OPi5 that includes support for USB2, PCIe2, Sata, Sdmmc, SPI Flash, PMIC.
Signed-off-by Muhammed Efe Cetin <[email protected]>Reviewed-by Ondřej Jirman <[email protected]>--- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588s-orangepi-5.dts | 673 ++++++++++++++++++ 2 files changed, 674 insertions(+)create mode 100644
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
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...
Can you provide some sort of documentation on how I can build and boot the kernel on this board? I was unable to use the upstream arm64 defconfig with this exact series applied to boot the board.
What was wrong when you tried to compile & boot the board? Can you provide some logs?
Umm don't have logs at hand, but I remember it didn't really reach the linux first line either, it went into sort of a bootloop just after the uboot stage.
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arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts new file +6
-0+ +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; +arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts line 231
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arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts new file +10
-0+ hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source;Are you able to actually use rtc as a wakeup source? I tried this on a downstream kernel that I mention below..
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rtcwake -s 10 -m mem
didn't actually seem to wake the device from deepsleep after 10 seconds. Do you know what other pins I can use as wakeup sources?
No, i've not tried it before.
ah okay
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arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts line 237
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arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts new file +6
-0+ }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22";Just wondering, can you please give some logs of the board with eth working? The image that I have from opi seems to fail eth? As in I am not able to see any ip address. here are the logs:
Quoted 3 lines
Unfortunately the board is not near me currently. However, i was able to use GMAC ethernet in both the upstreram and downstream kernels. Did you try any images other than Orange Pi ones?
Nope, are there any other images that maybe more suitable? Please can you point me to them?
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Signature · 2 lines
Best regards, Dhruva Gole <[email protected]>
Re: [PATCH v3 3/3] arm64: dts: rockchip: Add Orange Pi 5
Hi,
Quoted 26 lines · Dhruva Gole
Hello,
Quoted 23 lines · Muhammed Efe Cetin
Hello,
Quoted 19 lines · Dhruva Gole
Hi,
Quoted 11 lines · Muhammed Efe Cetin
Add initial support for OPi5 that includes support for USB2, PCIe2, Sata, Sdmmc, SPI Flash, PMIC.
Signed-off-by Muhammed Efe Cetin <[email protected]>Reviewed-by Ondřej Jirman <[email protected]>--- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588s-orangepi-5.dts | 673 ++++++++++++++++++ 2 files changed, 674 insertions(+)create mode 100644
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts...
Can you provide some sort of documentation on how I can build and boot the kernel on this board? I was unable to use the upstream arm64 defconfig with this exact series applied to boot the board.
Quoted 5 lines
Quoted 1 line
What was wrong when you tried to compile & boot the board? Can you provide some logs?
Umm don't have logs at hand, but I remember it didn't really reach the linux first line either, it went into sort of a bootloop just after the uboot stage.
Hmm there might be issue with your uboot compilation. It'd be better if you provide useful logs.
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arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts new file +6
-0+ +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; +arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts line 231
Quoted 10 lines
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts new file +10
-0+ hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source;Are you able to actually use rtc as a wakeup source? I tried this on a downstream kernel that I mention below..
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rtcwake -s 10 -m mem
didn't actually seem to wake the device from deepsleep after 10 seconds. Do you know what other pins I can use as wakeup sources?
No, i've not tried it before.
ah okay
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arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts line 237
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arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts new file +6
-0+ }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22";Just wondering, can you please give some logs of the board with eth working? The image that I have from opi seems to fail eth? As in I am not able to see any ip address. here are the logs:
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Unfortunately the board is not near me currently. However, i was able to use GMAC ethernet in both the upstreram and downstream kernels. Did you try any images other than Orange Pi ones?
Nope, are there any other images that maybe more suitable? Please can you point me to them?
You can check the images below the Third Party Images section in OPi's download page. GMAC should work properly with most of them.
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