Device Tree support for SH7751 based board
Subsystems (15)
Yoshinori Sato
maintainerv6 cover Device Tree support for SH7751 based board
This is an updated version of something I wrote about 7 years ago. Minimum support for R2D-plus and LANDISK.
I think R2D-1 will work if you add AX88796 to dts.
And board-specific functions and SCI's SPI functions are not supported.
You can get it working with qemu found here.
https://gitlab.com/yoshinori.sato/qemu/-/tree/landisk
v6 changes.
- pci-sh7751: merge register define.
- pci-sh7751: use 'dma-ranges' property.
- pci-sh7751: rename general PCI properties.
- sm501 and sm501fb: Re-design Device Tree properties.
- sh/kernel/setup: cleanup command line setup.
- irq-sh7751.c: some cleanup.
v5 changes.
- pci-sh7751: revert header changes. and some fix in previuous driver.
- sh/kernel/iomap.c: Use SH io functions.
- sm501 and sm501fb: re-write DT support.
v4 changes.
- cpg-sh7750: use clk-divider and clk-gate.
- pci-sh7751: unified header files to old PCI driver.
- irq-renesas-sh7751: IPR registers direct mapping.
- irq-renesas-sh7751irl: useful register bit mapping.
- sm501 and sm501fb: re-write dt parser.
- j2_minus: fix build error.
- dt-binding schema: fix some errors.
- *.dts: cleanup.
v3 changes.
- Rewrite clk drivers.
- Added sh_tmu to OF support.
- Cleanup PCI stuff.
- Update sm501 and sm501fb OF support.
- Update devicetree and documents.
v2 changes.
- Rebasing v6,6-rc1
- re-write irqchip driver.
- Add binding documents.
- Cleanup review comment.
Yoshinori Sato (37):
sh: passing FDT address to kernel startup.
sh: Kconfig unified OF supported targets.
sh: Enable OF support for build and configuration.
dt-bindings: interrupt-controller: Add header for Renesas SH3/4 INTC.
sh: GENERIC_IRQ_CHIP support for CONFIG_OF=y
sh: kernel/setup Update DT support.
sh: Fix COMMON_CLK support in CONFIG_OF=y.
clocksource: sh_tmu: CLOCKSOURCE support.
dt-bindings: timer: renesas,tmu: add renesas,tmu-sh7750
sh: Common PCI Framework driver support.
pci: pci-sh7751: Add SH7751 PCI driver
dt-bindings: pci: pci-sh7751: Add SH7751 PCI
dt-bindings: clock: sh7750-cpg: Add renesas,sh7750-cpg header.
clk: Compatible with narrow registers
clk: renesas: Add SH7750/7751 CPG Driver
irqchip: Add SH7751 INTC driver
dt-bindings: interrupt-controller: renesas,sh7751-intc: Add
json-schema
irqchip: SH7751 external interrupt encoder with enable gate.
dt-bindings: interrupt-controller: renesas,sh7751-irl-ext: Add
json-schema
serial: sh-sci: fix SH4 OF support.
dt-bindings: serial: renesas,scif: Add scif-sh7751.
dt-bindings: display: smi,sm501: SMI SM501 binding json-schema
mfd: sm501: Convert platform_data to OF property
dt-binding: sh: cpus: Add SH CPUs json-schema
dt-bindings: vendor-prefixes: Add iodata
dt-bindings: vendor-prefixes: Add smi
dt-bindings: ata: ata-generic: Add new targets
dt-bindings: soc: renesas: sh: Add SH7751 based target
sh: SH7751R SoC Internal peripheral definition dtsi.
sh: add RTS7751R2D Plus DTS
sh: Add IO DATA LANDISK dts
sh: Add IO DATA USL-5P dts
sh: j2_mimas_v2.dts update
sh: Add dtbs target support.
sh: RTS7751R2D Plus OF defconfig
sh: LANDISK OF defconfig
sh: j2_defconfig: update
.../devicetree/bindings/ata/ata-generic.yaml | 2 + .../bindings/clock/renesas,sh7750-cpg.yaml | 103 ++++ .../bindings/display/smi,sm501.yaml | 417 +++++++++++++++ .../renesas,sh7751-intc.yaml | 105 ++++ .../renesas,sh7751-irl-ext.yaml | 72 +++ .../bindings/pci/renesas,sh7751-pci.yaml | 150 ++++++ .../bindings/serial/renesas,scif.yaml | 1 + .../devicetree/bindings/sh/cpus.yaml | 74 +++ .../devicetree/bindings/soc/renesas/sh.yaml | 32 ++ .../bindings/timer/renesas,tmu.yaml | 67 ++- .../devicetree/bindings/vendor-prefixes.yaml | 4 + arch/sh/Kconfig | 12 +- arch/sh/boards/Kconfig | 24 +- arch/sh/boards/of-generic.c | 28 +- arch/sh/boot/compressed/head_32.S | 5 +- arch/sh/boot/dts/Makefile | 5 + arch/sh/boot/dts/j2_mimas_v2.dts | 2 +- arch/sh/boot/dts/landisk.dts | 75 +++ arch/sh/boot/dts/rts7751r2dplus.dts | 180 +++++++ arch/sh/boot/dts/sh7751r.dtsi | 152 ++++++ arch/sh/boot/dts/usl-5p.dts | 83 +++ arch/sh/configs/j2_defconfig | 11 +- arch/sh/configs/landisk-of_defconfig | 104 ++++ arch/sh/configs/rts7751r2dplus-of_defconfig | 80 +++ arch/sh/drivers/Makefile | 2 + arch/sh/include/asm/io.h | 8 + arch/sh/include/asm/irq.h | 10 +- arch/sh/include/asm/pci.h | 4 + arch/sh/kernel/cpu/Makefile | 6 +- arch/sh/kernel/cpu/irq/imask.c | 17 + arch/sh/kernel/cpu/sh4/Makefile | 3 + arch/sh/kernel/iomap.c | 18 + arch/sh/kernel/setup.c | 33 +- arch/sh/kernel/time.c | 12 + drivers/clk/clk-divider.c | 56 +- drivers/clk/clk-gate.c | 56 +- drivers/clk/renesas/Kconfig | 16 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-sh7750.c | 498 ++++++++++++++++++ drivers/clocksource/sh_tmu.c | 161 ++++-- drivers/irqchip/Kconfig | 15 + drivers/irqchip/Makefile | 3 + drivers/irqchip/irq-renesas-sh7751.c | 313 +++++++++++ drivers/irqchip/irq-renesas-sh7751irl.c | 228 ++++++++ drivers/mfd/sm501.c | 436 +++++++++++++++ drivers/pci/controller/Kconfig | 9 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pci-sh7751.c | 392 ++++++++++++++ drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/sh-sci.c | 6 +- drivers/video/fbdev/sm501fb.c | 106 ++++ include/dt-bindings/clock/sh7750-cpg.h | 26 + .../renesas,sh7751-intc.h | 19 + include/linux/clk-provider.h | 22 +- include/linux/sh_intc.h | 7 +- 55 files changed, 4096 insertions(+), 178 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml create mode 100644 Documentation/devicetree/bindings/display/smi,sm501.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml create mode 100644 Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml create mode 100644 Documentation/devicetree/bindings/sh/cpus.yaml create mode 100644 Documentation/devicetree/bindings/soc/renesas/sh.yaml create mode 100644 arch/sh/boot/dts/landisk.dts create mode 100644 arch/sh/boot/dts/rts7751r2dplus.dts create mode 100644 arch/sh/boot/dts/sh7751r.dtsi create mode 100644 arch/sh/boot/dts/usl-5p.dts create mode 100644 arch/sh/configs/landisk-of_defconfig create mode 100644 arch/sh/configs/rts7751r2dplus-of_defconfig create mode 100644 drivers/clk/renesas/clk-sh7750.c create mode 100644 drivers/irqchip/irq-renesas-sh7751.c create mode 100644 drivers/irqchip/irq-renesas-sh7751irl.c create mode 100644 drivers/pci/controller/pci-sh7751.c create mode 100644 include/dt-bindings/clock/sh7750-cpg.h create mode 100644 include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 1/37 sh: passing FDT address to kernel startup.
R4 is caller saved in SH ABI.
Save it so it doesn't get corrupted until it's needed for initialization.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/boot/compressed/head_32.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
arch/sh/boot/compressed/head_32.S +3 -2
@@ -15,7 +15,8 @@ startup: /* Load initial status register */ mov.l init_sr, r1 ldc r1, sr - + /* Save FDT address */ + mov r4, r13 /* Move myself to proper location if necessary */ mova 1f, r0 mov.l 1f, r2
@@ -84,7 +85,7 @@ l1: /* Jump to the start of the decompressed kernel */ mov.l kernel_start_addr, r0 jmp @r0 - nop + mov r13, r4 .align 2 bss_start_addr:
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 01/37] sh: passing FDT address to kernel startup.
Quoted 4 lines · Yoshinori Sato
R4 is caller saved in SH ABI.
Save it so it doesn't get corrupted until it's needed for initialization.Signed-off-by Yoshinori Sato <[email protected]>
My
Reviewed-by Geert Uytterhoeven <[email protected]>
on v3 is still valid.
Gr{oetje,eeting}s,
Geert
Signature · 5 lines
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Yoshinori Sato
maintainerPATCH v6 2/37 sh: Kconfig unified OF supported targets.
In reply to Yoshinori SatoTargets that support OF should be treated as one board.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/Kconfig | 1 + arch/sh/boards/Kconfig | 24 ++++++++++++++---------- 2 files changed, 15 insertions(+), 10 deletions(-)
arch/sh/Kconfig +1 -0
@@ -710,6 +710,7 @@ choice prompt "Kernel command line" optional default CMDLINE_OVERWRITE + depends on !OF || USE_BUILTIN_DTB help Setting this option allows the kernel command line arguments to be set.
arch/sh/boards/Kconfig +14 -10
@@ -19,16 +19,9 @@ config SH_DEVICE_TREE select TIMER_OF select COMMON_CLK select GENERIC_CALIBRATE_DELAY - -config SH_JCORE_SOC - bool "J-Core SoC" - select SH_DEVICE_TREE - select CLKSRC_JCORE_PIT - select JCORE_AIC - depends on CPU_J2 - help - Select this option to include drivers core components of the - J-Core SoC, including interrupt controllers and timers. + select GENERIC_IRQ_CHIP + select SYS_SUPPORTS_PCI + select GENERIC_PCI_IOMAP if PCI config SH_SOLUTION_ENGINE bool "SolutionEngine"
@@ -293,6 +286,7 @@ config SH_LANDISK bool "LANDISK" depends on CPU_SUBTYPE_SH7751R select HAVE_PCI + select SYS_SUPPORTS_PCI help I-O DATA DEVICE, INC. "LANDISK Series" support.
@@ -369,6 +363,16 @@ config SH_APSH4AD0A help Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A. +config SH_OF_BOARD + bool "General Open Firmware boards" + select SH_DEVICE_TREE + select CLKSRC_JCORE_PIT if CPU_J2 + select JCORE_AIC if CPU_J2 + select HAVE_PCI if CPU_SUBTYPE_SH7751R + help + This board means general OF supported targets. + + source "arch/sh/boards/mach-r2d/Kconfig" source "arch/sh/boards/mach-highlander/Kconfig" source "arch/sh/boards/mach-sdk7780/Kconfig"
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 02/37] sh: Kconfig unified OF supported targets.
Hi Sato-san,
Quoted 3 lines · Yoshinori Sato
Targets that support OF should be treated as one board.
Signed-off-by Yoshinori Sato <[email protected]>
Thanks for your patch!
arch/sh/Kconfig choice · line 713
Quoted 7 lines
arch/sh/Kconfig +1
-0@@ -710,6 +710,7 @@ choice prompt "Kernel command line" optional default CMDLINE_OVERWRITE + depends on !OF || USE_BUILTIN_DTB
This is still useful in the generic OF case.
I think it would be good to model this similar to what arm/arm64/riscv are using (from bootloader / extend / force).
Quoted 36 lines
arch/sh/Kconfig +0
-0help Setting this option allows the kernel command line arguments to be set.arch/sh/boards/Kconfig +4
-10@@ -19,16 +19,9 @@ config SH_DEVICE_TREE select TIMER_OF select COMMON_CLK select GENERIC_CALIBRATE_DELAY - -config SH_JCORE_SOC - bool "J-Core SoC" - select SH_DEVICE_TREE - select CLKSRC_JCORE_PIT - select JCORE_AIC - depends on CPU_J2 - help - Select this option to include drivers core components of the - J-Core SoC, including interrupt controllers and timers. + select GENERIC_IRQ_CHIP + select SYS_SUPPORTS_PCI + select GENERIC_PCI_IOMAP if PCI config SH_SOLUTION_ENGINE bool "SolutionEngine"@@ -293,6 +286,7 @@ config SH_LANDISK bool "LANDISK" depends on CPU_SUBTYPE_SH7751R select HAVE_PCI + select SYS_SUPPORTS_PCI help I-O DATA DEVICE, INC. "LANDISK Series" support.
arch/sh/boards/Kconfig config SH_APSH4AD0A · line 370
Quoted 8 lines
arch/sh/boards/Kconfig +5
-0@@ -369,6 +363,16 @@ config SH_APSH4AD0A help Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A. +config SH_OF_BOARD + bool "General Open Firmware boards" + select SH_DEVICE_TREE + select CLKSRC_JCORE_PIT if CPU_J2 + select JCORE_AIC if CPU_J2
Please move these selects to CPU_J2 instead...
arch/sh/boards/Kconfig config SH_APSH4AD0A · line 371
Quoted 1 line
arch/sh/boards/Kconfig +1
-0+ select HAVE_PCI if CPU_SUBTYPE_SH7751R
... and this to CPU_SUBTYPE_SH7751R, else it will become a long unmaintainable list soon...
arch/sh/boards/Kconfig config SH_APSH4AD0A · line 375
Quoted 4 lines
arch/sh/boards/Kconfig +4
-0+ help + This board means general OF supported targets. + +
Gr{oetje,eeting}s,
Geert
Signature · 5 lines
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Yoshinori Sato
maintainerPATCH v6 3/37 sh: Enable OF support for build and configuration.
In reply to Yoshinori SatoIRQ, CLK and PCI will be migrated to a common driver framework. So if OF, disable the SH specific drivers.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/Kconfig | 11 ++++++----- arch/sh/drivers/Makefile | 2 ++ arch/sh/kernel/cpu/Makefile | 9 +++++++-- arch/sh/kernel/cpu/sh4/Makefile | 3 +++ 4 files changed, 18 insertions(+), 7 deletions(-)
arch/sh/Kconfig +6 -5
@@ -65,10 +65,10 @@ config SUPERH select MODULES_USE_ELF_RELA select NEED_SG_DMA_LENGTH select NO_DMA if !MMU && !DMA_COHERENT - select NO_GENERIC_PCI_IOPORT_MAP if PCI + select NO_GENERIC_PCI_IOPORT_MAP if !SH_DEVICE_TREE select OLD_SIGACTION select OLD_SIGSUSPEND - select PCI_DOMAINS if PCI + select PCI_DOMAINS if PCI && !SH_DEVICE_TREE select PERF_EVENTS select PERF_USE_VMALLOC select RTC_LIB
@@ -152,7 +152,7 @@ menu "System type" # config CPU_SH2 bool - select SH_INTC + select SH_INTC if !SH_DEVICE_TREE config CPU_SH2A bool
@@ -178,7 +178,7 @@ config CPU_SH4 select CPU_HAS_INTEVT select CPU_HAS_SR_RB select CPU_HAS_FPU if !CPU_SH4AL_DSP - select SH_INTC + select SH_INTC if !SH_DEVICE_TREE select SYS_SUPPORTS_SH_TMU config CPU_SH4A
@@ -521,6 +521,7 @@ config SH_PCLK_FREQ config SH_CLK_CPG def_bool y + depends on !COMMON_CLK config SH_CLK_CPG_LEGACY depends on SH_CLK_CPG
@@ -665,7 +666,7 @@ config BUILTIN_DTB_SOURCE kernel. config ZERO_PAGE_OFFSET - hex + hex "Zero page offset" default "0x00010000" if PAGE_SIZE_64KB || SH_RTS7751R2D || \ SH_7751_SOLUTION_ENGINE default "0x00004000" if PAGE_SIZE_16KB || SH_SH03
arch/sh/drivers/Makefile +2 -0
@@ -5,6 +5,8 @@ obj-y += dma/ platform_early.o +ifndef CONFIG_SH_DEVICE_TREE obj-$(CONFIG_PCI) += pci/ +endif obj-$(CONFIG_PUSH_SWITCH) += push-switch.o obj-$(CONFIG_HEARTBEAT) += heartbeat.o
arch/sh/kernel/cpu/Makefile +7 -2
@@ -16,6 +16,11 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/ # Common interfaces. obj-$(CONFIG_SH_ADC) += adc.o +ifndef CONFIG_COMMON_CLK +obj-y += clock.o obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o - -obj-y += irq/ init.o clock.o fpu.o pfc.o proc.o +endif +ifndef CONFIG_GENERIC_IRQ_CHIP +obj-y += irq/ +endif +obj-y += init.o fpu.o pfc.o proc.o
arch/sh/kernel/cpu/sh4/Makefile +3 -0
@@ -15,6 +15,7 @@ perf-$(CONFIG_CPU_SUBTYPE_SH7750) := perf_event.o perf-$(CONFIG_CPU_SUBTYPE_SH7750S) := perf_event.o perf-$(CONFIG_CPU_SUBTYPE_SH7091) := perf_event.o +ifndef CONFIG_SH_DEVICE_TREE # CPU subtype setup obj-$(CONFIG_CPU_SUBTYPE_SH7750) += setup-sh7750.o obj-$(CONFIG_CPU_SUBTYPE_SH7750R) += setup-sh7750.o
@@ -29,5 +30,7 @@ ifndef CONFIG_CPU_SH4A clock-$(CONFIG_CPU_SH4) := clock-sh4.o endif +endif # CONFIG_SH_DEVICE_TREE + obj-y += $(clock-y) obj-$(CONFIG_PERF_EVENTS) += $(perf-y)
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 4/37 dt-bindings: interrupt-controller: Add header for Renesas SH3/4 INTC.
In reply to Yoshinori SatoRenesas SH7751 Interrupt controller priority register define.
Signed-off-by Yoshinori Sato <[email protected]>
--- .../renesas,sh7751-intc.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h
include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h new file +19 -0
@@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +* +* SH3/4 INTC IPR register offsets (Address / bits) +*/ + +#ifndef __DT_BINDINGS_RENESAS_SH7751_INTC +#define __DT_BINDINGS_RENESAS_SH7751_INTC + +#define IPRA 0 +#define IPRB 4 +#define IPRC 8 +#define IPRD 12 +#define INTPRI00 256 +#define IPR_B12 12 +#define IPR_B8 8 +#define IPR_B4 4 +#define IPR_B0 0 + +#endif
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 04/37] dt-bindings: interrupt-controller: Add header for Renesas SH3/4 INTC.
Quoted 2 lines · Yoshinori Sato
Renesas SH7751 Interrupt controller priority register define.
Still not a binding.
Some parts of my comments are implemented, others are just ignored (dropping the file, fixing full stop in commit msg). This is confusing. I don't know. Shall I just NAK it to make it clear?
NAK
Best regards,
Krzysztof
Yoshinori Sato
maintainerPATCH v6 5/37 sh: GENERIC_IRQ_CHIP support for CONFIG_OF=y
In reply to Yoshinori SatoRemove unused function prototype.
Add helper update_sr_imask. use for SH7751 irq driver. Add stub intc_finalize.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/include/asm/io.h | 2 ++ arch/sh/include/asm/irq.h | 10 ++++++++-- arch/sh/kernel/cpu/Makefile | 5 +---- arch/sh/kernel/cpu/irq/imask.c | 17 +++++++++++++++++ include/linux/sh_intc.h | 7 ++++++- 5 files changed, 34 insertions(+), 7 deletions(-)
arch/sh/include/asm/io.h +2 -0
@@ -121,7 +121,9 @@ __BUILD_MEMORY_STRING(__raw_, q, u64)#define ioport_map ioport_map#define ioport_unmap ioport_unmap +#ifndef CONFIG_SH_DEVICE_TREE #define pci_iounmap pci_iounmap +#endif #define ioread8 ioread8#define ioread16 ioread16
arch/sh/include/asm/irq.h +8 -2
@@ -16,8 +16,8 @@/* * Simple Mask Register Support */ -extern void make_maskreg_irq (unsigned int irq); -extern unsigned short *irq_mask_register; + +void update_sr_imask (unsigned int irq,bool enable);/* * PINT IRQs
@@ -54,4 +54,10 @@ extern void irq_finish(unsigned int irq);#include <asm-generic/irq.h> +/* SH3/4 INTC stuff */ +/* IRL level 0 - 15 */ +#define NR_IRL 15 +/* IRL0 -> IRQ16 */ +#define IRL_BASE_IRQ 16 +#endif /* __ASM_SH_IRQ_H */
arch/sh/kernel/cpu/Makefile +1 -4
@@ -20,7 +20,4 @@ ifndef CONFIG_COMMON_CLK obj-y += clock.o obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o endif -ifndef CONFIG_GENERIC_IRQ_CHIP -obj-y += irq/ -endif -obj-y += init.o fpu.o pfc.o proc.o +obj-y += init.o fpu.o pfc.o proc.o irq/
arch/sh/kernel/cpu/irq/imask.c +17 -0
@@ -51,6 +51,7 @@ static inline void set_interrupt_registers(int ip) : "t"); } +#ifndef CONFIG_GENERIC_IRQ_CHIP static void mask_imask_irq (struct irq_data *data) {unsigned int irq = data->irq;
@@ -83,3 +84,19 @@ void make_imask_irq(unsigned int irq)irq_set_chip_and_handler_name (irq, &imask_irq_chip, handle_level_irq, "level"); } +#else +void update_sr_imask (unsigned int irq,bool enable) +{ +if (enable) { +set_bit (irq, imask_mask); + interrupt_priority =IMASK_PRIORITY - +find_first_bit (imask_mask,IMASK_PRIORITY ); + }else { +clear_bit (irq, imask_mask); +if (interrupt_priority <IMASK_PRIORITY - irq) + interrupt_priority =IMASK_PRIORITY - irq; + } +set_interrupt_registers (interrupt_priority); +} +EXPORT_SYMBOL (update_sr_imask); +#endif
include/linux/sh_intc.h +6 -1
@@ -139,8 +139,13 @@ struct intc_desc symbol __initdata = { \int register_intc_controller (struct intc_desc *desc);int intc_set_priority (unsigned int irq,unsigned int prio);int intc_irq_lookup (const char *chipname,intc_enum enum_id); +#ifndef CONFIG_SH_DEVICE_TREE void intc_finalize (void ); - +#else +static inline void intc_finalize (void ) +{ +} +#endif #ifdef CONFIG_INTC_USERIMASK int register_intc_userimask (unsigned long addr);#else
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 6/37 sh: kernel/setup Update DT support.
In reply to Yoshinori SatoFix extrnal fdt initialize and bootargs.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/kernel/setup.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-)
arch/sh/kernel/setup.c +24 -9
@@ -30,6 +30,7 @@#include <linux/memblock.h> #include <linux/of.h> #include <linux/of_fdt.h> +#include <linux/libfdt.h> #include <linux/uaccess.h> #include <uapi/linux/mount.h> #include <asm/io.h>
@@ -269,8 +270,20 @@ void __ref sh_fdt_init(phys_addr_t dt_phys)void __init setup_arch (char **cmdline_p) { +#if defined(CONFIG_OF ) && defined(CONFIG_OF_EARLY_FLATTREE ) +if (IS_ENABLED (CONFIG_USE_BUILTIN_DTB )) { +/* Relocate Embedded DTB */ +unflatten_and_copy_device_tree (); + }else if (initial_boot_params) { +/* Reserve external DTB area */ +memblock_reserve (__pa (initial_boot_params), +fdt_totalsize (initial_boot_params)); +unflatten_device_tree (); + } +#endif enable_mmu (); +#ifndef CONFIG_OF ROOT_DEV =old_decode_dev (ORIG_ROOT_DEV ); printk(KERN_NOTICE "Boot params:\n"
@@ -299,6 +312,8 @@ void __init setup_arch(char **cmdline_p) bss_resource.start =virt_to_phys (__bss_start); bss_resource.end =virt_to_phys (__bss_stop)-1 ; +#endif +#ifdef CONFIG_CMDLINE_OVERWRITE strscpy (command_line,CONFIG_CMDLINE ,sizeof (command_line));#else
@@ -310,9 +325,17 @@ void __init setup_arch(char **cmdline_p)#endif /* Save unparsed command line copy for /proc/cmdline */ +#ifndef CONFIG_OF memcpy (boot_command_line, command_line,COMMAND_LINE_SIZE ); *cmdline_p = command_line; - +#else +if (!initial_boot_params) { +memcpy (boot_command_line, command_line,COMMAND_LINE_SIZE ); + *cmdline_p = command_line; + }else { + *cmdline_p = boot_command_line; + } +#endif parse_early_param ();plat_early_device_setup ();
@@ -322,14 +345,6 @@ void __init setup_arch(char **cmdline_p)/* Let earlyprintk output early console messages */ sh_early_platform_driver_probe ("earlyprintk" ,1 ,1 ); -#ifdef CONFIG_OF_EARLY_FLATTREE -#ifdef CONFIG_USE_BUILTIN_DTB -unflatten_and_copy_device_tree (); -#else -unflatten_device_tree (); -#endif -#endif -paging_init ();/* Perform the machine specific initialisation */
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 7/37 sh: Fix COMMON_CLK support in CONFIG_OF=y.
In reply to Yoshinori SatoInitialize the clock and timer using the COMMON_CLK procedure. sh's earlytimer mechanism doesn't work properly in OF, so timer initialization is delayed.
If CONFIG_OF=y, perform the general timer initialization procedure.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/boards/of-generic.c | 28 ++++------------------------ arch/sh/kernel/time.c | 12 ++++++++++++ 2 files changed, 16 insertions(+), 24 deletions(-)
arch/sh/boards/of-generic.c +4 -24
@@ -8,6 +8,7 @@#include <linux/of.h> #include <linux/of_clk.h> #include <linux/of_fdt.h> +#include <linux/of_platform.h> #include <linux/clocksource.h> #include <linux/irqchip.h> #include <asm/machvec.h>
@@ -98,16 +99,7 @@ static void sh_of_smp_probe(void)#endif -static void noop (void ) -{ -} - -static int noopi (void ) -{ -return 0 ; -} - -static void __init sh_of_mem_reserve (void ) +static void __init sh_of_mem_init (void ) {early_init_fdt_reserve_self ();early_init_fdt_scan_reserved_mem ();
@@ -140,25 +132,13 @@ static void __init sh_of_init_irq(void)irqchip_init (); } -static int __init sh_of_clk_init (void ) -{ -#ifdef CONFIG_COMMON_CLK -/* Disabled pending move to COMMON_CLK framework. */ -pr_info ("SH generic board support: scanning for clk providers\n" ); -of_clk_init (NULL ); -#endif -return 0 ; -} - static struct sh_machine_vector __initmv sh_of_generic_mv = { .mv_setup = sh_of_setup, .mv_name ="devicetree" ,/* replaced by DT root's model */ .mv_irq_demux = sh_of_irq_demux, .mv_init_irq = sh_of_init_irq, - .mv_clk_init = sh_of_clk_init, - .mv_mode_pins = noopi, - .mv_mem_init = noop, - .mv_mem_reserve = sh_of_mem_reserve, + .mv_mode_pins = generic_mode_pins, + .mv_mem_init = sh_of_mem_init, };struct sh_clk_ops ;
arch/sh/kernel/time.c +12 -0
@@ -19,7 +19,9 @@#include <asm/clock.h> #include <asm/rtc.h> #include <asm/platform_early.h> +#include <linux/of_clk.h> +#ifndef CONFIG_SH_DEVICE_TREE static void __init sh_late_time_init (void ) {/*
@@ -43,3 +45,13 @@ void __init time_init(void) late_time_init = sh_late_time_init; } +#else +/* CONFIG_SH_DEVICE_TREE */ +void __init time_init (void ) +{ +pr_info ("SH generic board support: scanning for clk providers\n" ); + +of_clk_init (NULL ); +timer_probe (); +} +#endif
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 8/37 clocksource: sh_tmu: CLOCKSOURCE support.
In reply to Yoshinori SatoAllows initialization as CLOCKSOURCE.
Signed-off-by Yoshinori Sato <[email protected]>
--- drivers/clocksource/sh_tmu.c | 161 +++++++++++++++++++++++------------ 1 file changed, 106 insertions(+), 55 deletions(-)
drivers/clocksource/sh_tmu.c +106 -55
@@ -17,6 +17,8 @@#include <linux/irq.h> #include <linux/module.h> #include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/pm_domain.h> #include <linux/pm_runtime.h>
@@ -65,6 +67,7 @@ struct sh_tmu_device {bool has_clockevent;bool has_clocksource; +const char *name; };#define TSTR -1/* shared register */
@@ -148,8 +151,8 @@ static int __sh_tmu_enable(struct sh_tmu_channel *ch)/* enable clock */ ret =clk_enable (ch->tmu->clk);if (ret) { -dev_err (&ch->tmu->pdev->dev,"ch%u: cannot enable clock\n" , - ch->index); +pr_err ("%s ch%u: cannot enable clock\n" , + ch->tmu->name, ch->index);return ret; }
@@ -174,9 +177,10 @@ static int sh_tmu_enable(struct sh_tmu_channel *ch)if (ch->enable_count++ >0 )return 0 ; -pm_runtime_get_sync (&ch->tmu->pdev->dev); -dev_pm_syscore_device (&ch->tmu->pdev->dev, true); - +if (ch->tmu->pdev) { +pm_runtime_get_sync (&ch->tmu->pdev->dev); +dev_pm_syscore_device (&ch->tmu->pdev->dev, true); + }return __sh_tmu_enable (ch); }
@@ -202,8 +206,10 @@ static void sh_tmu_disable(struct sh_tmu_channel *ch)__sh_tmu_disable (ch); -dev_pm_syscore_device (&ch->tmu->pdev->dev, false); -pm_runtime_put (&ch->tmu->pdev->dev); +if (ch->tmu->pdev) { +dev_pm_syscore_device (&ch->tmu->pdev->dev, false); +pm_runtime_put (&ch->tmu->pdev->dev); + } } static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
@@ -245,7 +251,7 @@ static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)return IRQ_HANDLED ; } -static struct sh_tmu_channel *cs_to_sh_tmu (struct clocksource *cs) +static inline struct sh_tmu_channel *cs_to_sh_tmu (struct clocksource *cs) { return container_of(cs, struct sh_tmu_channel, cs); }
@@ -292,7 +298,8 @@ static void sh_tmu_clocksource_suspend(struct clocksource *cs)if (--ch->enable_count ==0 ) {__sh_tmu_disable (ch); -dev_pm_genpd_suspend (&ch->tmu->pdev->dev); +if (ch->tmu->pdev) +dev_pm_genpd_suspend (&ch->tmu->pdev->dev); } }
@@ -304,7 +311,8 @@ static void sh_tmu_clocksource_resume(struct clocksource *cs)return ;if (ch->enable_count++ ==0 ) { -dev_pm_genpd_resume (&ch->tmu->pdev->dev); +if (ch->tmu->pdev) +dev_pm_genpd_resume (&ch->tmu->pdev->dev);__sh_tmu_enable (ch); } }
@@ -324,14 +332,14 @@ static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, cs->mask =CLOCKSOURCE_MASK (32 ); cs->flags =CLOCK_SOURCE_IS_CONTINUOUS ; -dev_info (&ch->tmu->pdev->dev,"ch%u: used as clock source\n" , - ch->index); +pr_info ("%s ch%u: used as clock source\n" , + ch->tmu->name, ch->index);clocksource_register_hz (cs, ch->tmu->rate);return 0 ; } -static struct sh_tmu_channel *ced_to_sh_tmu (struct clock_event_device *ced) +static inline struct sh_tmu_channel *ced_to_sh_tmu (struct clock_event_device *ced) { return container_of(ced, struct sh_tmu_channel, ced); }
@@ -364,8 +372,8 @@ static int sh_tmu_clock_event_set_state(struct clock_event_device *ced,if (clockevent_state_oneshot (ced) ||clockevent_state_periodic (ced))sh_tmu_disable (ch); -dev_info (&ch->tmu->pdev->dev,"ch%u: used for %s clock events\n" , - ch->index, periodic ?"periodic" :"oneshot" ); +pr_info ("%s ch%u: used for %s clock events\n" , + ch->tmu->name, ch->index, periodic ?"periodic" :"oneshot" );sh_tmu_clock_event_start (ch, periodic);return 0 ; }
@@ -403,7 +411,8 @@ static void sh_tmu_clock_event_resume(struct clock_event_device *ced) }static void sh_tmu_register_clockevent (struct sh_tmu_channel *ch, -const char *name) +const char *name, +struct device_node *np) {struct clock_event_device *ced = &ch->ced;int ret;
@@ -417,30 +426,32 @@ static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, ced->set_state_shutdown = sh_tmu_clock_event_shutdown; ced->set_state_periodic = sh_tmu_clock_event_set_periodic; ced->set_state_oneshot = sh_tmu_clock_event_set_oneshot; - ced->suspend = sh_tmu_clock_event_suspend; - ced->resume = sh_tmu_clock_event_resume; - -dev_info (&ch->tmu->pdev->dev,"ch%u: used for clock events\n" , - ch->index); +if (ch->tmu->pdev) { + ced->suspend = sh_tmu_clock_event_suspend; + ced->resume = sh_tmu_clock_event_resume; + } +pr_info ("%s ch%u: used for clock events\n" , + ch->tmu->name, ch->index);clockevents_config_and_register (ced, ch->tmu->rate,0x300 ,0xffffffff ); ret =request_irq (ch->irq, sh_tmu_interrupt,IRQF_TIMER |IRQF_IRQPOLL |IRQF_NOBALANCING , -dev_name (&ch->tmu->pdev->dev), ch); + ch->tmu->name, ch);if (ret) { -dev_err (&ch->tmu->pdev->dev,"ch%u: failed to request irq %d\n" , - ch->index, ch->irq); +pr_err ("%s ch%u: failed to request irq %d\n" , + ch->tmu->name, ch->index, ch->irq);return ; } }static int sh_tmu_register (struct sh_tmu_channel *ch,const char *name, +struct device_node *np,bool clockevent,bool clocksource) {if (clockevent) { ch->tmu->has_clockevent = true; -sh_tmu_register_clockevent (ch, name); +sh_tmu_register_clockevent (ch, name, np); }else if (clocksource) { ch->tmu->has_clocksource = true;sh_tmu_register_clocksource (ch, name);
@@ -451,7 +462,8 @@ static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,static int sh_tmu_channel_setup (struct sh_tmu_channel *ch,unsigned int index,bool clockevent,bool clocksource, -struct sh_tmu_device *tmu) +struct sh_tmu_device *tmu, +struct device_node *np) {/* Skip unused channels. */ if (!clockevent && !clocksource)
@@ -465,53 +477,59 @@ static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,else ch->base = tmu->mapbase +8 + ch->index *12 ; - ch->irq =platform_get_irq (tmu->pdev, index); +if (tmu->pdev) + ch->irq =platform_get_irq (tmu->pdev, index); +else + ch->irq =of_irq_get (np, index);if (ch->irq <0 )return ch->irq; ch->cs_enabled = false; ch->enable_count =0 ; -return sh_tmu_register (ch,dev_name (&tmu->pdev->dev), +return sh_tmu_register (ch, tmu->name, np, clockevent, clocksource); } -static int sh_tmu_map_memory (struct sh_tmu_device *tmu) +static int sh_tmu_map_memory (struct sh_tmu_device *tmu,struct device_node *np) {struct resource *res; - res =platform_get_resource (tmu->pdev,IORESOURCE_MEM ,0 ); -if (!res) { -dev_err (&tmu->pdev->dev,"failed to get I/O memory\n" ); -return -ENXIO ; - } +if (tmu->pdev) { + res =platform_get_resource (tmu->pdev,IORESOURCE_MEM ,0 ); +if (!res) { +pr_err ("sh_tmu failed to get I/O memory\n" ); +return -ENXIO ; + } + + tmu->mapbase =ioremap (res->start,resource_size (res)); + }else + tmu->mapbase =of_iomap (np,0 ); - tmu->mapbase =ioremap (res->start,resource_size (res));if (tmu->mapbase ==NULL )return -ENXIO ;return 0 ; } -static int sh_tmu_parse_dt (struct sh_tmu_device *tmu) +static int sh_tmu_parse_dt (struct sh_tmu_device *tmu,struct device_node *np) { -struct device_node *np = tmu->pdev->dev.of_node; - tmu->model =SH_TMU ; tmu->num_channels =3 ;of_property_read_u32 (np,"#renesas,channels" , &tmu->num_channels);if (tmu->num_channels !=2 && tmu->num_channels !=3 ) { -dev_err (&tmu->pdev->dev,"invalid number of channels %u\n" , - tmu->num_channels); +pr_err ("%s: invalid number of channels %u\n" , + tmu->name, tmu->num_channels);return -EINVAL ; }return 0 ; } -static int sh_tmu_setup (struct sh_tmu_device *tmu,struct platform_device *pdev) +static int sh_tmu_setup (struct sh_tmu_device *tmu, +struct platform_device *pdev,struct device_node *np) {unsigned int i;int ret;
@@ -520,8 +538,13 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)raw_spin_lock_init (&tmu->lock); -if (IS_ENABLED (CONFIG_OF ) && pdev->dev.of_node) { - ret =sh_tmu_parse_dt (tmu); +if (pdev) + tmu->name =dev_name (&pdev->dev); +else + tmu->name =of_node_full_name (np); + +if (IS_ENABLED (CONFIG_OF ) && np) { + ret =sh_tmu_parse_dt (tmu, np);if (ret <0 )return ret; }else if (pdev->dev.platform_data) {
@@ -531,14 +554,17 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) tmu->model = id->driver_data; tmu->num_channels =hweight8 (cfg->channels_mask); }else { -dev_err (&tmu->pdev->dev,"missing platform data\n" ); +pr_err ("%s missing platform data\n" , tmu->name);return -ENXIO ; }/* Get hold of clock. */ - tmu->clk =clk_get (&tmu->pdev->dev,"fck" ); +if (pdev) + tmu->clk =clk_get (&tmu->pdev->dev,"fck" ); +else + tmu->clk =of_clk_get (np,0 );if (IS_ERR (tmu->clk)) { -dev_err (&tmu->pdev->dev,"cannot get clock\n" ); +pr_err ("%s: cannot get clock\n" , tmu->name);return PTR_ERR (tmu->clk); }
@@ -555,9 +581,9 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)clk_disable (tmu->clk);/* Map the memory resource. */ - ret =sh_tmu_map_memory (tmu); + ret =sh_tmu_map_memory (tmu, np);if (ret <0 ) { -dev_err (&tmu->pdev->dev,"failed to remap I/O memory\n" ); +pr_err ("%s: failed to remap I/O memory\n" , tmu->name); goto err_clk_unprepare; }
@@ -575,12 +601,12 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)*/ for (i =0 ; i < tmu->num_channels; ++i) { ret =sh_tmu_channel_setup (&tmu->channels[i], i, - i ==0 , i ==1 , tmu); + i ==0 , i ==1 , tmu, np);if (ret <0 ) goto err_unmap; } - -platform_set_drvdata (pdev, tmu); +if (pdev) +platform_set_drvdata (pdev, tmu);return 0 ;
@@ -594,6 +620,7 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)return ret; } +#ifndef CONFIG_SH_DEVICE_TREE static int sh_tmu_probe (struct platform_device *pdev) {struct sh_tmu_device *tmu =platform_get_drvdata (pdev);
@@ -613,7 +640,7 @@ static int sh_tmu_probe(struct platform_device *pdev)if (tmu ==NULL )return -ENOMEM ; - ret =sh_tmu_setup (tmu, pdev); + ret =sh_tmu_setup (tmu, pdev, pdev->dev.of_node);if (ret) {kfree (tmu);pm_runtime_idle (&pdev->dev);
@@ -631,7 +658,26 @@ static int sh_tmu_probe(struct platform_device *pdev)return 0 ; } +#else +static int __init sh_tmu_of_register (struct device_node *np) +{ +struct sh_tmu_device *tmu; +int ret; + + tmu =kzalloc (sizeof (*tmu),GFP_KERNEL ); +if (tmu ==NULL ) +return -ENOMEM ; + + ret =sh_tmu_setup (tmu,NULL , np); +if (ret) { +kfree (tmu); +pr_warn ("%pOF: Timer register failed (%d)" , np, ret); + } +return ret; +} +#endif +#ifndef CONFIG_SH_DEVICE_TREE static const struct platform_device_id sh_tmu_id_table[] = { {"sh-tmu" ,SH_TMU }, { "sh-tmu-sh3", SH_TMU_SH3 },
@@ -665,12 +711,17 @@ static void __exit sh_tmu_exit(void) platform_driver_unregister(&sh_tmu_device_driver); } +subsys_initcall (sh_tmu_init); +module_exit (sh_tmu_exit); +#endif +#ifdef CONFIG_SUPERH +#ifdef CONFIG_SH_DEVICE_TREE +TIMER_OF_DECLARE (sh_tmu,"renesas,tmu" , sh_tmu_of_register); +#else sh_early_platform_init ("earlytimer" , &sh_tmu_device_driver);#endif - -subsys_initcall (sh_tmu_init); -module_exit (sh_tmu_exit); +#endif MODULE_AUTHOR ("Magnus Damm" );MODULE_DESCRIPTION ("SuperH TMU Timer Driver" );
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 08/37] clocksource: sh_tmu: CLOCKSOURCE support.
Hi Saton-san,
Thanks for your patch!
Please drop the period at the end of the one-line summary.
Quoted 1 line · Yoshinori Sato
Allows initialization as CLOCKSOURCE.
Please explain why this is needed. E.g.
Add support for early registration using TIMER_OF_DECLARE(), so the timer can be used as a clocksource on SoCs that do not have any other suitable timer.
Quoted 7 lines
Signed-off-by Yoshinori Sato <[email protected]>
drivers/clocksource/sh_tmu.c static int __sh_tmu_enable(struct sh_tmu_channel *ch) · line 155
Quoted 7 lines
drivers/clocksource/sh_tmu.c +2
-2@@ -148,8 +151,8 @@ static int __sh_tmu_enable(struct sh_tmu_channel *ch)/* enable clock */ ret =clk_enable (ch->tmu->clk);if (ret) { -dev_err (&ch->tmu->pdev->dev,"ch%u: cannot enable clock\n" , - ch->index); +pr_err ("%s ch%u: cannot enable clock\n" , + ch->tmu->name, ch->index);
Please wrap the line after, not before, "ch->tmu->name,".
drivers/clocksource/sh_tmu.c static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, · line 336
Quoted 12 lines
drivers/clocksource/sh_tmu.c +2
-2return ret; }@@ -324,14 +332,14 @@ static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, cs->mask =CLOCKSOURCE_MASK (32 ); cs->flags =CLOCK_SOURCE_IS_CONTINUOUS ; -dev_info (&ch->tmu->pdev->dev,"ch%u: used as clock source\n" , - ch->index); +pr_info ("%s ch%u: used as clock source\n" , + ch->tmu->name, ch->index);
No need to wrap this line at all.
Quoted 11 lines
drivers/clocksource/sh_tmu.c +1
-1clocksource_register_hz (cs, ch->tmu->rate);return 0 ; } -static struct sh_tmu_channel *ced_to_sh_tmu (struct clock_event_device *ced) +static inline struct sh_tmu_channel *ced_to_sh_tmu (struct clock_event_device *ced) { return container_of(ced, struct sh_tmu_channel, ced); }
drivers/clocksource/sh_tmu.c static int sh_tmu_clock_event_set_state(struct clock_event_device *ced, · line 376
Quoted 7 lines
drivers/clocksource/sh_tmu.c +2
-2@@ -364,8 +372,8 @@ static int sh_tmu_clock_event_set_state(struct clock_event_device *ced,if (clockevent_state_oneshot (ced) ||clockevent_state_periodic (ced))sh_tmu_disable (ch); -dev_info (&ch->tmu->pdev->dev,"ch%u: used for %s clock events\n" , - ch->index, periodic ?"periodic" :"oneshot" ); +pr_info ("%s ch%u: used for %s clock events\n" , + ch->tmu->name, ch->index, periodic ?"periodic" :"oneshot" );
Please wrap the line after, not before, "ch->tmu->name,".
drivers/clocksource/sh_tmu.c static void sh_tmu_clock_event_resume(struct clock_event_device *ced) · line 415
Quoted 10 lines
drivers/clocksource/sh_tmu.c +2
-1sh_tmu_clock_event_start (ch, periodic);return 0 ; }@@ -403,7 +411,8 @@ static void sh_tmu_clock_event_resume(struct clock_event_device *ced) }static void sh_tmu_register_clockevent (struct sh_tmu_channel *ch, -const char *name) +const char *name, +struct device_node *np)
"np" is unused in this function, hence this change is unneeded. (Hey, I already said that in my review of v3)
Quoted 8 lines
drivers/clocksource/sh_tmu.c +0
-1{struct clock_event_device *ced = &ch->ced;int ret;@@ -417,30 +426,32 @@ static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, ced->set_state_shutdown = sh_tmu_clock_event_shutdown; ced->set_state_periodic = sh_tmu_clock_event_set_periodic; ced->set_state_oneshot = sh_tmu_clock_event_set_oneshot; - ced->suspend = sh_tmu_clock_event_suspend;
drivers/clocksource/sh_tmu.c static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, · line 434
Quoted 10 lines
drivers/clocksource/sh_tmu.c +6
-4- ced->resume = sh_tmu_clock_event_resume; - -dev_info (&ch->tmu->pdev->dev,"ch%u: used for clock events\n" , - ch->index); +if (ch->tmu->pdev) { + ced->suspend = sh_tmu_clock_event_suspend; + ced->resume = sh_tmu_clock_event_resume; + } +pr_info ("%s ch%u: used for clock events\n" , + ch->tmu->name, ch->index);
No need to wrap this line at all.
drivers/clocksource/sh_tmu.c static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, · line 443
Quoted 12 lines
drivers/clocksource/sh_tmu.c +3
-3clockevents_config_and_register (ced, ch->tmu->rate,0x300 ,0xffffffff ); ret =request_irq (ch->irq, sh_tmu_interrupt,IRQF_TIMER |IRQF_IRQPOLL |IRQF_NOBALANCING , -dev_name (&ch->tmu->pdev->dev), ch); + ch->tmu->name, ch);if (ret) { -dev_err (&ch->tmu->pdev->dev,"ch%u: failed to request irq %d\n" , - ch->index, ch->irq); +pr_err ("%s ch%u: failed to request irq %d\n" , + ch->tmu->name, ch->index, ch->irq);
Please wrap the line after, not before, "ch->tmu->name,".
drivers/clocksource/sh_tmu.c static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, · line 449
Quoted 6 lines
drivers/clocksource/sh_tmu.c +1
-0return ; } } static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name, + struct device_node *np,
np is unneeded.
Quoted 11 lines
drivers/clocksource/sh_tmu.c +1
-1bool clockevent, bool clocksource) {if (clockevent) { ch->tmu->has_clockevent = true; -sh_tmu_register_clockevent (ch, name); +sh_tmu_register_clockevent (ch, name, np); }else if (clocksource) { ch->tmu->has_clocksource = true;sh_tmu_register_clocksource (ch, name);
drivers/clocksource/sh_tmu.c static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, · line 483
Quoted 8 lines
drivers/clocksource/sh_tmu.c +4
-1@@ -465,53 +477,59 @@ static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,else ch->base = tmu->mapbase +8 + ch->index *12 ; - ch->irq =platform_get_irq (tmu->pdev, index); +if (tmu->pdev) + ch->irq =platform_get_irq (tmu->pdev, index); +else + ch->irq =of_irq_get (np, index);
You can use of_irq_get() unconditionally.
drivers/clocksource/sh_tmu.c static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, · line 490
Quoted 8 lines
drivers/clocksource/sh_tmu.c +1
-1if (ch->irq <0 )return ch->irq; ch->cs_enabled = false; ch->enable_count =0 ; - return sh_tmu_register(ch, dev_name(&tmu->pdev->dev), + return sh_tmu_register(ch, tmu->name, np,
No need to pass np.
Quoted 13 lines
drivers/clocksource/sh_tmu.c +1
-6clockevent, clocksource); } -static int sh_tmu_map_memory (struct sh_tmu_device *tmu) +static int sh_tmu_map_memory (struct sh_tmu_device *tmu,struct device_node *np) {struct resource *res; - res =platform_get_resource (tmu->pdev,IORESOURCE_MEM ,0 ); -if (!res) { -dev_err (&tmu->pdev->dev,"failed to get I/O memory\n" ); -return -ENXIO ; - }
drivers/clocksource/sh_tmu.c static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, · line 507
Quoted 10 lines
drivers/clocksource/sh_tmu.c +10
-0+if (tmu->pdev) { + res =platform_get_resource (tmu->pdev,IORESOURCE_MEM ,0 ); +if (!res) { +pr_err ("sh_tmu failed to get I/O memory\n" ); +return -ENXIO ; + } + + tmu->mapbase =ioremap (res->start,resource_size (res)); + }else + tmu->mapbase =of_iomap (np,0 );
You can use of_iomap() unconditionally.
Quoted 13 lines
drivers/clocksource/sh_tmu.c +1
-4- tmu->mapbase =ioremap (res->start,resource_size (res));if (tmu->mapbase ==NULL )return -ENXIO ;return 0 ; } -static int sh_tmu_parse_dt (struct sh_tmu_device *tmu) +static int sh_tmu_parse_dt (struct sh_tmu_device *tmu,struct device_node *np) { -struct device_node *np = tmu->pdev->dev.of_node; -
drivers/clocksource/sh_tmu.c static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, · line 524
Quoted 10 lines
drivers/clocksource/sh_tmu.c +2
-2tmu->model =SH_TMU ; tmu->num_channels =3 ;of_property_read_u32 (np,"#renesas,channels" , &tmu->num_channels);if (tmu->num_channels !=2 && tmu->num_channels !=3 ) { -dev_err (&tmu->pdev->dev,"invalid number of channels %u\n" , - tmu->num_channels); +pr_err ("%s: invalid number of channels %u\n" , + tmu->name, tmu->num_channels);
Please wrap the line after, not before, "ch->tmu->name,".
Quoted 18 lines
drivers/clocksource/sh_tmu.c +2
-2return -EINVAL ; }return 0 ; } -static int sh_tmu_setup (struct sh_tmu_device *tmu,struct platform_device *pdev) +static int sh_tmu_setup (struct sh_tmu_device *tmu, +struct platform_device *pdev,struct device_node *np) {unsigned int i;int ret;@@ -531,14 +554,17 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) tmu->model = id->driver_data; tmu->num_channels =hweight8 (cfg->channels_mask); }else { -dev_err (&tmu->pdev->dev,"missing platform data\n" );
drivers/clocksource/sh_tmu.c static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) · line 565
Quoted 10 lines
drivers/clocksource/sh_tmu.c +5
-1+pr_err ("%s missing platform data\n" , tmu->name);return -ENXIO ; }/* Get hold of clock. */ - tmu->clk =clk_get (&tmu->pdev->dev,"fck" ); +if (pdev) + tmu->clk =clk_get (&tmu->pdev->dev,"fck" ); +else + tmu->clk =of_clk_get (np,0 );
You can use of_clk_get() unconditionally.
Quoted 8 lines
drivers/clocksource/sh_tmu.c +1
-1if (IS_ERR (tmu->clk)) { -dev_err (&tmu->pdev->dev,"cannot get clock\n" ); +pr_err ("%s: cannot get clock\n" , tmu->name);return PTR_ERR (tmu->clk); }
drivers/clocksource/sh_tmu.c static void __exit sh_tmu_exit(void) · line 720
Quoted 10 lines
drivers/clocksource/sh_tmu.c +6
-0@@ -665,12 +711,17 @@ static void __exit sh_tmu_exit(void) platform_driver_unregister(&sh_tmu_device_driver); } +subsys_initcall (sh_tmu_init); +module_exit (sh_tmu_exit); +#endif +#ifdef CONFIG_SUPERH +#ifdef CONFIG_SH_DEVICE_TREE +TIMER_OF_DECLARE (sh_tmu,"renesas,tmu" , sh_tmu_of_register);
Probably this TIMER_OF_DECLARE() should be done unconditionally, like is done in drivers/clocksource/renesas-ostm.c.
I gave that a try on R-Mobile A1, which also has TMU, but it didn't seem to work (timer not firing?). So I suspect there are some missing clk_enable() calls. In the case of the platform driver, these are handled using pm_runtime_get_sync().
drivers/clocksource/sh_tmu.c static void __exit sh_tmu_exit(void) · line 727
Quoted 10 lines
drivers/clocksource/sh_tmu.c +2
-3+#else sh_early_platform_init ("earlytimer" , &sh_tmu_device_driver);#endif - -subsys_initcall (sh_tmu_init); -module_exit (sh_tmu_exit); +#endif MODULE_AUTHOR ("Magnus Damm" );MODULE_DESCRIPTION ("SuperH TMU Timer Driver" );
Gr{oetje,eeting}s,
Geert
Signature · 5 lines
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Yoshinori Sato
maintainerPATCH v6 9/37 dt-bindings: timer: renesas,tmu: add renesas,tmu-sh7750
In reply to Yoshinori SatoAdd SH7750 TMU entry.
I wanted to replace interrupts and interrupt-names in the if compatible is "renesas,tmu-7750", but it seems that I can't rewrite it as expected. This resulted in a redundant conditional statement.
Signed-off-by Yoshinori Sato <[email protected]>
--- .../bindings/timer/renesas,tmu.yaml | 67 ++++++++++++++----- 1 file changed, 51 insertions(+), 16 deletions(-)
Documentation/devicetree/bindings/timer/renesas,tmu.yaml +51 -16
@@ -39,14 +39,15 @@ properties: - renesas,tmu-r8a779a0 # R-Car V3U - renesas,tmu-r8a779f0 # R-Car S4-8 - renesas,tmu-r8a779g0 # R-Car V4H + - renesas,tmu-sh7750 # SH7750 - const: renesas,tmu reg: maxItems: 1 - interrupts: - minItems: 2 - maxItems: 3 + interrupts: true + + interrupt-names: true clocks: maxItems: 1
@@ -75,21 +76,55 @@ required: - clock-names - power-domains -if: - not: - properties: - compatible: - contains: - enum: - - renesas,tmu-r8a7740 - - renesas,tmu-r8a7778 - - renesas,tmu-r8a7779 -then: - required: - - resets - additionalProperties: false +allOf: + - if: + not: + properties: + compatible: + contains: + enum: + - renesas,tmu-r8a7740 + - renesas,tmu-r8a7778 + - renesas,tmu-r8a7779 + - renesas,tmu-sh7750 + + then: + required: + - resets + + - if: + not: + properties: + compatible: + contains: + enum: + - renesas,tmu-sh7750 + + then: + properties: + interrupts: + minItems: 2 + maxItems: 3 + interrupt-names: + items: + - const: tuni0 + - const: tuni1 + - const: tuni2 + + else: + properties: + interrupts: + minItems: 2 + maxItems: 4 + interrupt-names: + items: + - const: tuni0 + - const: tuni1 + - const: tuni2 + - const: ticpi2 + examples: - | #include <dt-bindings/clock/r8a7779-clock.h>
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 09/37] dt-bindings: timer: renesas,tmu: add renesas,tmu-sh7750
Hi Sato-san,
Quoted 7 lines · Yoshinori Sato
Add SH7750 TMU entry.
I wanted to replace interrupts and interrupt-names in the if compatible is "renesas,tmu-7750", but it seems that I can't rewrite it as expected. This resulted in a redundant conditional statement.
Signed-off-by Yoshinori Sato <[email protected]>
Thanks for your patch!
Documentation/devicetree/bindings/timer/renesas,tmu.yaml properties: · line 42
Quoted 7 lines
Documentation/devicetree/bindings/timer/renesas,tmu.yaml +1
-0@@ -39,14 +39,15 @@ properties: - renesas,tmu-r8a779a0 # R-Car V3U - renesas,tmu-r8a779f0 # R-Car S4-8 - renesas,tmu-r8a779g0 # R-Car V4H + - renesas,tmu-sh7750 # SH7750
OK
Documentation/devicetree/bindings/timer/renesas,tmu.yaml properties: · line 50
Quoted 11 lines
Documentation/devicetree/bindings/timer/renesas,tmu.yaml +3
-3- const: renesas,tmu reg: maxItems: 1 - interrupts: - minItems: 2 - maxItems: 3 + interrupts: true + + interrupt-names: true
I would drop this change (see below).
Quoted 23 lines
Documentation/devicetree/bindings/timer/renesas,tmu.yaml +1
-13clocks: maxItems: 1@@ -75,21 +76,55 @@ required: - clock-names - power-domains -if: - not: - properties: - compatible: - contains: - enum: - - renesas,tmu-r8a7740 - - renesas,tmu-r8a7778 - - renesas,tmu-r8a7779 -then: - required: - - resets - additionalProperties: false +allOf:
Documentation/devicetree/bindings/timer/renesas,tmu.yaml required: · line 91
Quoted 10 lines
Documentation/devicetree/bindings/timer/renesas,tmu.yaml +10
-0+ - if: + not: + properties: + compatible: + contains: + enum: + - renesas,tmu-r8a7740 + - renesas,tmu-r8a7778 + - renesas,tmu-r8a7779 + - renesas,tmu-sh7750
Adding renesas,tmu-sh7750 to this list is OK.
Quoted 29 lines
Documentation/devicetree/bindings/timer/renesas,tmu.yaml +29
-0+ + then: + required: + - resets + + - if: + not: + properties: + compatible: + contains: + enum: + - renesas,tmu-sh7750 + + then: + properties: + interrupts: + minItems: 2 + maxItems: 3 + interrupt-names: + items: + - const: tuni0 + - const: tuni1 + - const: tuni2 + + else: + properties: + interrupts: + minItems: 2 + maxItems: 4
Documentation/devicetree/bindings/timer/renesas,tmu.yaml required: · line 130
Quoted 10 lines
Documentation/devicetree/bindings/timer/renesas,tmu.yaml +7
-0+ interrupt-names: + items: + - const: tuni0 + - const: tuni1 + - const: tuni2 + - const: ticpi2 + examples: - | #include <dt-bindings/clock/r8a7779-clock.h>
The new interrupt logic is not really correct: several TMU instances on other SoCs do support the fourth interrupt. It just was not documented before, or supported by the driver.
I have sent a patch to document the fourth interrupt[1]. Once that patch has been applied, adding support for sh7751 involves adding just two new lines.
[1] "PATCH] dt-bindings: timer: renesas,tmu: Document input capture
interrupt"
https://lore.kernel.org/r/fb1e38c93e62221f94304edd980a2fb79c1f2995.1705325608.git.geert+renesas@glider.beGr{oetje,eeting}s,
Geert
Signature · 5 lines
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Yoshinori Sato
maintainerPATCH v6 10/37 sh: Common PCI Framework driver support.
In reply to Yoshinori SatoAdd New OF based PCI Host driver.
This driver conflicts some point in legacy PCI driver. To resolve the conflict, I made some changes to the legacy driver.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/include/asm/io.h | 6 ++++++ arch/sh/include/asm/pci.h | 4 ++++ arch/sh/kernel/iomap.c | 18 ++++++++++++++++++ 3 files changed, 28 insertions(+)
arch/sh/include/asm/io.h +6 -0
@@ -20,6 +20,7 @@#include <asm/page.h> #include <linux/pgtable.h> #include <asm-generic/iomap.h> +#include <linux/ioport.h> #define __IO_PREFIX generic#include <asm/io_generic.h>
@@ -319,4 +320,9 @@ unsigned long long poke_real_address_q(unsigned long long addr,int valid_phys_addr_range (phys_addr_t addr,size_t size);int valid_mmap_phys_addr_range (unsigned long pfn,size_t size); +#if defined(CONFIG_PCI ) && !defined(CONFIG_GENERIC_IOMAP ) +#define pci_remap_iospace pci_remap_iospace +int pci_remap_iospace (const struct resource *res,phys_addr_t phys_addr); +#endif +#endif /* __ASM_SH_IO_H */
arch/sh/include/asm/pci.h +4 -0
@@ -2,6 +2,7 @@#ifndef __ASM_SH_PCI_H#define __ASM_SH_PCI_H +#ifndef CONFIG_SH_DEVICE_TREE /* Can be used to override the logic in pci_scan_bus for skipping already-configured bus numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the loader */
@@ -88,4 +89,7 @@ static inline int pci_proc_domain(struct pci_bus *bus)return hose->need_domain_info; } +#else /* CONFIG_SH_DEVICE_TREE */ +#include <asm-generic/pci.h> +#endif #endif /* __ASM_SH_PCI_H */
arch/sh/kernel/iomap.c +18 -0
@@ -160,3 +160,21 @@ void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)mmio_outsl (addr, src, count); }EXPORT_SYMBOL (iowrite32_rep); + +#if defined(CONFIG_PCI ) && !defined(CONFIG_GENERIC_IOMAP ) +int pci_remap_iospace (const struct resource *res,phys_addr_t phys_addr) +{ +unsigned long vaddr = res->start; + +if (!(res->flags &IORESOURCE_IO )) +return -EINVAL ; + +if (res->end >IO_SPACE_LIMIT ) +return -EINVAL ; + +__set_io_port_base (phys_addr); +return ioremap_page_range (vaddr, vaddr +resource_size (res), phys_addr, +pgprot_device (PAGE_KERNEL )); +} +EXPORT_SYMBOL (pci_remap_iospace); +#endif
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 11/37 pci: pci-sh7751: Add SH7751 PCI driver
In reply to Yoshinori SatoRenesas SH7751 CPU Internal PCI Controller driver.
Signed-off-by Yoshinori Sato <[email protected]>
--- drivers/pci/controller/Kconfig | 9 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pci-sh7751.c | 392 ++++++++++++++++++++++++++++ 3 files changed, 402 insertions(+) create mode 100644 drivers/pci/controller/pci-sh7751.c
drivers/pci/controller/Kconfig +9 -0
@@ -353,6 +353,15 @@ config PCIE_XILINX_CPM Say 'Y' here if you want kernel support for the Xilinx Versal CPM host bridge. +config PCI_SH7751 + bool "Renesas SH7751 PCI controller" + depends on OF + depends on CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST + select PCI_HOST_COMMON + help + Say 'Y' here if you want kernel to support the Renesas SH7751 PCI + Host Bridge driver. + source "drivers/pci/controller/cadence/Kconfig" source "drivers/pci/controller/dwc/Kconfig" source "drivers/pci/controller/mobiveil/Kconfig"
drivers/pci/controller/Makefile +1 -0
@@ -40,6 +40,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o +obj-$(CONFIG_PCI_SH7751) += pci-sh7751.o # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW obj-y += dwc/
drivers/pci/controller/pci-sh7751.c new file +392 -0
392 lines not on this page · raw message
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 12/37 dt-bindings: pci: pci-sh7751: Add SH7751 PCI
In reply to Yoshinori SatoRenesas SH7751 PCI Controller json-schema.
Signed-off-by Yoshinori Sato <[email protected]>
--- .../bindings/pci/renesas,sh7751-pci.yaml | 150 ++++++++++++++++++ 1 file changed, 150 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml new file +150 -0
@@ -0,0 +1,150 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/renesas,sh7751-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7751 PCI Host controller + +maintainers: + - Yoshinori Sato <[email protected]> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: renesas,sh7751-pci + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: PCI Controller + - const: Bus State Controller + + "#interrupt-cells": + const: 1 + + "#address-cells": + const: 3 + + "#size-cells": + const: 2 + + ranges: true + + dma-ranges: true + + interrupt-controller: true + + renesas,bus-arbit-round-robin: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set DMA bus arbitration to round robin. + + pci-command-reg-fast-back-to-back: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI command register Fast Back-to-Back enable bit. + + pci-command-reg-serr: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI command register SERR# enable. + + pci-command-reg-wait-cycle-control: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI command register Wait cycle control bit. + + pci-command-reg-parity-error-response: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register Parity error response bit. + + pci-command-reg-vga-snoop: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register VGA palette snoop bit. + + pci-command-reg-write-invalidate: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register Memory write and invaldate enable bit. + + pci-command-reg-special-cycle: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register Special cycle bit. + + pci-command-reg-bus-master: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register Bus master bit. + + pci-command-reg-memory-space: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register Memory space bit. + + pci-command-reg-io-space: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register I/O space bit. + + pci-bar: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: Overwrite to PCI CONFIG Base Address Registers value. + items: + items: + - description: BAR register number + - description: BAR register value + minItems: 1 + maxItems: 6 + +required: + - compatible + - reg + - "#interrupt-cells" + - "#address-cells" + - "#size-cells" + - ranges + - interrupt-map + - interrupt-map-mask + +unevaluatedProperties: false + +examples: + - | + pci@fe200000 { + compatible = "renesas,sh7751-pci"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-controller; + device_type = "pci"; + bus-range = <0 0>; + ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>, + <0x01000000 0 0x00000000 0xfe240000 0 0x00040000>; + dma-ranges = <0x02000000 0 0xc000000 0x0c000000 0 0x04000000>; + reg = <0xfe200000 0x0400>, + <0xff800000 0x0100>; + interrupt-map = <0x0000 0 0 1 &julianintc 5>, + <0x0000 0 0 2 &julianintc 6>, + <0x0000 0 0 3 &julianintc 7>, + <0x0000 0 0 4 &julianintc 8>, + <0x0800 0 0 1 &julianintc 6>, + <0x0800 0 0 2 &julianintc 7>, + <0x0800 0 0 3 &julianintc 8>, + <0x0800 0 0 4 &julianintc 5>, + <0x1000 0 0 1 &julianintc 7>, + <0x1000 0 0 2 &julianintc 8>, + <0x1000 0 0 3 &julianintc 5>, + <0x1000 0 0 4 &julianintc 6>; + pci-bar = <0 0xab000001>, <2 0xd0000000>; + pci-command-reg-io-space; + interrupt-map-mask = <0x1800 0 0 7>; + };
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 12/37] dt-bindings: pci: pci-sh7751: Add SH7751 PCI
Hi Yoshinori,
thanks for your patch!
Quoted 3 lines · Yoshinori Sato
Renesas SH7751 PCI Controller json-schema.
Signed-off-by Yoshinori Sato <[email protected]>
(...)
Quoted 44 lines
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml new file +44
-0+ renesas,bus-arbit-round-robin: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set DMA bus arbitration to round robin. + + pci-command-reg-fast-back-to-back: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI command register Fast Back-to-Back enable bit. + + pci-command-reg-serr: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI command register SERR# enable. + + pci-command-reg-wait-cycle-control: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI command register Wait cycle control bit. + + pci-command-reg-parity-error-response: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register Parity error response bit. + + pci-command-reg-vga-snoop: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register VGA palette snoop bit. + + pci-command-reg-write-invalidate: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register Memory write and invaldate enable bit. + + pci-command-reg-special-cycle: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register Special cycle bit. + + pci-command-reg-bus-master: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register Bus master bit.
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml line 96
Quoted 10 lines
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml new file +10
-0+ + pci-command-reg-memory-space: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register Memory space bit. + + pci-command-reg-io-space: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register I/O space bit.
Do you really need to configure all these things? It seems they are just set to default values anyway?
Can't you just look at the compatible "renesas,sh7751-pci" and set it to the values you know are needed for that compatible?
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml line 106
Quoted 9 lines
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml new file +9
-0+ pci-bar: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: Overwrite to PCI CONFIG Base Address Registers value. + items: + items: + - description: BAR register number + - description: BAR register value + minItems: 1 + maxItems: 6
Same with this, isn't this always the same (hardcoded) values for "renesas,sh7751-pci" if used?
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml line 146
Quoted 12 lines
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml new file +12
-0+ interrupt-map = <0x0000 0 0 1 &julianintc 5>, + <0x0000 0 0 2 &julianintc 6>, + <0x0000 0 0 3 &julianintc 7>, + <0x0000 0 0 4 &julianintc 8>, + <0x0800 0 0 1 &julianintc 6>, + <0x0800 0 0 2 &julianintc 7>, + <0x0800 0 0 3 &julianintc 8>, + <0x0800 0 0 4 &julianintc 5>, + <0x1000 0 0 1 &julianintc 7>, + <0x1000 0 0 2 &julianintc 8>, + <0x1000 0 0 3 &julianintc 5>, + <0x1000 0 0 4 &julianintc 6>;
This interrupt-map looks very strange, usually the last cell is the polarity flag and here it is omitted? I would expect something like:
<0x0000 0 0 1 &julianintc 5 IRQ_TYPE_LEVEL_LOW>, (...)
The interrupt-map schema in dtschema isn't really looking at this so it is easy to get it wrong.
Yours,
Linus Walleij
Rob Herring
maintainerRe: [DO NOT MERGE v6 12/37] dt-bindings: pci: pci-sh7751: Add SH7751 PCI
Quoted 69 lines · Linus Walleij
Hi Yoshinori,
thanks for your patch!
Quoted 3 lines · Yoshinori Sato
Renesas SH7751 PCI Controller json-schema.
Signed-off-by Yoshinori Sato <[email protected]>(...)
Quoted 44 lines
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml new file +44
-0+ renesas,bus-arbit-round-robin: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set DMA bus arbitration to round robin. + + pci-command-reg-fast-back-to-back: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI command register Fast Back-to-Back enable bit. + + pci-command-reg-serr: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI command register SERR# enable. + + pci-command-reg-wait-cycle-control: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI command register Wait cycle control bit. + + pci-command-reg-parity-error-response: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register Parity error response bit. + + pci-command-reg-vga-snoop: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register VGA palette snoop bit. + + pci-command-reg-write-invalidate: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register Memory write and invaldate enable bit. + + pci-command-reg-special-cycle: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register Special cycle bit. + + pci-command-reg-bus-master: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register Bus master bit.Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml line 96
Quoted 10 lines
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml new file +10
-0+ + pci-command-reg-memory-space: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register Memory space bit. + + pci-command-reg-io-space: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Set for PCI Command register I/O space bit.Do you really need to configure all these things? It seems they are just set to default values anyway?
Quoted 2 lines
Can't you just look at the compatible "renesas,sh7751-pci" and set it to the values you know are needed for that compatible?
Yes. Please drop all these.
Quoted 11 lines
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml line 106
Quoted 10 lines
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml new file +9
-0+ pci-bar: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: Overwrite to PCI CONFIG Base Address Registers value. + items: + items: + - description: BAR register number + - description: BAR register value + minItems: 1 + maxItems: 6
Quoted 2 lines
Same with this, isn't this always the same (hardcoded) values for "renesas,sh7751-pci" if used?
The OpenFirmware PCI bus supplement already defines how to specify BAR values in DT in "reg" or "assigned-addresses". If you need to specify these, use that. Note don't expect the kernel to do anything with them.
Rob
Quoted 14 lines
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml line 146
Quoted 13 lines
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml new file +12
-0+ interrupt-map = <0x0000 0 0 1 &julianintc 5>, + <0x0000 0 0 2 &julianintc 6>, + <0x0000 0 0 3 &julianintc 7>, + <0x0000 0 0 4 &julianintc 8>, + <0x0800 0 0 1 &julianintc 6>, + <0x0800 0 0 2 &julianintc 7>, + <0x0800 0 0 3 &julianintc 8>, + <0x0800 0 0 4 &julianintc 5>, + <0x1000 0 0 1 &julianintc 7>, + <0x1000 0 0 2 &julianintc 8>, + <0x1000 0 0 3 &julianintc 5>, + <0x1000 0 0 4 &julianintc 6>;
Quoted 7 lines
This interrupt-map looks very strange, usually the last cell is the polarity flag and here it is omitted? I would expect something like:
<
0x00000 0 1 &julianintc 5IRQ_TYPE_LEVEL_LOW>, (...)The interrupt-map schema in dtschema isn't really looking at this so it is easy to get it wrong.
dtc should IIRC. Maybe not in the example being incomplete.
Rob
Yoshinori Sato
maintainerPATCH v6 13/37 dt-bindings: clock: sh7750-cpg: Add renesas,sh7750-cpg header.
In reply to Yoshinori SatoSH7750 CPG Clock output define.
Signed-off-by Yoshinori Sato <[email protected]>
--- .../bindings/clock/renesas,sh7750-cpg.yaml | 103 ++++++++++++++++++ include/dt-bindings/clock/sh7750-cpg.h | 26 +++++ 2 files changed, 129 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml create mode 100644 include/dt-bindings/clock/sh7750-cpg.h
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml new file +103 -0
@@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7750/7751 Clock Pulse Generator (CPG) + +maintainers: + - Yoshinori Sato <[email protected]> + +description: + The Clock Pulse Generator (CPG) generates core clocks for the SoC. It + includes PLLs, and variable ratio dividers. + + The CPG may also provide a Clock Domain for SoC devices, in combination with + the CPG Module Stop (MSTP) Clocks. + +properties: + compatible: + enum: + - renesas,sh7750-cpg # SH7750 + - renesas,sh7750s-cpg # SH775S + - renesas,sh7750r-cpg # SH7750R + - renesas,sh7751-cpg # SH7751 + - renesas,sh7751r-cpg # SH7751R + + reg: true + + reg-names: true + + clocks: true + + clock-names: true + + '#clock-cells': + const: 1 + + renesas,mode: + description: Board-specific settings of the MD[0-2] pins on SoC + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 6 + + '#power-domain-cells': + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - '#clock-cells' + +allOf: + - if: + properties: + compatible: + contains: + enum: + - renesas,sh7750-cpg + - renesas,sh7750s-cpg + then: + properties: + reg: + maxItems: 1 + reg-names: + items: + - const: FRQCR + + - if: + properties: + compatible: + contains: + enum: + - renesas,sh7750r-cpg + - renesas,sh7751-cpg + - renesas,sh7751r-cpg + then: + properties: + reg: + maxItems: 2 + reg-names: + items: + - const: FRQCR + - const: CLKSTP00 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sh7750-cpg.h> + cpg: clock-controller@ffc00000 { + #clock-cells = <1>; + #power-domain-cells = <0>; + compatible = "renesas,sh7751r-cpg"; + clocks = <&xtal>; + clock-names = "xtal"; + reg = <0xffc00000 20>, <0xfe0a0000 16>; + reg-names = "FRQCR", "CLKSTP00"; + renesas,mode = <0>; + };
include/dt-bindings/clock/sh7750-cpg.h new file +26 -0
@@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +* +* Copyright 2023 Yoshinori Sato +*/ + +#ifndef __DT_BINDINGS_CLOCK_SH7750_H__ +#define __DT_BINDINGS_CLOCK_SH7750_H__ + +#define SH7750_CPG_PLLOUT 0 + +#define SH7750_CPG_FCK 1 +#define SH7750_CPG_BCK 2 +#define SH7750_CPG_ICK 3 + +#define SH7750_MSTP_SCI 4 +#define SH7750_MSTP_RTC 5 +#define SH7750_MSTP_TMU012 6 +#define SH7750_MSTP_SCIF 7 +#define SH7750_MSTP_DMAC 8 +#define SH7750_MSTP_UBC 9 +#define SH7750_MSTP_SQ 10 +#define SH7750_CSTP_INTC 11 +#define SH7750_CSTP_TMU34 12 +#define SH7750_CSTP_PCIC 13 + +#endif
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 13/37] dt-bindings: clock: sh7750-cpg: Add renesas,sh7750-cpg header.
Hi Sato-san,
Thanks for your patch!
Quoted 1 line · Yoshinori Sato
SH7750 CPG Clock output define.
Please improve the patch description.
Quoted 27 lines
Signed-off-by Yoshinori Sato <[email protected]>Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml new file +22
-0@@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7750/7751 Clock Pulse Generator (CPG) + +maintainers: + - Yoshinori Sato <[email protected]> + +description: + The Clock Pulse Generator (CPG) generates core clocks for the SoC. It + includes PLLs, and variable ratio dividers. + + The CPG may also provide a Clock Domain for SoC devices, in combination with + the CPG Module Stop (MSTP) Clocks. + +properties: + compatible: + enum: + - renesas,sh7750-cpg # SH7750
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml line 32
Quoted 10 lines
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml new file +10
-0+ - renesas,sh7750s-cpg # SH775S + - renesas,sh7750r-cpg # SH7750R + - renesas,sh7751-cpg # SH7751 + - renesas,sh7751r-cpg # SH7751R + + reg: true + + reg-names: true + + clocks: true
clocks:
maxItems: 1
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml line 34
Quoted 2 lines
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml new file +2
-0+ + clock-names: true
clock-names:
const: extal
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml line 99
Quoted 9 lines
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml new file +9
-0+examples: + - | + #include <dt-bindings/clock/sh7750-cpg.h> + cpg: clock-controller@ffc00000 { + #clock-cells = <1>; + #power-domain-cells = <0>; + compatible = "renesas,sh7751r-cpg"; + clocks = <&xtal>; + clock-names = "xtal";
"extal"
"xtal" is an output pin, connected to a crystal resonator. "extal" is the clock input put (either crystal resonator or exteral clock input.
Quoted 11 lines
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml new file +4
-0+ reg = <0xffc00000 20>, <0xfe0a0000 16>; + reg-names = "FRQCR", "CLKSTP00"; + renesas,mode = <0>; + };include/dt-bindings/clock/sh7750-cpg.h new file +1
-0@@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
include/dt-bindings/clock/sh7750-cpg.h line 11
Quoted 10 lines
include/dt-bindings/clock/sh7750-cpg.h new file +10
-0+* +* Copyright 2023 Yoshinori Sato +*/ + +#ifndef __DT_BINDINGS_CLOCK_SH7750_H__ +#define __DT_BINDINGS_CLOCK_SH7750_H__ + +#define SH7750_CPG_PLLOUT 0 + +#define SH7750_CPG_FCK 1
PCK?
include/dt-bindings/clock/sh7750-cpg.h line 13
Quoted 2 lines
include/dt-bindings/clock/sh7750-cpg.h new file +2
-0+#define SH7750_CPG_BCK 2 +#define SH7750_CPG_ICK 3
Gr{oetje,eeting}s,
Geert
Signature · 5 lines
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Yoshinori Sato
maintainerPATCH v6 14/37 clk: Compatible with narrow registers
In reply to Yoshinori Satodivider and gate only support 32-bit registers.
Older hardware uses narrower registers, so I want to be able to handle 8-bit and 16-bit wide registers.
Seven clk_divider flags are used, and if I add flags for 8bit access and 16bit access, 8bit will not be enough, so I expanded it to u16.
Signed-off-by Yoshinori Sato <[email protected]>
--- drivers/clk/clk-divider.c | 56 ++++++++++++++++++++++++------------ drivers/clk/clk-gate.c | 56 +++++++++++++++++++++++++++--------- include/linux/clk-provider.h | 22 ++++++++++---- 3 files changed, 97 insertions(+), 37 deletions(-)
drivers/clk/clk-divider.c +37 -19
@@ -26,20 +26,38 @@* parent - fixed parent. No clk_set_parent support */ -static inline u32 clk_div_readl (struct clk_divider *divider) -{ -if (divider->flags &CLK_DIVIDER_BIG_ENDIAN ) -return ioread32be (divider->reg); - -return readl (divider->reg); +static inline u32 clk_div_read (struct clk_divider *divider) +{ +if (divider->flags &CLK_DIVIDER_REG_8BIT ) +return readb (divider->reg); +else if (divider->flags &CLK_DIVIDER_REG_16BIT ) { +if (divider->flags &CLK_DIVIDER_BIG_ENDIAN ) +return ioread16be (divider->reg); +else +return readw (divider->reg); + }else { +if (divider->flags &CLK_DIVIDER_BIG_ENDIAN ) +return ioread32be (divider->reg); +else +return readl (divider->reg); + } } -static inline void clk_div_writel (struct clk_divider *divider,u32 val) +static inline void clk_div_write (struct clk_divider *divider,u32 val) { -if (divider->flags &CLK_DIVIDER_BIG_ENDIAN ) -iowrite32be (val, divider->reg); -else -writel (val, divider->reg); +if (divider->flags &CLK_DIVIDER_REG_8BIT ) +writeb (val, divider->reg); +else if (divider->flags &CLK_DIVIDER_REG_16BIT ) { +if (divider->flags &CLK_DIVIDER_BIG_ENDIAN ) +iowrite16be (val, divider->reg); +else +writew (val, divider->reg); + }else { +if (divider->flags &CLK_DIVIDER_BIG_ENDIAN ) +iowrite32be (val, divider->reg); +else +writel (val, divider->reg); + } } static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
@@ -152,7 +170,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,struct clk_divider *divider =to_clk_divider (hw);unsigned int val; - val =clk_div_readl (divider) >> divider->shift; + val =clk_div_read (divider) >> divider->shift; val &=clk_div_mask (divider->width); return divider_recalc_rate(hw, parent_rate, val, divider->table,
@@ -434,7 +452,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,if (divider->flags &CLK_DIVIDER_READ_ONLY ) {u32 val; - val =clk_div_readl (divider) >> divider->shift; + val =clk_div_read (divider) >> divider->shift; val &=clk_div_mask (divider->width); return divider_ro_round_rate(hw, rate, prate, divider->table,
@@ -455,7 +473,7 @@ static int clk_divider_determine_rate(struct clk_hw *hw,if (divider->flags &CLK_DIVIDER_READ_ONLY ) {u32 val; - val =clk_div_readl (divider) >> divider->shift; + val =clk_div_read (divider) >> divider->shift; val &=clk_div_mask (divider->width); return divider_ro_determine_rate(hw, req, divider->table,
@@ -505,11 +523,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,if (divider->flags &CLK_DIVIDER_HIWORD_MASK ) { val =clk_div_mask (divider->width) << (divider->shift +16 ); }else { - val =clk_div_readl (divider); + val =clk_div_read (divider); val &= ~(clk_div_mask (divider->width) << divider->shift); } val |= (u32 )value << divider->shift; -clk_div_writel (divider, val); +clk_div_write (divider, val);if (divider->lock)spin_unlock_irqrestore (divider->lock, flags);
@@ -538,7 +556,7 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, + void __iomem *reg, u8 shift, u8 width, u32 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock) { struct clk_divider *div;
@@ -610,7 +628,7 @@ EXPORT_SYMBOL_GPL(__clk_hw_register_divider);struct clk *clk_register_divider_table (struct device *dev,const char *name,const char *parent_name,unsigned long flags,void __iomem *reg,u8 shift,u8 width, -u8 clk_divider_flags,const struct clk_div_table *table, +u32 clk_divider_flags,const struct clk_div_table *table,spinlock_t *lock) {struct clk_hw *hw;
@@ -664,7 +682,7 @@ struct clk_hw *__devm_clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, + void __iomem *reg, u8 shift, u8 width, u32 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock) { struct clk_hw **ptr, *hw;
drivers/clk/clk-gate.c +43 -13
90 lines not on this page · raw message
include/linux/clk-provider.h +17 -5
@@ -508,12 +508,16 @@ void of_fixed_clk_setup(struct device_node *np);* CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for * the gate register. Setting this flag makes the register accesses big * endian. +* CLK_GATE_REG_8BIT - by default 32bit register accesses are used for +* the gate register. Setting this flag makes the register accesses 8bit. +* CLK_GATE_REG_16BIT - by default 32bit register accesses are used for +* the gate register. Setting this flag makes the register accesses 16bit. */ struct clk_gate {struct clk_hw hw;void __iomem *reg;u8 bit_idx; -u8 flags; +u32 flags;spinlock_t *lock; };
@@ -522,6 +526,8 @@ struct clk_gate {#define CLK_GATE_SET_TO_DISABLE BIT(0)#define CLK_GATE_HIWORD_MASK BIT(1)#define CLK_GATE_BIG_ENDIAN BIT(2) +#define CLK_GATE_REG_8BIT BIT(3) +#define CLK_GATE_REG_16BIT BIT(4)extern const struct clk_ops clk_gate_ops; struct clk_hw *__clk_hw_register_gate(struct device *dev,
@@ -675,13 +681,17 @@ struct clk_div_table {* CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used * for the divider register. Setting this flag makes the register accesses * big endian. +* CLK_DIVIDER_REG_8BIT - by default 32bit register accesses are used for +* the gate register. Setting this flag makes the register accesses 8bit. +* CLK_DIVIDER_REG_16BIT - by default 32bit register accesses are used for +* the gate register. Setting this flag makes the register accesses 16bit. */ struct clk_divider {struct clk_hw hw;void __iomem *reg;u8 shift;u8 width; -u8 flags; +u16 flags;const struct clk_div_table *table;spinlock_t *lock; };
@@ -697,6 +707,8 @@ struct clk_divider {#define CLK_DIVIDER_READ_ONLY BIT(5)#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)#define CLK_DIVIDER_BIG_ENDIAN BIT(7) +#define CLK_DIVIDER_REG_8BIT BIT(8) +#define CLK_DIVIDER_REG_16BIT BIT(9)extern const struct clk_ops clk_divider_ops;extern const struct clk_ops clk_divider_ro_ops;
@@ -726,18 +738,18 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, + void __iomem *reg, u8 shift, u8 width, u32 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock);struct clk_hw *__devm_clk_hw_register_divider (struct device *dev,struct device_node *np,const char *name,const char *parent_name,const struct clk_hw *parent_hw,const struct clk_parent_data *parent_data,unsigned long flags, -void __iomem *reg,u8 shift,u8 width,u8 clk_divider_flags, +void __iomem *reg,u8 shift,u8 width,u32 clk_divider_flags,const struct clk_div_table *table,spinlock_t *lock);struct clk *clk_register_divider_table (struct device *dev,const char *name,const char *parent_name,unsigned long flags,void __iomem *reg,u8 shift,u8 width, -u8 clk_divider_flags,const struct clk_div_table *table, +u32 clk_divider_flags,const struct clk_div_table *table,spinlock_t *lock);/** * clk_register_divider - register a divider clock with the clock framework
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 14/37] clk: Compatible with narrow registers
Hi Sato-san,
Quoted 8 lines · Yoshinori Sato
divider and gate only support 32-bit registers.
Older hardware uses narrower registers, so I want to be able to handle 8-bit and 16-bit wide registers.Seven
clk_dividerflags are used, and if I add flags for 8bit access and 16bit access, 8bit will not be enough, so I expanded it to u16.Signed-off-by Yoshinori Sato <[email protected]>
Thanks for your patch!
drivers/clk/clk-gate.c struct clk_hw *__clk_hw_register_gate(struct device *dev, · line 162
Quoted 5 lines
drivers/clk/clk-gate.c +0
-0@@ -143,6 +161,18 @@ struct clk_hw *__clk_hw_register_gate(struct device *dev,return ERR_PTR (-EINVAL ); }
Please add a check for invalid CLK_GATE_HIWORD_MASK and register width combinations:
if (clk_gate_flags & (CLK_GATE_REG_16BIT | CLK_GATE_REG_8BIT)) {
pr_err("HIWORD_MASK needs 32-bit registers\n");
return ERR_PTR(-EINVAL);
}Quoted 25 lines
drivers/clk/clk-gate.c +12
-0} +if (clk_gate_flags &CLK_GATE_REG_16BIT ) { +if (bit_idx >15 ) { +pr_err ("gate bit exceeds 16 bits\n" ); +return ERR_PTR (-EINVAL ); + } + } +if (clk_gate_flags &CLK_GATE_REG_8BIT ) { +if (bit_idx >7 ) { +pr_err ("gate bit exceeds 8 bits\n" ); +return ERR_PTR (-EINVAL ); + } + }/* allocate the gate */ gate =kzalloc (sizeof (*gate),GFP_KERNEL );include/linux/clk-provider.h +1
-0@@ -508,12 +508,16 @@ void of_fixed_clk_setup(struct device_node *np);* CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for * the gate register. Setting this flag makes the register accesses big * endian. +* CLK_GATE_REG_8BIT - by default 32bit register accesses are used for
include/linux/clk-provider.h void of_fixed_clk_setup(struct device_node *np); · line 520
Quoted 10 lines
include/linux/clk-provider.h +4
-1+* the gate register. Setting this flag makes the register accesses 8bit. +* CLK_GATE_REG_16BIT - by default 32bit register accesses are used for +* the gate register. Setting this flag makes the register accesses 16bit. */ struct clk_gate {struct clk_hw hw;void __iomem *reg;u8 bit_idx; -u8 flags; +u32 flags;
There is no need to increase the size of the flags field for the gate clock.
include/linux/clk-provider.h struct clk_gate { · line 533
Quoted 12 lines
include/linux/clk-provider.h +2
-0spinlock_t *lock; };@@ -522,6 +526,8 @@ struct clk_gate {#define CLK_GATE_SET_TO_DISABLE BIT(0)#define CLK_GATE_HIWORD_MASK BIT(1)#define CLK_GATE_BIG_ENDIAN BIT(2) +#define CLK_GATE_REG_8BIT BIT(3) +#define CLK_GATE_REG_16BIT BIT(4)extern const struct clk_ops clk_gate_ops; struct clk_hw *__clk_hw_register_gate(struct device *dev,
The rest LGTM.
Gr{oetje,eeting}s,
Geert
Signature · 5 lines
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Yoshinori Sato
maintainerPATCH v6 15/37 clk: renesas: Add SH7750/7751 CPG Driver
In reply to Yoshinori SatoRenesas SH7750 and SH7751 series CPG driver. This driver supported frequency control and clock gating.
Signed-off-by Yoshinori Sato <[email protected]>
--- drivers/clk/renesas/Kconfig | 16 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-sh7750.c | 498 +++++++++++++++++++++++++++++++ 3 files changed, 513 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/renesas/clk-sh7750.c
drivers/clk/renesas/Kconfig +14 -2
@@ -1,8 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 config CLK_RENESAS - bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS - default y if ARCH_RENESAS + bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS && !SUPERH + default y if ARCH_RENESAS || SUPERH select CLK_EMEV2 if ARCH_EMEV2 select CLK_RZA1 if ARCH_R7S72100 select CLK_R7S9210 if ARCH_R7S9210
@@ -40,6 +40,9 @@ config CLK_RENESAS select CLK_R9A08G045 if ARCH_R9A08G045 select CLK_R9A09G011 if ARCH_R9A09G011 select CLK_SH73A0 if ARCH_SH73A0 + select CLK_SH7750 if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \ + CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751 || \ + CPU_SUBTYPE_SH7751R if CLK_RENESAS
@@ -193,6 +196,10 @@ config CLK_SH73A0 select CLK_RENESAS_CPG_MSTP select CLK_RENESAS_DIV6 +config CLK_SH7750 + bool "SH7750/7751 family clock support" if COMPILE_TEST + help + This is a driver for SH7750 / SH7751 CPG. # Family config CLK_RCAR_CPG_LIB
@@ -223,6 +230,11 @@ config CLK_RZG2L bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER +config CLK_SH7750 + bool "Renesas SH7750/7751 family clock support" if COMPILE_TEST + help + This is a driver for SH7750 / SH7751 CPG. + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TEST
drivers/clk/renesas/Makefile +1 -0
@@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o +obj-$(CONFIG_CLK_SH7750) += clk-sh7750.o # Family obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
drivers/clk/renesas/clk-sh7750.c new file +498 -0
498 lines not on this page · raw message
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 15/37] clk: renesas: Add SH7750/7751 CPG Driver
Hi Sato-san,
Quoted 4 lines · Yoshinori Sato
Renesas SH7750 and SH7751 series CPG driver. This driver supported frequency control and clock gating.
Signed-off-by Yoshinori Sato <[email protected]>
Thanks for your patch!
drivers/clk/renesas/Kconfig config CLK_SH73A0 · line 202
Quoted 10 lines
drivers/clk/renesas/Kconfig +4
-0@@ -193,6 +196,10 @@ config CLK_SH73A0 select CLK_RENESAS_CPG_MSTP select CLK_RENESAS_DIV6 +config CLK_SH7750 + bool "SH7750/7751 family clock support" if COMPILE_TEST + help + This is a driver for SH7750 / SH7751 CPG.
This is a duplicate of the below. Please drop it.
Quoted 34 lines
drivers/clk/renesas/Kconfig +5
-0# Family config CLK_RCAR_CPG_LIB@@ -223,6 +230,11 @@ config CLK_RZG2L bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER +config CLK_SH7750 + bool "Renesas SH7750/7751 family clock support" if COMPILE_TEST + help + This is a driver for SH7750 / SH7751 CPG. + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TESTdrivers/clk/renesas/clk-sh7750.c new file +15
-0+static int register_pll (struct device_node *node,struct cpg_priv *cpg) +{ +const char *clk_name = node->name; +const char *parent_name; +struct clk_init_data init = { + .name =PLLOUT , + .ops = &pll_ops, + .flags =0 , + .num_parents =1 , + }; +int ret; + + parent_name =of_clk_get_parent_name (node,0 ); + init.parent_names = &parent_name; + cpg->hw.init = &init;
drivers/clk/renesas/clk-sh7750.c line 196
Quoted 10 lines
drivers/clk/renesas/clk-sh7750.c new file +10
-0+ + ret =of_clk_hw_register (node, &cpg->hw); +if (ret <0 ) { +pr_err ("%s: failed to register %s pll clock (%d)\n" , + __func__, clk_name, ret); +return ret; + } +if (ret <0 ) +pr_err ("%s: failed to add provider %s (%d)\n" , + __func__, clk_name, ret);
Bogus check and error message.
Quoted 36 lines
drivers/clk/renesas/clk-sh7750.c new file +35
-0+return ret; +} +static int register_div (struct device_node *node,struct cpg_priv *cpg) +{ +static const char *const divout[] = { +"fck" ,"bck" ,"ick" , + }; +static const char *const stbcrout[] = { +"sci_clk" ,"rtc_clk" ,"tmu012_clk" ,/* STBCR */ +"scif_clk" ,"dmac_clk" ,/* STBCR */ +"ubc_clk" ,"sq_clk" ,/* STBCR2 */ + }; +static const char *const clkstpout[] = { +"intc_clk" ,"tmu34_clk" ,"pcic_clk" ,/* CLKSTP00 */ + }; + +unsigned int i; +int ret; +struct clk_hw_onecell_data *data; +struct clk_hw *reg_hw; +int num_clk =ARRAY_SIZE (divout) +ARRAY_SIZE (stbcrout) +ARRAY_SIZE (clkstpout); + + data =kzalloc (struct_size (data, hws, num_clk +1 ),GFP_KERNEL ); +if (!data) +return -ENOMEM ; + + num_clk =0 ; +for (i =0 ; i <ARRAY_SIZE (divout); i++) { + reg_hw =__clk_hw_register_divider (NULL , node, divout[i], +PLLOUT ,NULL ,NULL , +0 , cpg->frqcr, i *3 ,3 , +CLK_DIVIDER_REG_16BIT , + (i ==0 ) ? pdiv_table : div_table, + &cpg->clklock); +if (IS_ERR (reg_hw)) {
drivers/clk/renesas/clk-sh7750.c line 316
Quoted 10 lines
drivers/clk/renesas/clk-sh7750.c new file +10
-0+ ret =PTR_ERR (reg_hw); + goto error; + } + data->hws[num_clk++] = reg_hw; + } +for (i =0 ; i <ARRAY_SIZE (stbcrout); i++) { +u32 off = (i <5 ) ?STBCR :STBCR2 ; + +if (i >=5 && !(cpg->feat &MSTP_CR2 )) +break ;
Alternatively, you could set the maximum loop counter upfront
n = cpg->feat & MSTP_CR2 ? ARRAY_SIZE(stbcrout) : 5;
for (i = 0; i < n; i++) ...Quoted 5 lines
drivers/clk/renesas/clk-sh7750.c new file +5
-0+ reg_hw =__clk_hw_register_gate (NULL , node, stbcrout[i], + divout[0 ],NULL ,NULL , +0 , cpg->frqcr + off, i %5 , +CLK_GATE_REG_8BIT |CLK_GATE_SET_TO_DISABLE , + &cpg->clklock);
drivers/clk/renesas/clk-sh7750.c line 331
Quoted 10 lines
drivers/clk/renesas/clk-sh7750.c new file +10
-0+if (IS_ERR (reg_hw)) { + ret =PTR_ERR (reg_hw); + goto error; + } + data->hws[num_clk++] = reg_hw; + } +if (cpg->feat &MSTP_CLKSTP ) { +for (i =0 ; i <ARRAY_SIZE (clkstpout); i++) { +if (i ==2 && !(cpg->feat &MSTP_CSTP2 )) +continue ;
Set maximum loop counter upfront?
Quoted 27 lines
drivers/clk/renesas/clk-sh7750.c new file +27
-0+ reg_hw =clk_hw_register_clkstp (node, clkstpout[i], + divout[0 ], cpg->clkstp00, + i, &cpg->clklock); +if (IS_ERR (reg_hw)) { + ret =PTR_ERR (reg_hw); + goto error; + } + data->hws[num_clk++] = reg_hw; + } + } + data->num = num_clk; + ret =of_clk_add_hw_provider (node, of_clk_hw_onecell_get, data); +if (ret <0 ) + goto error; +return 0 ; + +error: +pr_err ("%pOF: failed to register clock (%d)\n" , + node, ret); +for (num_clk--; num_clk >=0 ; num_clk--) +kfree (data->hws[num_clk]); +kfree (data); +return ret; +} + +static struct cpg_priv *sh7750_cpg_setup (struct device_node *node,u32 feat) +{
drivers/clk/renesas/clk-sh7750.c line 368
Quoted 10 lines
drivers/clk/renesas/clk-sh7750.c new file +10
-0+unsigned int num_parents; +u32 mode; +struct cpg_priv *cpg; +int ret =0 ; + + num_parents =of_clk_get_parent_count (node); +if (num_parents <1 ) { +pr_err ("%s: no parent found" , node->name); +return ERR_PTR (-ENODEV ); + }
Do you need num_parents?
drivers/clk/renesas/clk-sh7750.c line 370
Quoted 2 lines
drivers/clk/renesas/clk-sh7750.c new file +2
-0+ +of_property_read_u32_index (node,"renesas,mode" ,0 , &mode);
mode may be used uninitialized, if "renesas,mode" is missing.
Quoted 26 lines
drivers/clk/renesas/clk-sh7750.c new file +26
-0+if (mode >=7 ) { +pr_err ("%s: Invalid clock mode setting (%u)\n" , + node->name, mode); +return ERR_PTR (-EINVAL ); + } + + cpg =kzalloc (sizeof (struct cpg_priv ),GFP_KERNEL ); +if (!cpg) +return ERR_PTR (-ENOMEM ); + + cpg->frqcr =of_iomap (node,0 ); +if (cpg->frqcr ==NULL ) { +pr_err ("%pOF: failed to map divide register" , node); + ret = -ENODEV ; + goto cpg_free; + } + +if (feat &MSTP_CLKSTP ) { + cpg->clkstp00 =of_iomap (node,1 ); +if (cpg->clkstp00 ==NULL ) { +pr_err ("%pOF: failed to map clkstp00 register" , node); + ret = -ENODEV ; + goto unmap_frqcr; + } + } + cpg->feat = feat;
drivers/clk/renesas/clk-sh7750.c line 406
Quoted 10 lines
drivers/clk/renesas/clk-sh7750.c new file +10
-0+ cpg->mode = mode; + + ret =register_pll (node, cpg); +if (ret <0 ) + goto unmap_clkstp00; + + ret =register_div (node, cpg); +if (ret <0 ) + goto unmap_clkstp00; +
Perhaps "cpg_data = cpg;" here, and return an error code instead? ...
Quoted 6 lines
drivers/clk/renesas/clk-sh7750.c new file +6
-0+return cpg; + +unmap_clkstp00: +iounmap (cpg->clkstp00); +unmap_frqcr: +iounmap (cpg->frqcr);
drivers/clk/renesas/clk-sh7750.c line 422
Quoted 10 lines
drivers/clk/renesas/clk-sh7750.c new file +10
-0+cpg_free: +kfree (cpg); +return ERR_PTR (ret); +} + +static void __init sh7750_cpg_init (struct device_node *node) +{ + cpg_data =sh7750_cpg_setup (node, cpg_feature[CPG_SH7750 ]); +if (IS_ERR (cpg_data)) + cpg_data =NULL ;
... then all cpg_data handling can be removed here...
drivers/clk/renesas/clk-sh7750.c line 474
Quoted 13 lines
drivers/clk/renesas/clk-sh7750.c new file +12
-0+} +static int sh7750_cpg_probe (struct platform_device *pdev) +{ +u32 feature; + +if (cpg_data) +return 0 ; + feature = *(u32 *)of_device_get_match_data (&pdev->dev); + cpg_data =sh7750_cpg_setup (pdev->dev.of_node, feature); +if (IS_ERR (cpg_data)) +return PTR_ERR (cpg_data); +return 0 ;
... and this can be simplified to
return sh7750_cpg_setup(...);
Quoted 1 line
+}
Gr{oetje,eeting}s,
Geert
Signature · 5 lines
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Yoshinori Sato
maintainerPATCH v6 16/37 irqchip: Add SH7751 INTC driver
In reply to Yoshinori SatoRenesas SH7751 Internal interrupt controller driver.
Signed-off-by Yoshinori Sato <[email protected]>
--- drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-renesas-sh7751.c | 313 +++++++++++++++++++++++++++ 3 files changed, 322 insertions(+) create mode 100644 drivers/irqchip/irq-renesas-sh7751.c
drivers/irqchip/Kconfig +8 -0
@@ -679,4 +679,12 @@ config SUNPLUS_SP7021_INTC chained controller, routing all interrupt source in P-Chip to the primary controller on C-Chip. +config RENESAS_SH7751_INTC + bool "Renesas SH7751 Interrupt Controller" + depends on SH_DEVICE_TREE || COMPILE_TEST + select IRQ_DOMAIN_HIERARCHY + help + Support for the Renesas SH7751 On-chip interrupt controller. + And external interrupt encoder for some targets. + endmenu
drivers/irqchip/Makefile +1 -0
@@ -120,3 +120,4 @@ obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o +obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o
drivers/irqchip/irq-renesas-sh7751.c new file +313 -0
313 lines not on this page · raw message
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 17/37 dt-bindings: interrupt-controller: renesas,sh7751-intc: Add json-schema
In reply to Yoshinori SatoRenesas SH7751 INTC json-schema.
Signed-off-by Yoshinori Sato <[email protected]>
--- .../renesas,sh7751-intc.yaml | 105 ++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml new file +105 -0
@@ -0,0 +1,105 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7751 Interrupt Controller + +maintainers: + - Yoshinori Sato <[email protected]> + +properties: + compatible: + items: + - const: renesas,sh7751-intc + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + reg: + maxItems: 2 + + reg-names: + items: + - const: ICR + - const: INTPRI00 + + renesas,icr-irlm: + $ref: /schemas/types.yaml#/definitions/flag + description: If true four independent interrupt requests mode (ICR.IRLM is 1). + + renesas,ipr-map: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + IRQ to IPR mapping definition. + 1st - INTEVT code + 2nd - Register + 3rd - bit index + +required: + - compatible + - reg + - reg-names + - '#interrupt-cells' + - interrupt-controller + - renesas,ipr-map + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/renesas,sh7751-intc.h> + shintc: interrupt-controller@ffd00000 { + compatible = "renesas,sh7751-intc"; + reg = <0xffd00000 14>, <0xfe080000 128>; + reg-names = "ICR", "INTPRI00"; + #interrupt-cells = <1>; + interrupt-controller; + renesas,ipr-map = <0x240 IPRD IPR_B12>, /* IRL0 */ + <0x2a0 IPRD IPR_B8>, /* IRL1 */ + <0x300 IPRD IPR_B4>, /* IRL2 */ + <0x360 IPRD IPR_B0>, /* IRL3 */ + <0x400 IPRA IPR_B12>, /* TMU0 */ + <0x420 IPRA IPR_B8>, /* TMU1 */ + <0x440 IPRA IPR_B4>, /* TMU2 TNUI */ + <0x460 IPRA IPR_B4>, /* TMU2 TICPI */ + <0x480 IPRA IPR_B0>, /* RTC ATI */ + <0x4a0 IPRA IPR_B0>, /* RTC PRI */ + <0x4c0 IPRA IPR_B0>, /* RTC CUI */ + <0x4e0 IPRB IPR_B4>, /* SCI ERI */ + <0x500 IPRB IPR_B4>, /* SCI RXI */ + <0x520 IPRB IPR_B4>, /* SCI TXI */ + <0x540 IPRB IPR_B4>, /* SCI TEI */ + <0x560 IPRB IPR_B12>, /* WDT */ + <0x580 IPRB IPR_B8>, /* REF RCMI */ + <0x5a0 IPRB IPR_B4>, /* REF ROVI */ + <0x600 IPRC IPR_B0>, /* H-UDI */ + <0x620 IPRC IPR_B12>, /* GPIO */ + <0x640 IPRC IPR_B8>, /* DMAC DMTE0 */ + <0x660 IPRC IPR_B8>, /* DMAC DMTE1 */ + <0x680 IPRC IPR_B8>, /* DMAC DMTE2 */ + <0x6a0 IPRC IPR_B8>, /* DMAC DMTE3 */ + <0x6c0 IPRC IPR_B8>, /* DMAC DMAE */ + <0x700 IPRC IPR_B4>, /* SCIF ERI */ + <0x720 IPRC IPR_B4>, /* SCIF RXI */ + <0x740 IPRC IPR_B4>, /* SCIF BRI */ + <0x760 IPRC IPR_B4>, /* SCIF TXI */ + <0x780 IPRC IPR_B8>, /* DMAC DMTE4 */ + <0x7a0 IPRC IPR_B8>, /* DMAC DMTE5 */ + <0x7c0 IPRC IPR_B8>, /* DMAC DMTE6 */ + <0x7e0 IPRC IPR_B8>, /* DMAC DMTE7 */ + <0xa00 INTPRI00 IPR_B0>, /* PCIC PCISERR */ + <0xa20 INTPRI00 IPR_B4>, /* PCIC PCIDMA3 */ + <0xa40 INTPRI00 IPR_B4>, /* PCIC PCIDMA2 */ + <0xa60 INTPRI00 IPR_B4>, /* PCIC PCIDMA1 */ + <0xa80 INTPRI00 IPR_B4>, /* PCIC PCIDMA0 */ + <0xaa0 INTPRI00 IPR_B4>, /* PCIC PCIPWON */ + <0xac0 INTPRI00 IPR_B4>, /* PCIC PCIPWDWN */ + <0xae0 INTPRI00 IPR_B4>, /* PCIC PCIERR */ + <0xb00 INTPRI00 IPR_B8>, /* TMU3 */ + <0xb80 INTPRI00 IPR_B12>; /* TMU4 */ + }; +...
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 17/37] dt-bindings: interrupt-controller: renesas,sh7751-intc: Add json-schema
Hi Yoshinori,
thanks for your patch!
Quoted 11 lines · Yoshinori Sato
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml new file +11
-0+ renesas,icr-irlm: + $ref: /schemas/types.yaml#/definitions/flag + description: If true four independent interrupt requests mode (ICR.IRLM is 1). + + renesas,ipr-map: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + IRQ to IPR mapping definition. + 1st - INTEVT code + 2nd - Register + 3rd - bit index
(...)
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml line 64
Quoted 4 lines
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml new file +4
-0+ renesas,ipr-map = <0x240 IPRD IPR_B12>, /* IRL0 */ + <0x2a0 IPRD IPR_B8>, /* IRL1 */ + <0x300 IPRD IPR_B4>, /* IRL2 */ + <0x360 IPRD IPR_B0>, /* IRL3 */
(...)
Is it really necessary to have all this in the device tree?
You know from the compatible that this is "renesas,sh7751-intc" and I bet this table will be the same for any sh7751 right?
Then just put it in a table in the driver instead and skip this from the device tree and bindings. If more interrupt controllers need to be supported by the driver, you can simply look up the table from the compatible string.
Yours,
Linus Walleij
Yoshinori Sato
maintainerRe: [DO NOT MERGE v6 17/37] dt-bindings: interrupt-controller: renesas,sh7751-intc: Add json-schema
Quoted 30 lines · Linus Walleij
Hi Yoshinori,
thanks for your patch!
Quoted 11 lines · Yoshinori Sato
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml new file +11
-0+ renesas,icr-irlm: + $ref: /schemas/types.yaml#/definitions/flag + description: If true four independent interrupt requests mode (ICR.IRLM is 1). + + renesas,ipr-map: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + IRQ to IPR mapping definition. + 1st - INTEVT code + 2nd - Register + 3rd - bit index(...)
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml line 64
Quoted 4 lines
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml new file +4
-0+ renesas,ipr-map = <0x240 IPRD IPR_B12>, /* IRL0 */ + <0x2a0 IPRD IPR_B8>, /* IRL1 */ + <0x300 IPRD IPR_B4>, /* IRL2 */ + <0x360 IPRD IPR_B0>, /* IRL3 */(...)
Is it really necessary to have all this in the device tree?
Quoted 7 lines
You know from the compatible that this is "renesas,sh7751-intc" and I bet this table will be the same for any sh7751 right?
Then just put it in a table in the driver instead and skip this from the device tree and bindings. If more interrupt controllers need to be supported by the driver, you can simply look up the table from the compatible string.
The SH interrupt controller has the same structure, only this part is different for each SoC. Currently, we are targeting only the 7751, but in the future we plan to handle all SoCs. Is it better to differentiate SoC only by compatible?
Quoted 3 lines
Yours,
Linus Walleij
Signature · 1 line
Yosinori Sato
Re: [DO NOT MERGE v6 17/37] dt-bindings: interrupt-controller: renesas,sh7751-intc: Add json-schema
Hi Sato-san,
Quoted 30 lines · Yoshinori Sato
Quoted 28 lines · Linus Walleij
Quoted 11 lines · Yoshinori Sato
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml new file +11
-0+ renesas,icr-irlm: + $ref: /schemas/types.yaml#/definitions/flag + description: If true four independent interrupt requests mode (ICR.IRLM is 1). + + renesas,ipr-map: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + IRQ to IPR mapping definition. + 1st - INTEVT code + 2nd - Register + 3rd - bit index(...)
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml line 64
Quoted 4 lines
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml new file +4
-0+ renesas,ipr-map = <0x240 IPRD IPR_B12>, /* IRL0 */ + <0x2a0 IPRD IPR_B8>, /* IRL1 */ + <0x300 IPRD IPR_B4>, /* IRL2 */ + <0x360 IPRD IPR_B0>, /* IRL3 */(...)
Is it really necessary to have all this in the device tree?
You know from the compatible that this is "renesas,sh7751-intc" and I bet this table will be the same for any sh7751 right?
Quoted 8 lines
Quoted 4 lines
Then just put it in a table in the driver instead and skip this from the device tree and bindings. If more interrupt controllers need to be supported by the driver, you can simply look up the table from the compatible string.
The SH interrupt controller has the same structure, only this part is different for each SoC. Currently, we are targeting only the 7751, but in the future we plan to handle all SoCs. Is it better to differentiate SoC only by compatible?
Yes, it is better to differentiate SoC only by compatible value.
When you describe all differences explicitly using properties, you might discover later that you missed something important, causing backwards compatibility issues with old DTBs.
DT is a stable ABI, while you can always update a driver when needed.
Gr{oetje,eeting}s,
Geert
Signature · 5 lines
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Yoshinori Sato
maintainerPATCH v6 18/37 irqchip: SH7751 external interrupt encoder with enable gate.
In reply to Yoshinori SatoSH7751 have 15 level external interrupt.
It is typically connected to the CPU through a priority encoder that can suppress requests.
This driver provides a way to control those hardware with irqchip.
Signed-off-by Yoshinori Sato <[email protected]>
--- drivers/irqchip/Kconfig | 7 + drivers/irqchip/Makefile | 2 + drivers/irqchip/irq-renesas-sh7751irl.c | 228 ++++++++++++++++++++++++ 3 files changed, 237 insertions(+) create mode 100644 drivers/irqchip/irq-renesas-sh7751irl.c
drivers/irqchip/Kconfig +7 -0
@@ -687,4 +687,11 @@ config RENESAS_SH7751_INTC Support for the Renesas SH7751 On-chip interrupt controller. And external interrupt encoder for some targets. +config RENESAS_SH7751IRL_INTC + bool "Renesas SH7751 based target IRL encoder support." + depends on RENESAS_SH7751_INTC + help + Support for External Interrupt encoder + on the some Renesas SH7751 based target. + endmenu
drivers/irqchip/Makefile +2 -0
@@ -121,3 +121,5 @@ obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o +obj-$(CONFIG_RENESAS_SH7751IRL_INTC) += irq-renesas-sh7751irl.o +
drivers/irqchip/irq-renesas-sh7751irl.c new file +228 -0
228 lines not on this page · raw message
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 19/37 dt-bindings: interrupt-controller: renesas,sh7751-irl-ext: Add json-schema
In reply to Yoshinori SatoRenesas SH7751 external interrupt encoder json-schema.
Signed-off-by Yoshinori Sato <[email protected]>
--- .../renesas,sh7751-irl-ext.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml new file +72 -0
@@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-irl-ext.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7751 external interrupt encoder with enable regs. + +maintainers: + - Yoshinori Sato <[email protected]> + +description: + This is the generally used external interrupt encoder on SH7751 based boards. + +properties: + compatible: + items: + - const: renesas,sh7751-irl-ext + + reg: true + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + '#address-cells': + const: 0 + + renesas,set-to-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: Invert enable registers. Setting the bit to 0 enables interrupts. + + renesas,enable-bit: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: | + IRQ enable register bit mapping + 1st word interrupt level + 2nd word bit index of enable register + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - renesas,enable-bit + +additionalProperties: false + +examples: + - | + r2dintc: sh7751irl_encoder@a4000000 { + compatible = "renesas,sh7751-irl-ext"; + reg = <0xa4000000 0x02>; + interrupt-controller; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <1>; + renesas,enable-bit = <0 11>, /* PCI INTD */ + <1 9>, /* CF IDE */ + <2 8>, /* CF CD */ + <3 12>, /* PCI INTC */ + <4 10>, /* SM501 */ + <5 6>, /* KEY */ + <6 5>, /* RTC ALARM */ + <7 4>, /* RTC T */ + <8 7>, /* SDCARD */ + <9 14>, /* PCI INTA */ + <10 13>, /* PCI INTB */ + <11 0>, /* EXT */ + <12 15>; /* TP */ + };
Signature · 1 line
2.39.2
Rob Herring
maintainerRe: [DO NOT MERGE v6 19/37] dt-bindings: interrupt-controller: renesas,sh7751-irl-ext: Add json-schema
Quoted 8 lines · Yoshinori Sato
Renesas SH7751 external interrupt encoder json-schema.
Signed-off-by Yoshinori Sato <[email protected]>--- .../renesas,sh7751-irl-ext.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.example.dtb: sh7751irl_encoder@a4000000: '#size-cells' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-irl-ext.yaml#
doc reference errors (make refcheckdocs):
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Rob Herring
maintainerRe: [DO NOT MERGE v6 19/37] dt-bindings: interrupt-controller: renesas,sh7751-irl-ext: Add json-schema
In reply to Yoshinori SatoQuoted 24 lines · Yoshinori Sato
Renesas SH7751 external interrupt encoder json-schema.
Signed-off-by Yoshinori Sato <[email protected]>--- .../renesas,sh7751-irl-ext.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yamlDocumentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml new file +10
-0@@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-irl-ext.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7751 external interrupt encoder with enable regs. + +maintainers: + - Yoshinori Sato <[email protected]>
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml line 20
Quoted 10 lines
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml new file +10
-0+ +description: + This is the generally used external interrupt encoder on SH7751 based boards. + +properties: + compatible: + items: + - const: renesas,sh7751-irl-ext + + reg: true
Must define how many entries and what they are if more than one.
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml line 32
Quoted 12 lines
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml new file +12
-0+ + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + '#address-cells': + const: 0 + + renesas,set-to-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: Invert enable registers. Setting the bit to 0 enables interrupts.
Why is this a property? Does it change per board or instance? If not, it should be implied by compatible.
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml line 39
Quoted 7 lines
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml new file +7
-0+ + renesas,enable-bit: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: | + IRQ enable register bit mapping + 1st word interrupt level + 2nd word bit index of enable register
Same question here.
If it remains, then you need:
items:
items:
- description: interrupt level (does that mean high/low?)
- description: bit index of enable register
Plus any constraints on the values if possible.
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml line 52
Quoted 13 lines
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml new file +13
-0+ +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - renesas,enable-bit + +additionalProperties: false + +examples: + - | + r2dintc: sh7751irl_encoder@a4000000 {
interrupt-controller@a4000000 {
Quoted 9 lines
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml new file +9
-0+ compatible = "renesas,sh7751-irl-ext"; + reg = <0xa4000000 0x02>; + interrupt-controller; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <1>; + renesas,enable-bit = <0 11>, /* PCI INTD */ + <1 9>, /* CF IDE */ + <2 8>, /* CF CD */
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml line 71
Quoted 10 lines
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml new file +10
-0+ <3 12>, /* PCI INTC */ + <4 10>, /* SM501 */ + <5 6>, /* KEY */ + <6 5>, /* RTC ALARM */ + <7 4>, /* RTC T */ + <8 7>, /* SDCARD */ + <9 14>, /* PCI INTA */ + <10 13>, /* PCI INTB */ + <11 0>, /* EXT */ + <12 15>; /* TP */
Looks like 'interrupt level' is just the index of the values? Why not make this an array?
Rob
Yoshinori Sato
maintainerPATCH v6 20/37 serial: sh-sci: fix SH4 OF support.
In reply to Yoshinori Sato- fix earlycon name.
- fix earlyprintk hung (NULL pointer reference).
- fix SERIAL_SH_SCI_EARLYCON enablement
Signed-off-by Yoshinori Sato <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
--- drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/sh-sci.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-)
drivers/tty/serial/Kconfig +1 -1
@@ -658,7 +658,7 @@ config SERIAL_SH_SCI_EARLYCON depends on SERIAL_SH_SCI=y select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON - default ARCH_RENESAS + default ARCH_RENESAS || SUPERH config SERIAL_SH_SCI_DMA bool "DMA support" if EXPERT
drivers/tty/serial/sh-sci.c +3 -3
@@ -2720,7 +2720,7 @@ static int sci_remap_port(struct uart_port *port)if (port->membase)return 0 ; -if (port->dev->of_node || (port->flags &UPF_IOREMAP )) { +if ((port->dev && port->dev->of_node) || (port->flags &UPF_IOREMAP )) { port->membase =ioremap (port->mapbase, sport->reg_size);if (unlikely (!port->membase)) {dev_err (port->dev,"can't remap port#%d\n" , port->line);
@@ -3555,8 +3555,8 @@ static int __init hscif_early_console_setup(struct earlycon_device *device,OF_EARLYCON_DECLARE (sci,"renesas,sci" , sci_early_console_setup);OF_EARLYCON_DECLARE (scif,"renesas,scif" , scif_early_console_setup); -OF_EARLYCON_DECLARE (scif,"renesas,scif-r7s9210" , rzscifa_early_console_setup); -OF_EARLYCON_DECLARE (scif,"renesas,scif-r9a07g044" , rzscifa_early_console_setup); +OF_EARLYCON_DECLARE (rzscifa,"renesas,scif-r7s9210" , rzscifa_early_console_setup); +OF_EARLYCON_DECLARE (rzscifa,"renesas,scif-r9a07g044" , rzscifa_early_console_setup);OF_EARLYCON_DECLARE (scifa,"renesas,scifa" , scifa_early_console_setup);OF_EARLYCON_DECLARE (scifb,"renesas,scifb" , scifb_early_console_setup);OF_EARLYCON_DECLARE (hscif,"renesas,hscif" , hscif_early_console_setup);
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 21/37 dt-bindings: serial: renesas,scif: Add scif-sh7751.
In reply to Yoshinori SatoAdd Renesas SH7751 SCIF.
Signed-off-by Yoshinori Sato <[email protected]>
--- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/serial/renesas,scif.yaml +1 -0
@@ -18,6 +18,7 @@ properties: - items: - enum: - renesas,scif-r7s72100 # RZ/A1H + - renesas,scif-sh7751 # SH7751 - const: renesas,scif # generic SCIF compatible UART - items:
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 21/37] dt-bindings: serial: renesas,scif: Add scif-sh7751.
Quoted 3 lines · Yoshinori Sato
Add Renesas SH7751 SCIF.
Signed-off-by Yoshinori Sato <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
Signature · 5 lines
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Yoshinori Sato
maintainerPATCH v6 22/37 dt-bindings: display: smi,sm501: SMI SM501 binding json-schema
In reply to Yoshinori SatoSigned-off-by Yoshinori Sato <[email protected]>
--- .../bindings/display/smi,sm501.yaml | 417 ++++++++++++++++++ 1 file changed, 417 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/smi,sm501.yaml
Documentation/devicetree/bindings/display/smi,sm501.yaml new file +417 -0
@@ -0,0 +1,417 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/smi,sm501.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Motion SM501 Mobile Multimedia Companion Chip + +maintainers: + - Yoshinori Sato <[email protected]> + +description: | + These DT bindings describe the SM501. + +properties: + compatible: + const: + smi,sm501 + + reg: + maxItems: 2 + description: | + First entry: System Configuration register + Second entry: IO space (Display Controller register) + + interrupts: + description: SM501 interrupt to the cpu should be described here. + + mode: + $ref: /schemas/types.yaml#/definitions/string + description: select a video mode + + edid: + description: | + verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller. + + little-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: available on big endian systems, to set different foreign endian. + big-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: available on little endian systems, to set different foreign endian. + + swap-fb-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: swap framebuffer byteorder. + + route-crt-panel: + $ref: /schemas/types.yaml#/definitions/flag + description: Panel output merge to CRT. + + crt: + type: object + description: CRT output control + properties: + edid: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: | + verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller. + + smi,flags: + $ref: /schemas/types.yaml#/definitions/string-array + description: Display control flags. + items: + anyOf: + - const: use-init-done + - const: disable-at-exit + - const: use-hwcursor + - const: use-hwaccel + - const: panel-no-fpen + - const: panel-no-vbiasen + - const: panel-inv-fpen + - const: panel-inv-vbiasen + maxItems: 8 + + bpp: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Color depth + + panel: + type: object + description: Panel output control + properties: + edid: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: | + verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller. + + smi,flags: + $ref: /schemas/types.yaml#/definitions/string-array + description: Display control flags. + items: + anyOf: + - const: use-init-done + - const: disable-at-exit + - const: use-hwcursor + - const: use-hwaccel + - const: panel-no-fpen + - const: panel-no-vbiasen + - const: panel-inv-fpen + - const: panel-inv-vbiasen + maxItems: 8 + + bpp: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Color depth + + smi,devices: + $ref: /schemas/types.yaml#/definitions/string-array + description: Select SM501 device functions. + items: + anyOf: + - const: usb-host + - const: usb-slave + - const: ssp0 + - const: ssp1 + - const: uart0 + - const: uart1 + - const: fbaccel + - const: ac97 + - const: i2s + - const: gpio + minItems: 1 + maxItems: 10 + + smi,mclk: + $ref: /schemas/types.yaml#/definitions/uint32 + description: mclk frequency. + + smi,m1xclk: + $ref: /schemas/types.yaml#/definitions/uint32 + description: m1xclk frequency. + + misc-timing: + type: object + description: Miscellaneous Timing register values. + properties: + ex: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Extend bus holding time. + enum: [0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240] + + xc: + $ref: /schemas/types.yaml#/definitions/string + description: Xscale clock input select. + items: + enum: + - internal-pll + - hclk + - gpio33 + + us: + $ref: /schemas/types.yaml#/definitions/string + description: USB host current detection. + items: + enum: + - disable + - enable + + ssm1: + $ref: /schemas/types.yaml#/definitions/string + description: SDRAM clock select for PW mode 1. + items: + enum: + - 288mhz + - div + + sm1: + $ref: /schemas/types.yaml#/definitions/uint32 + description: SDRAM clock divider for PW mode 1. + enum: [1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, 384] + + ssm0: + $ref: /schemas/types.yaml#/definitions/string + description: SDRAM clock select for PW mode 0. + items: + enum: + - 288mhz + - div + + sm0: + $ref: /schemas/types.yaml#/definitions/uint32 + description: SDRAM clock divider for PW mode 0. + enum: [1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, 384] + + deb: + $ref: /schemas/types.yaml#/definitions/string + description: 96MHz PLL debug control. + items: + enum: + - input-reference + - output + + acpi: + $ref: /schemas/types.yaml#/definitions/string + description: ACPI control. + items: + enum: + - disable + - enable + + divider: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Second PLL output frequency. + enum: [336, 288, 240, 192] + + usb-mode: + $ref: /schemas/types.yaml#/definitions/string + description: USB Host mode. + items: + enum: + - normal + - simulation + + delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Delay time to latch read data. Set the value to 10x. + enum: [5, 10, 15, 20, 25] + + misc-control: + type: object + description: Miscellaneous Control register values. + properties: + pad: + $ref: /schemas/types.yaml#/definitions/uint32 + description: PCI Pad drive strength. + enum: [24, 12, 8] + + usbclk: + $ref: /schemas/types.yaml#/definitions/string + description: USB Clcok Select. + items: + enum: + - crystal + - 96mhz + - 48mhz + + uart-ssp: + $ref: /schemas/types.yaml#/definitions/string + description: UART1/SSP1 select. + items: + enum: + - uart1 + - ssp1 + + lat: + $ref: /schemas/types.yaml#/definitions/string + description: 8051 Latch enable. + items: + enum: + - disable + - enable + + fp: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Flat Panel data select. + enum: [18, 24] + + freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Frequency select. + enum: [24, 12] + + refresh: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Internal memory refresh timing. + enum: [8, 16, 32, 64] + + hold: + $ref: /schemas/types.yaml#/definitions/uint32 + description: BUS Hold time. + enum: [0, 8, 16, 24, 32] + + sh: + $ref: /schemas/types.yaml#/definitions/string + description: SuperH ready polarity. + items: + enum: + - active-low + - active-high + + ii: + $ref: /schemas/types.yaml#/definitions/string + description: Interrupt Inverting. + items: + enum: + - normal + - invert + + pll: + $ref: /schemas/types.yaml#/definitions/string + description: PLL clock count. + items: + enum: + - disable + - enable + + gap: + $ref: /schemas/types.yaml#/definitions/string + description: DAC Band GAP control. + items: + const: default + + dac: + $ref: /schemas/types.yaml#/definitions/string + description: DAC Power control. + items: + enum: + - disable + - enable + + mc: + $ref: /schemas/types.yaml#/definitions/string + description: USB slave controller. + items: + enum: + - cpu + - '8051' + + bl: + $ref: /schemas/types.yaml#/definitions/uint32 + description: CPU Master burst length. + enum: [8, 1] + + usb: + $ref: /schemas/types.yaml#/definitions/string + description: USB port select. + items: + enum: + - master + - slave + + lb: + $ref: /schemas/types.yaml#/definitions/string + description: USB loop-back select. + items: + enum: + - normal + - loopback + vr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: NEC VR Memory map select. + enum: [30, 62] + + gpio-pin-control: + type: object + description: GPIO control configuration. + properties: + pin: + type: object + properties: + gpio: + $ref: /schemas/types.yaml#/definitions/flag + description: pin in/out use GPIO. + function: + $ref: /schemas/types.yaml#/definitions/flag + description: pin in/out use function. + + gpio-i2c: + type: object + description: GPIO I2C definition. + properties: + i2c: + type: object + properties: + bus: + $ref: /schemas/types.yaml#/definitions/uint32 + description: I2C bus number. + + sda: + $ref: /schemas/types.yaml#/definitions/uint32 + description: I2C SDA pin port number. + + scl: + $ref: /schemas/types.yaml#/definitions/uint32 + description: I2C SCL pin port number. + + delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: bit transmission delay. + + timeout: + $ref: /schemas/types.yaml#/definitions/uint32 + description: transmission timeout. + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + + +examples: + # MPC5200 + - | + display@1,0 { + compatible = "smi,sm501"; + reg = <0x00000000 0x00800000 + 0x03e00000 0x00200000>; + interrupts = <1 1 3>; + mode = "640x480-32@60"; + edid = [00 ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00 + 00 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 f0 0a 80 fb 20 e0 25 10 32 60 + 02 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bd]; + };
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 22/37] dt-bindings: display: smi,sm501: SMI SM501 binding json-schema
Hi Sato-san,
Quoted 1 line · Yoshinori Sato
Signed-off-by Yoshinori Sato <[email protected]>
Thanks for your patch!
Quoted 4 lines
--- .../bindings/display/smi,sm501.yaml | 417 ++++++++++++++++++ 1 file changed, 417 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/smi,sm501.yaml
Surely Documentation/devicetree/bindings/display/sm501fb.txt should be removed, too?
Quoted 13 lines
Documentation/devicetree/bindings/display/smi,sm501.yaml new file +10
-0+ crt: + type: object + description: CRT output control + properties: + edid: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: | + verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller.
Documentation/devicetree/bindings/display/smi,sm501.yaml line 73
Quoted 10 lines
Documentation/devicetree/bindings/display/smi,sm501.yaml new file +10
-0+ + smi,flags: + $ref: /schemas/types.yaml#/definitions/string-array + description: Display control flags. + items: + anyOf: + - const: use-init-done + - const: disable-at-exit + - const: use-hwcursor + - const: use-hwaccel
The "use-*" flags look like software policy, not hardware description, and thus do not belong in DT?
Quoted 20 lines
Documentation/devicetree/bindings/display/smi,sm501.yaml new file +20
-0+ - const: panel-no-fpen + - const: panel-no-vbiasen + - const: panel-inv-fpen + - const: panel-inv-vbiasen + maxItems: 8 + + bpp: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Color depth + + panel: + type: object + description: Panel output control + properties: + edid: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: | + verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller.
Documentation/devicetree/bindings/display/smi,sm501.yaml line 103
Quoted 10 lines
Documentation/devicetree/bindings/display/smi,sm501.yaml new file +10
-0+ + smi,flags: + $ref: /schemas/types.yaml#/definitions/string-array + description: Display control flags. + items: + anyOf: + - const: use-init-done + - const: disable-at-exit + - const: use-hwcursor + - const: use-hwaccel
The "use-*" flags look like software policy, not hardware description, and thus do not belong in DT?
Quoted 17 lines
Documentation/devicetree/bindings/display/smi,sm501.yaml new file +17
-0+ - const: panel-no-fpen + - const: panel-no-vbiasen + - const: panel-inv-fpen + - const: panel-inv-vbiasen + maxItems: 8 + + bpp: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Color depth + + smi,devices: + $ref: /schemas/types.yaml#/definitions/string-array + description: Select SM501 device functions. + items: + anyOf: + - const: usb-host + - const: usb-slave
Documentation/devicetree/bindings/display/smi,sm501.yaml line 130
Quoted 10 lines
Documentation/devicetree/bindings/display/smi,sm501.yaml new file +10
-0+ - const: ssp0 + - const: ssp1 + - const: uart0 + - const: uart1 + - const: fbaccel + - const: ac97 + - const: i2s + - const: gpio + minItems: 1 + maxItems: 10
I think it would be better to have individual subnodes for the sub devices, with status = "ok"/"disabled".
If you go that route, you do need some fallback code to handle the lack of subnodes in the existing user in arch/powerpc/boot/dts/charon.dts.
BTW, why can sm501_pci_initdata get away with setting ".devices = SM501_USE_ALL"? Or, would it hurt to enable all subdevices unconditionally?
Documentation/devicetree/bindings/display/smi,sm501.yaml line 138
Quoted 8 lines
Documentation/devicetree/bindings/display/smi,sm501.yaml new file +8
-0+ + smi,mclk: + $ref: /schemas/types.yaml#/definitions/uint32 + description: mclk frequency. + + smi,m1xclk: + $ref: /schemas/types.yaml#/definitions/uint32 + description: m1xclk frequency.
These two should be clock specifiers (i.e. phandles pointing to clock nodes + optional clock indices).
Quoted 8 lines
Documentation/devicetree/bindings/display/smi,sm501.yaml new file +8
-0+ + misc-timing: + type: object + description: Miscellaneous Timing register values. + properties: + ex: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Extend bus holding time.
Documentation/devicetree/bindings/display/smi,sm501.yaml line 156
Quoted 10 lines
Documentation/devicetree/bindings/display/smi,sm501.yaml new file +10
-0+ enum: [0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240] + + xc: + $ref: /schemas/types.yaml#/definitions/string + description: Xscale clock input select. + items: + enum: + - internal-pll + - hclk + - gpio33
Software policy instead of hardware description again?
I am not familiar with how the SM501 works, so I cannot comment on the other properties, but several of them look like they need rework.
Gr{oetje,eeting}s,
Geert
Signature · 5 lines
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Yoshinori Sato
maintainerPATCH v6 23/37 mfd: sm501: Convert platform_data to OF property
In reply to Yoshinori SatoVarious parameters of SM501 can be set using platform_data, so parameters cannot be passed in the DeviceTree target. Expands the parameters set in platform_data so that they can be specified using DeviceTree properties.
Signed-off-by Yoshinori Sato <[email protected]>
--- drivers/mfd/sm501.c | 436 ++++++++++++++++++++++++++++++++++ drivers/video/fbdev/sm501fb.c | 106 +++++++++ 2 files changed, 542 insertions(+)
drivers/mfd/sm501.c +436 -0
@@ -82,6 +82,23 @@ struct sm501_devdata {unsigned int rev; }; +enum prop_type { +PROP_NUM ,PROP_STR , +}; + +enum val_type { +ENDIS ,MT_EX ,MT_XC ,MT_SSM ,MT_SM ,MT_DEBUG ,MT_DIV ,MT_USB ,MT_DELAY , +MC_PAD ,MC_USBCLK ,MC_SSP ,MC_FP ,MC_FREQ ,MC_REFRESH ,MC_HOLD ,MC_SH , +MC_II ,MC_GAP ,MC_DAC ,MC_MC ,MC_BL ,MC_USB ,MC_LB ,MC_VR , +}; + +struct sm501_config_props { +char *name; +u32 shift; +u32 width; +enum prop_type prop_type; +enum val_type val_type; +};#define MHZ (1000 * 1000)
@@ -1370,6 +1387,419 @@ static int sm501_init_dev(struct sm501_devdata *sm)return 0 ; } +static u32 lookup_str (const char *val,const char *const *list) +{ +u32 ret =0 ; + +while (*list) { +if (strcmp (val, *list) ==0 ) +return ret; + list++; + ret++; + } +return ~0 ; +} + +static u32 lookup_num (u32 val,const u32 *list) +{ +u32 ret =0 ; + +while (*list != ~0 ) { +if (val == *list) +return ret; + list++; + ret++; + } +return ~0 ; +} + +static const struct sm501_config_props misc_timming[] = { + {"ex" ,28 ,4 ,PROP_NUM ,MT_EX }, + {"xc" ,24 ,2 ,PROP_STR ,MT_XC }, + {"us" ,23 ,1 ,PROP_STR ,ENDIS }, + {"ssm1" ,20 ,1 ,PROP_STR ,MT_SSM }, + {"sm1" ,16 ,4 ,PROP_NUM ,MT_SM }, + {"ssm0" ,12 ,1 ,PROP_STR ,MT_SSM }, + {"sm0" ,8 ,4 ,PROP_NUM ,MT_SM }, + {"deb" ,7 ,1 ,PROP_STR ,MT_DEBUG }, + {"acpi" ,6 ,1 ,PROP_STR ,ENDIS }, + {"divider" ,4 ,2 ,PROP_NUM ,MT_DIV }, + {"usb-mode" ,3 ,1 ,PROP_STR ,MT_USB }, + {"delay" ,0 ,3 ,PROP_NUM ,MT_DELAY }, + {}, +}; + +static const struct sm501_config_props misc_control[] = { + {"pad" ,30 ,2 ,PROP_NUM ,MC_PAD }, + {"usbclk" ,28 ,2 ,PROP_STR ,MC_USBCLK }, + {"uart-ssp" ,27 ,1 ,PROP_STR ,MC_SSP }, + {"lat" ,26 ,1 ,PROP_STR ,ENDIS }, + {"fp" ,25 ,1 ,PROP_NUM ,MC_FP }, + {"freq" ,24 ,1 ,PROP_NUM ,MC_FREQ }, + {"refresh" ,21 ,2 ,PROP_NUM ,MC_REFRESH }, + {"hold" ,18 ,3 ,PROP_NUM ,MC_HOLD }, + {"sh" ,17 ,1 ,PROP_STR ,MC_SH }, + {"ii" ,16 ,1 ,PROP_STR ,MC_II }, + {"pll" ,15 ,1 ,PROP_STR ,ENDIS }, + {"gap" ,13 ,2 ,PROP_STR ,MC_GAP }, + {"dac" ,12 ,1 ,PROP_STR ,MC_DAC }, + {"mc" ,11 ,1 ,PROP_STR ,MC_MC }, + {"bl" ,10 ,1 ,PROP_NUM ,MC_BL }, + {"usb" ,9 ,1 ,PROP_STR ,MC_USB }, + {"lb" ,8 ,1 ,PROP_STR ,MC_LB }, + {"vr" ,4 ,1 ,PROP_NUM ,MC_VR }, + {}, +}; + +/* Read configuration values */ +static void sm501_of_read_config (struct device *dev,struct device_node *np, +const char *prefix, +const struct sm501_config_props *props, +struct sm501_reg_init *ret) +{ +static const char *const endis[] = {"disable" ,"enable" ,NULL }; +static const char *const xc[] = {"internal-pll" ,"hclk" ,"gpio33" ,NULL }; +static const char *const ssm[] = {"288mhz" ,"div" ,NULL }; +static const char *const debmode[] = {"input-reference" ,"output" ,NULL }; +static const char *const usbmode[] = {"normal" ,"simulation" ,NULL }; +static const char *const usbclk[] = {"crystal" ,"-" ,"96mhz" ,"48mhz" ,NULL }; +static const char *const ssp[] = {"uart1" ,"ssp1" ,NULL }; +static const char *const sh_ready[] = {"active-low" ,"active-high" ,NULL }; +static const char *const int_invert[] = {"normal" ,"invert" ,NULL }; +static const char *const slave[] = {"cpu" ,"8051" ,NULL }; +static const char *const usbport[] = {"master" ,"slave" ,NULL }; +static const char *const usbloop[] = {"normal" ,"loopback" ,NULL }; + +static const u32 divrate[] = {336 ,288 ,240 ,192 , ~0 }; +static const u32 fpdata[] = {18 ,24 , ~0 }; +static const u32 cfreq[] = {24 ,12 , ~0 }; +static const u32 bushold[] = {0 ,8 ,16 ,24 ,32 , ~0 }; +static const u32 burst[] = {8 ,1 , ~0 }; +static const u32 vrmem[] = {30 ,62 , ~0 }; + +struct device_node *child; +const char *sval; +u32 mask; +u32 val; +int err; + + ret->mask = ~0 ; + ret->set =0 ; + + child =of_get_child_by_name (np, prefix); +if (!child) +return ; + +while (props->name) { +switch (props->prop_type) { +case PROP_NUM : + err =of_property_read_u32 (child, props->name, &val); +break ; +case PROP_STR : + err =of_property_read_string (child, props->name, &sval); +break ; + } +if (!err) { +switch (props->val_type) { +case ENDIS : + val =lookup_str (sval, endis); +break ; +case MT_EX : + val /=16 ; +break ; +case MT_XC : + val =lookup_str (sval, xc); +break ; +case MT_SSM : + val =lookup_str (sval, ssm); +break ; +case MT_SM : +if ((val %3 ) ==0 ) { + val /=3 ; + val =ffs (val); + val +=8 ; + }else { + val =ffs (val); + } +break ; +case MT_DEBUG : + val =lookup_str (sval, debmode); +break ; +case MT_DIV : + val =lookup_num (val, divrate); +break ; +case MT_USB : + val =lookup_str (sval, usbmode); +break ; +case MT_DELAY : + val /=5 ; +break ; +case MC_PAD : + val /=8 ; + val =2 - val; +break ; +case MC_USBCLK : + val =lookup_str (sval, usbclk); +break ; +case MC_SSP : + val =lookup_str (sval, ssp); +break ; +case MC_FP : + val =lookup_num (val, fpdata); +break ; +case MC_FREQ : + val =lookup_num (val, cfreq); +break ; +case MC_REFRESH : + val =ffs (val) -3 ; +break ; +case MC_HOLD : + val =lookup_num (val, bushold); +break ; +case MC_SH : + val =lookup_str (sval, sh_ready); +break ; +case MC_II : + val =lookup_str (sval, int_invert); +break ; +case MC_GAP : +if (!strcmp (sval,"default" )) + val =0 ; +else + val = ~0 ; +break ; +case MC_DAC : + val =lookup_str (sval, endis) ^1 ; +break ; +case MC_MC : + val =lookup_str (sval, slave); +break ; +case MC_BL : + val =lookup_num (val, burst); +break ; +case MC_USB : + val =lookup_str (sval, usbport); +break ; +case MC_LB : + val =lookup_str (sval, usbloop); +break ; +case MC_VR : + val =lookup_num (val, vrmem); +break ; + } + mask = (1 << props->width) -1 ; +if (mask >= val) { + mask = ~(mask << props->shift); + ret->mask &= mask; + ret->set |= val << props->shift; + }else { +switch (props->prop_type) { +case PROP_NUM : +dev_warn (dev,"%s invalid value %d" , + props->name, val); + +break ; +case PROP_STR : +dev_warn (dev,"%s invalid value %s" , + props->name, sval); +break ; + } + } + } + props++; + } +} + +/* Read GPIO control */ +/* +* DT example. +* gpio-pin-control { +* pin@0 { +* gpio-port; +* }; +* pin@1 { +* function; +* }; +* }; +*/ +static void sm501_of_read_gpio (struct device *dev,struct device_node *np, +struct sm501_reg_init *hi,struct sm501_reg_init *low) +{ +struct device_node *gpio_group, *pin; +const char *prop_mode; +unsigned int pin_no; +int mode; +u64 mask; +u64 set; + + mask = ~0 ; + set =0 ; + gpio_group =of_get_child_by_name (np,"gpio-pin-control" ); +if (gpio_group) { +for_each_child_of_node (gpio_group, pin) { + mode =-1 ; +if (sscanf (pin->full_name,"pin@%u" , &pin_no) ==1 ) { +if (of_property_read_bool (pin,"gpio-port" )) + mode =0 ; +else if (of_property_read_bool (pin,"function" )) + mode =1 ; + } +/* GPIO0 - 47 and 55 -63 */ +if (mode <0 || + (pin_no >=64 || (pin_no >=48 && pin_no <=54 ))) { +dev_warn (dev, +"%s mode %s is invalid." , pin->name, prop_mode); + }else { + mask &= ~(1 << pin_no); + set |= mode << pin_no; + } + } + } + hi->set = set >>32 ; + low->set = set &0xffffffff ; + hi->mask = mask >>32 ; + low->mask = mask &0xffffffff ; +} + +static inline int read_i2c_prop (struct device *dev,struct device_node *child, +const char *name,u32 *val) +{ +if (of_property_read_u32 (child, name, val)) { +dev_warn (dev,"%s/%s not found. skip it." ,of_node_full_name (child), name); +return -ENOENT ; + } +return 0 ; +} + +/* Read GPIO I2C configuration */ +/* +* DT example. +* gpio-i2c { +* i2c@0 { +* sda = <gpio-pin>; +* scl = <gpio-pin>; +* delay = <delay>; +* timeout = <timeout>; +* }; +* i2c@1 { +* : +* }; +* : +* }; +*/ +static int sm501_parse_dt_gpio_i2c (struct device *dev,struct sm501_platdata *plat, +struct device_node *np) +{ +struct device_node *i2c_group, *child; +unsigned int i; +u32 i2c_nr; +int err; + + i2c_group =of_get_child_by_name (np,"gpio-i2c" ); +if (!i2c_group) +return 0 ; + + i2c_nr =of_get_child_count (i2c_group); + plat->gpio_i2c =devm_kzalloc (dev,sizeof (*plat->gpio_i2c) * i2c_nr, +GFP_KERNEL ); +if (!plat->gpio_i2c) +return -ENOMEM ; + + plat->gpio_i2c_nr = i2c_nr; + i =0 ; +for_each_child_of_node (i2c_group, child) { +u32 bus; + +if (sscanf (child->full_name,"i2c@%u" , &bus) !=1 ) { +dev_warn (dev,"Unknown address %s\n" , child->name); +continue ; + } + + err =0 ; + plat->gpio_i2c[i].bus_num = bus; + err +=read_i2c_prop (dev, child,"sda" , &plat->gpio_i2c[i].pin_sda); + err +=read_i2c_prop (dev, child,"scl" , &plat->gpio_i2c[i].pin_scl); + err +=read_i2c_prop (dev, child,"delay" , &plat->gpio_i2c[i].udelay); + err +=read_i2c_prop (dev, child,"timeout" , &plat->gpio_i2c[i].timeout); +if (err ==0 ) + i++; + } + +return 0 ; +} + +/* Read device functions */ +static u32 sm501_read_devices (struct device *dev,struct device_node *np) +{ +static const char *const funcname[] = { +"usb-host" ,"usb-slave" ,"ssp0" ,"ssp1" , +"uart0" ,"uart1" ,"fbaccel" ,"ac97" , +"i2s" ,"gpio" , + }; +struct property *prop; +unsigned int i; +const char *s; +u32 ret =0 ; + +of_property_for_each_string (np,"smi,devices" , prop, s) { +for (i =0 ; i <ARRAY_SIZE (funcname); i++) { +if (strcmp (s, funcname[i]) ==0 ) { + ret |=1 << i; + goto next; + } + } +dev_warn (dev,"Unknown device function '%s'" , s); +next: + } +if (!ret) +dev_warn (dev,"devices not defined. disable all functions." ); +return ret; +} + +/* Build platform_data from OF property */ +struct plat_dt { +struct sm501_platdata plat; +struct sm501_initdata init; +}; + +static int sm501_parse_dt (struct sm501_devdata *sm,struct device_node *np) +{ +struct sm501_platdata *plat; +struct plat_dt *dt_p; +u32 word; +int ret; + + dt_p =devm_kzalloc (sm->dev,sizeof (*dt_p),GFP_KERNEL ); +if (!dt_p) +return -ENOMEM ; + + plat = &dt_p->plat; + plat->init = &dt_p->init; + + plat->init->devices =sm501_read_devices (sm->dev, np); +/* mclk and m1xclk are not u32, so convert between them using intermediate variables. */ +of_property_read_u32 (np,"smi,mclk" , &word); + plat->init->mclk = word; +of_property_read_u32 (np,"smi,m1xclk" , &word); + plat->init->m1xclk = word; + +sm501_of_read_config (sm->dev, np,"misc-timing" , misc_timming, + &plat->init->misc_timing); +sm501_of_read_config (sm->dev, np,"misc-control" , misc_control, + &plat->init->misc_control); +sm501_of_read_gpio (sm->dev, np, + &plat->init->gpio_high, &plat->init->gpio_low); + +if (IS_ENABLED (CONFIG_MFD_SM501_GPIO ) && + (plat->init->devices &SM501_USE_GPIO )) { + ret =sm501_parse_dt_gpio_i2c (sm->dev, plat, np); +if (ret) +return ret; + } + sm->platdata = plat; +return 0 ; +} +static int sm501_plat_probe (struct platform_device *dev) {struct sm501_devdata *sm;
@@ -1406,6 +1836,12 @@ static int sm501_plat_probe(struct platform_device *dev) goto err_res; } +if (IS_ENABLED (CONFIG_OF ) && dev->dev.of_node) { + ret =sm501_parse_dt (sm, dev->dev.of_node); +if (ret) + goto err_res; + } +platform_set_drvdata (dev, sm); sm->regs =ioremap (sm->io_res->start,resource_size (sm->io_res));
drivers/video/fbdev/sm501fb.c +106 -0
118 lines not on this page · raw message
Signature · 1 line
2.39.2
Lee Jones
maintainerRe: [DO NOT MERGE v6 23/37] mfd: sm501: Convert platform_data to OF property
Quoted 8 lines · Yoshinori Sato
Various parameters of SM501 can be set using
platform_data, so parameters cannot be passed in the DeviceTree target. Expands the parameters set inplatform_dataso that they can be specified using DeviceTree properties.Signed-off-by Yoshinori Sato <[email protected]>--- drivers/mfd/sm501.c | 436 ++++++++++++++++++++++++++++++++++
How has this grown from 99 lines to 436 lines?
Most of it almost certainly needs moving (back?) out to the leaf drivers. A great deal of the properties parsed in here are only relevant to a single device (display for instance). Please move all non-generic handling out to the relevant subsystems.
Quoted 2 lines
drivers/video/fbdev/sm501fb.c | 106 +++++++++ 2 files changed, 542 insertions(+)
Signature · 1 line
Lee Jones [李琼斯]
Yoshinori Sato
maintainerPATCH v6 24/37 dt-binding: sh: cpus: Add SH CPUs json-schema
In reply to Yoshinori SatoRenesas SH series and compatible ISA CPUs.
Signed-off-by Yoshinori Sato <[email protected]>
--- .../devicetree/bindings/sh/cpus.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/sh/cpus.yaml
Documentation/devicetree/bindings/sh/cpus.yaml new file +74 -0
@@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sh/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SuperH CPUs + +maintainers: + - Yoshinori Sato <[email protected]> + +description: |+ + The device tree allows to describe the layout of CPUs in a system through + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") + defining properties for every cpu. + + Bindings for CPU nodes follow the Devicetree Specification, available from: + + https://www.devicetree.org/specifications/ + +properties: + compatible: + anyOf: + - items: + - enum: + - renesas,sh2a + - renesas,sh3 + - renesas,sh4 + - renesas,sh4a + - jcore,j2 + - const: renesas,sh2 + - const: renesas,sh2 + + clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: CPU core clock frequency. + + clocks: + maxItems: 1 + + clock-names: true + + reg: + maxItems: 1 + + device_type: true + +required: + - compatible + - reg + - device_type + +additionalProperties: true + +examples: + - | + #include <dt-bindings/clock/sh7750-cpg.h> + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + compatible = "renesas,sh4", "renesas,sh2"; + device_type = "cpu"; + reg = <0>; + clocks = <&cpg SH7750_CPG_ICK>; + clock-names = "ick"; + icache-size = <16384>; + icache-line-size = <32>; + dcache-size = <32768>; + dcache-line-size = <32>; + }; + }; +...
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 24/37] dt-binding: sh: cpus: Add SH CPUs json-schema
Yo,
Quoted 23 lines · Yoshinori Sato
Renesas SH series and compatible ISA CPUs.
Signed-off-by Yoshinori Sato <[email protected]>--- .../devicetree/bindings/sh/cpus.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/sh/cpus.yamlDocumentation/devicetree/bindings/sh/cpus.yaml new file +9
-0@@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sh/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SuperH CPUs + +maintainers:
Documentation/devicetree/bindings/sh/cpus.yaml line 19
Quoted 10 lines
Documentation/devicetree/bindings/sh/cpus.yaml new file +10
-0+ - Yoshinori Sato <[email protected]> + +description: |+ + The device tree allows to describe the layout of CPUs in a system through + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") + defining properties for every cpu. + + Bindings for CPU nodes follow the Devicetree Specification, available from: + + https://www.devicetree.org/specifications/
You likely copied this description from the arm binding (or from dt-schema), but I don't think this is anything other than a statement of the obvious. If there is a description here it should (IMO) talk about the superh cpus.
Quoted 7 lines
Documentation/devicetree/bindings/sh/cpus.yaml new file +7
-0+ +properties: + compatible: + anyOf: + - items: + - enum: + - renesas,sh2a
Documentation/devicetree/bindings/sh/cpus.yaml line 36
Quoted 10 lines
Documentation/devicetree/bindings/sh/cpus.yaml new file +10
-0+ - renesas,sh3 + - renesas,sh4 + - renesas,sh4a + - jcore,j2 + - const: renesas,sh2 + - const: renesas,sh2 + + clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: CPU core clock frequency.
What is the point of this? You have a clocks property, can't you obtain the clock frequency by looking up the provider of that clock?
Documentation/devicetree/bindings/sh/cpus.yaml line 41
Quoted 5 lines
Documentation/devicetree/bindings/sh/cpus.yaml new file +5
-0+ + clocks: + maxItems: 1 + + clock-names: true
Why do you need clock-names if you only have one clock?
Documentation/devicetree/bindings/sh/cpus.yaml line 53
Quoted 12 lines
Documentation/devicetree/bindings/sh/cpus.yaml new file +12
-0+ + reg: + maxItems: 1 + + device_type: true + +required: + - compatible + - reg + - device_type + +additionalProperties: true
This should be unevaluatedProperties: false
Properties like the icache-size are documented in cpu.yaml and you can add an reference to that to permit them. The riscv cpus binding does this if you need to see how that works.
Cheers,
Conor.
Quoted 23 lines
Documentation/devicetree/bindings/sh/cpus.yaml new file +20
-0+examples: + - | + #include <dt-bindings/clock/sh7750-cpg.h> + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + compatible = "renesas,sh4", "renesas,sh2"; + device_type = "cpu"; + reg = <0>; + clocks = <&cpg SH7750_CPG_ICK>; + clock-names = "ick"; + icache-size = <16384>; + icache-line-size = <32>; + dcache-size = <32768>; + dcache-line-size = <32>; + }; + }; +...Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 25/37 dt-bindings: vendor-prefixes: Add iodata
In reply to Yoshinori SatoAdd IO DATA DEVICE INC.
https://www.iodata.com/
Signed-off-by Yoshinori Sato <[email protected]>
--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/vendor-prefixes.yaml +2 -0
@@ -671,6 +671,8 @@ patternProperties: description: Inventec "^inversepath,.*": description: Inverse Path + "^iodata,.*": + description: IO DATA DEVICE Inc. "^iom,.*": description: Iomega Corporation "^irondevice,.*":
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 25/37] dt-bindings: vendor-prefixes: Add iodata
Quoted 4 lines · Yoshinori Sato
Add IO DATA DEVICE INC.
https://www.iodata.com/Signed-off-by Yoshinori Sato <[email protected]>
I think you are missing an r-b tag here from Geert:
https://lore.kernel.org/all/CAMuHMdUvNT1tDTOq4ppqn69cocAeveaXrsoL2VQ2efBQ+hv2aA@mail.gmail.com/
Acked-by Conor Dooley <[email protected]>
Cheers,
Conor.
Quoted 20 lines
--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)Documentation/devicetree/bindings/vendor-prefixes.yaml +2
-0@@ -671,6 +671,8 @@ patternProperties: description: Inventec "^inversepath,.*": description: Inverse Path + "^iodata,.*": + description: IO DATA DEVICE Inc. "^iom,.*": description: Iomega Corporation "^irondevice,.*":Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 25/37] dt-bindings: vendor-prefixes: Add iodata
In reply to Yoshinori SatoQuoted 4 lines · Yoshinori Sato
Add IO DATA DEVICE INC.
https://www.iodata.com/Signed-off-by Yoshinori Sato <[email protected]>
My
Reviewed-by Geert Uytterhoeven <[email protected]>
on v3 is still valid.
Gr{oetje,eeting}s,
Geert
Signature · 5 lines
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Yoshinori Sato
maintainerPATCH v6 26/37 dt-bindings: vendor-prefixes: Add smi
In reply to Yoshinori SatoAdd Silicon Mortion Technology Corporation
https://www.siliconmotion.com/
Signed-off-by Yoshinori Sato <[email protected]>
--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/vendor-prefixes.yaml +2 -0
@@ -1283,6 +1283,8 @@ patternProperties: description: Skyworks Solutions, Inc. "^smartlabs,.*": description: SmartLabs LLC + "^smi,.*": + description: Silicon Motion Technology Corporation "^smsc,.*": description: Standard Microsystems Corporation "^snps,.*":
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 26/37] dt-bindings: vendor-prefixes: Add smi
Quoted 13 lines · Yoshinori Sato
Add Silicon Mortion Technology Corporation
https://www.siliconmotion.com/Signed-off-by Yoshinori Sato <[email protected]>--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)Documentation/devicetree/bindings/vendor-prefixes.yaml +0
-0
Documentation/devicetree/bindings/vendor-prefixes.yaml patternProperties: · line 1287
Quoted 5 lines
Documentation/devicetree/bindings/vendor-prefixes.yaml +2
-0@@ -1283,6 +1283,8 @@ patternProperties: description: Skyworks Solutions, Inc. "^smartlabs,.*": description: SmartLabs LLC + "^smi,.*": + description: Silicon Motion Technology Corporation
How come "smi" is used for a company with this name?
Why is it not something like SMTC? There's probably some history here that I am unaware of.
Cheers,
Conor.
Quoted 6 lines
Documentation/devicetree/bindings/vendor-prefixes.yaml +0
-0"^smsc,.*": description: Standard Microsystems Corporation "^snps,.*":Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 26/37] dt-bindings: vendor-prefixes: Add smi
Hi Conor,
Quoted 2 lines · Conor Dooley
Quoted 1 line · Yoshinori Sato
Add Silicon Mortion Technology Corporation
Motion
Quoted 7 lines
Quoted 7 lines
https://www.siliconmotion.com/
Signed-off-by Yoshinori Sato <[email protected]>--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)
Quoted 14 lines
Documentation/devicetree/bindings/vendor-prefixes.yaml patternProperties: · line 1287
Quoted 10 lines
Documentation/devicetree/bindings/vendor-prefixes.yaml +2
-0@@ -1283,6 +1283,8 @@ patternProperties: description: Skyworks Solutions, Inc. "^smartlabs,.*": description: SmartLabs LLC + "^smi,.*": + description: Silicon Motion Technology CorporationHow come "smi" is used for a company with this name?
Why is it not something like SMTC? There's probably some history here that I am unaware of.
See Documentation/devicetree/bindings/display/sm501fb.txt The stock ticker is "SIMO", though.
https://www.nasdaq.com/market-activity/stocks/simo
Gr{oetje,eeting}s,
Geert
Signature · 5 lines
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Re: [DO NOT MERGE v6 26/37] dt-bindings: vendor-prefixes: Add smi
Quoted 30 lines · Geert Uytterhoeven
Hi Conor,
Quoted 2 lines · Conor Dooley
Quoted 1 line · Yoshinori Sato
Add Silicon Mortion Technology Corporation
Motion
Quoted 7 lines
Quoted 7 lines
https://www.siliconmotion.com/
Signed-off-by Yoshinori Sato <[email protected]>--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)Quoted 14 lines
Documentation/devicetree/bindings/vendor-prefixes.yaml patternProperties: · line 1287
Quoted 10 lines
Documentation/devicetree/bindings/vendor-prefixes.yaml +2
-0@@ -1283,6 +1283,8 @@ patternProperties: description: Skyworks Solutions, Inc. "^smartlabs,.*": description: SmartLabs LLC + "^smi,.*": + description: Silicon Motion Technology CorporationHow come "smi" is used for a company with this name?
Why is it not something like SMTC? There's probably some history here that I am unaware of.
Quoted 4 lines
See
Documentation/devicetree/bindings/display/sm501fb.txtThe stock ticker is "SIMO", though.
https://www.nasdaq.com/market-activity/stocks/simo
From https://en.wikipedia.org/wiki/Silicon_Motion:
"Controllers are marketed under the “SMI” brand,
enterprise-grade SSDs under the "Shannon Systems" brand.
"
Guenter
Conor Dooley
Acked-byRe: [DO NOT MERGE v6 26/37] dt-bindings: vendor-prefixes: Add smi
In reply to Geert UytterhoevenQuoted 30 lines · Geert Uytterhoeven
Hi Conor,
Quoted 2 lines · Conor Dooley
Quoted 1 line · Yoshinori Sato
Add Silicon Mortion Technology Corporation
Motion
Quoted 7 lines
Quoted 7 lines
https://www.siliconmotion.com/
Signed-off-by Yoshinori Sato <[email protected]>--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)Quoted 14 lines
Documentation/devicetree/bindings/vendor-prefixes.yaml patternProperties: · line 1287
Quoted 10 lines
Documentation/devicetree/bindings/vendor-prefixes.yaml +2
-0@@ -1283,6 +1283,8 @@ patternProperties: description: Skyworks Solutions, Inc. "^smartlabs,.*": description: SmartLabs LLC + "^smi,.*": + description: Silicon Motion Technology CorporationHow come "smi" is used for a company with this name?
Why is it not something like SMTC? There's probably some history here that I am unaware of.
Quoted 3 lines
See
Documentation/devicetree/bindings/display/sm501fb.txtThe stock ticker is "SIMO", though.
https://www.nasdaq.com/market-activity/stocks/simo
If there's an existing user, there's little reason to stand in the way I think.
Acked-by Conor Dooley <[email protected]>
Cheers,
Conor.
Rob Herring
maintainerRe: [DO NOT MERGE v6 26/37] dt-bindings: vendor-prefixes: Add smi
Quoted 31 lines · Conor Dooley
Quoted 30 lines · Geert Uytterhoeven
Hi Conor,
Quoted 2 lines · Conor Dooley
Quoted 1 line · Yoshinori Sato
Add Silicon Mortion Technology Corporation
Motion
Quoted 21 lines
Quoted 12 lines
https://www.siliconmotion.com/
Signed-off-by Yoshinori Sato <[email protected]>--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)Documentation/devicetree/bindings/vendor-prefixes.yaml +0
-0Documentation/devicetree/bindings/vendor-prefixes.yaml patternProperties: · line 1287
Quoted 5 lines
Documentation/devicetree/bindings/vendor-prefixes.yaml +2
-0@@ -1283,6 +1283,8 @@ patternProperties: description: Skyworks Solutions, Inc. "^smartlabs,.*": description: SmartLabs LLC + "^smi,.*": + description: Silicon Motion Technology CorporationHow come "smi" is used for a company with this name?
Why is it not something like SMTC? There's probably some history here that I am unaware of.
Quoted 7 lines
Quoted 3 lines
See
Documentation/devicetree/bindings/display/sm501fb.txtThe stock ticker is "SIMO", though.
https://www.nasdaq.com/market-activity/stocks/simoIf there's an existing user, there's little reason to stand in the way I think.
Acked-by Conor Dooley <[email protected]>
Or reason not to apply, so I'm applying this.
BTW, 'RFC' is the standard way to say 'DO NOT MERGE'.
Rob
Re: [DO NOT MERGE v6 26/37] dt-bindings: vendor-prefixes: Add smi
In reply to Yoshinori SatoHello,
not a complete review, I just note that there is a duplicate space in the Subject. You might want to fix for the next patch round.
Best regards
Uwe
Signature · 2 lines
Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | https://www.pengutronix.de/ |
Yoshinori Sato
maintainerPATCH v6 27/37 dt-bindings: ata: ata-generic: Add new targets
In reply to Yoshinori SatoAdded new ata-generic target.
- iodata,usl-5p-ata
- renesas,rts7751r2d-ata
Each boards have simple IDE Interface. Use ATA generic driver.
Signed-off-by Yoshinori Sato <[email protected]>
--- Documentation/devicetree/bindings/ata/ata-generic.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/ata/ata-generic.yaml +2 -0
@@ -18,6 +18,8 @@ properties: - enum: - arm,vexpress-cf - fsl,mpc8349emitx-pata + - iodata,usl-5p-ata + - renesas,rts7751r2d-ata - const: ata-generic reg:
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 27/37] dt-bindings: ata: ata-generic: Add new targets
Quoted 7 lines · Yoshinori Sato
Added new ata-generic target.
- iodata,usl-5p-ata
- renesas,rts7751r2d-ataEach boards have simple IDE Interface. Use ATA generic driver.
Signed-off-by Yoshinori Sato <[email protected]>
Acked-by Conor Dooley <[email protected]>
Cheers,
Conor.
Quoted 20 lines
--- Documentation/devicetree/bindings/ata/ata-generic.yaml | 2 ++ 1 file changed, 2 insertions(+)Documentation/devicetree/bindings/ata/ata-generic.yaml +2
-0@@ -18,6 +18,8 @@ properties: - enum: - arm,vexpress-cf - fsl,mpc8349emitx-pata + - iodata,usl-5p-ata + - renesas,rts7751r2d-ata - const: ata-generic reg:Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 27/37] dt-bindings: ata: ata-generic: Add new targets
Quoted 10 lines · Conor Dooley
Quoted 7 lines · Yoshinori Sato
Added new ata-generic target.
- iodata,usl-5p-ata
- renesas,rts7751r2d-ataEach boards have simple IDE Interface. Use ATA generic driver.
Signed-off-by Yoshinori Sato <[email protected]>Acked-by Conor Dooley <[email protected]>
That said, a bullet point list in the commit message of what compatibles you added isn't really achieving anything, you can drop that from the commit message if/when you resend the series.
Quoted 24 lines
Cheers,
Conor.Quoted 20 lines
--- Documentation/devicetree/bindings/ata/ata-generic.yaml | 2 ++ 1 file changed, 2 insertions(+)Documentation/devicetree/bindings/ata/ata-generic.yaml +2
-0@@ -18,6 +18,8 @@ properties: - enum: - arm,vexpress-cf - fsl,mpc8349emitx-pata + - iodata,usl-5p-ata + - renesas,rts7751r2d-ata - const: ata-generic reg:Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 27/37] dt-bindings: ata: ata-generic: Add new targets
In reply to Yoshinori SatoQuoted 5 lines · Yoshinori Sato
Added new ata-generic target.
- iodata,usl-5p-ata
- renesas,rts7751r2d-ataEach boards have simple IDE Interface. Use ATA generic driver.
This looks OK to me, so feel free to add:
Acked-by Damien Le Moal <[email protected]>
Note: The "DO NOT MERGE" patch prefix almost got me to immediately delete this 37 patches in my inbox... If you wish to get this work merged after review, please use the regular "PATCH" prefix. No worries, the series will not be merged until is is reviewed :)
Signature · 2 lines
Damien Le Moal Western Digital Research
Re: [DO NOT MERGE v6 27/37] dt-bindings: ata: ata-generic: Add new targets
Quoted 7 lines · Damien Le Moal
Quoted 5 lines · Yoshinori Sato
Added new ata-generic target.
- iodata,usl-5p-ata
- renesas,rts7751r2d-ataEach boards have simple IDE Interface. Use ATA generic driver.
Quoted 8 lines
This looks OK to me, so feel free to add:
Acked-by Damien Le Moal <[email protected]>Note: The "DO NOT MERGE" patch prefix almost got me to immediately delete this 37 patches in my inbox... If you wish to get this work merged after review, please use the regular "PATCH" prefix. No worries, the series will not be merged until is is reviewed :)
The point of DO NOT MERGE was that feedback was not being implemented and same set of patches with same issues were kept sending. :/
Best regards,
Krzysztof
Damien Le Moal
maintainerRe: [DO NOT MERGE v6 27/37] dt-bindings: ata: ata-generic: Add new targets
Quoted 12 lines · Krzysztof Kozlowski
Quoted 11 lines · Damien Le Moal
Quoted 5 lines · Yoshinori Sato
Added new ata-generic target.
- iodata,usl-5p-ata
- renesas,rts7751r2d-ataEach boards have simple IDE Interface. Use ATA generic driver.
This looks OK to me, so feel free to add:
Acked-by Damien Le Moal <[email protected]>
Quoted 7 lines
Quoted 4 lines
Note: The "DO NOT MERGE" patch prefix almost got me to immediately delete this 37 patches in my inbox... If you wish to get this work merged after review, please use the regular "PATCH" prefix. No worries, the series will not be merged until is is reviewed :)
The point of DO NOT MERGE was that feedback was not being implemented and same set of patches with same issues were kept sending. :/
OK. I found that prefix unusual, but not a big deal. Thanks.
Quoted 4 lines
Best regards,
Krzysztof
Signature · 2 lines
Damien Le Moal Western Digital Research
Yoshinori Sato
maintainerPATCH v6 28/37 dt-bindings: soc: renesas: sh: Add SH7751 based target
In reply to Yoshinori SatoSigned-off-by Yoshinori Sato <[email protected]>
--- .../devicetree/bindings/soc/renesas/sh.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/sh.yaml
Documentation/devicetree/bindings/soc/renesas/sh.yaml new file +32 -0
@@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/sh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SuperH Platform + +maintainers: + - Yoshinori Sato <[email protected]> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: RTS7751R2D Plus + items: + - enum: + - renesas,rts7751r2d # Renesas SH4 2D graphics board + - const: renesas,sh7751r + + - description: Julian board + items: + - enum: + - iodata,landisk # LANDISK HDL-U + - iodata,usl-5p # USL-5P + - const: renesas,sh7751r + +additionalProperties: true + +...
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 28/37] dt-bindings: soc: renesas: sh: Add SH7751 based target
Hi Sato-san,
Quoted 1 line · Yoshinori Sato
Signed-off-by Yoshinori Sato <[email protected]>
Thanks for your patch!
Quoted 21 lines
Documentation/devicetree/bindings/soc/renesas/sh.yaml new file +18
-0@@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/sh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SuperH Platform + +maintainers: + - Yoshinori Sato <[email protected]> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: RTS7751R2D Plus + items:
Documentation/devicetree/bindings/soc/renesas/sh.yaml line 28
Quoted 10 lines
Documentation/devicetree/bindings/soc/renesas/sh.yaml new file +10
-0+ - enum: + - renesas,rts7751r2d # Renesas SH4 2D graphics board + - const: renesas,sh7751r + + - description: Julian board + items: + - enum: + - iodata,landisk # LANDISK HDL-U + - iodata,usl-5p # USL-5P + - const: renesas,sh7751r
As both use the same fallback compatible value, I would just merge them into a single section for SH7751R.
Documentation/devicetree/bindings/soc/renesas/sh.yaml line 32
Quoted 4 lines
Documentation/devicetree/bindings/soc/renesas/sh.yaml new file +4
-0+ +additionalProperties: true + +...
Gr{oetje,eeting}s,
Geert
Signature · 5 lines
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Yoshinori Sato
maintainerPATCH v6 29/37 sh: SH7751R SoC Internal peripheral definition dtsi.
In reply to Yoshinori SatoSH7751R internal peripherals device tree.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/boot/dts/sh7751r.dtsi | 148 ++++++++++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) create mode 100644 arch/sh/boot/dts/sh7751r.dtsi
arch/sh/boot/dts/sh7751r.dtsi new file +148 -0
@@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the SH7751R SoC + */ + +#include <dt-bindings/interrupt-controller/renesas,sh7751-intc.h> +#include <dt-bindings/clock/sh7750-cpg.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "renesas,sh4", "renesas,sh2"; + device_type = "cpu"; + reg = <0>; + clocks = <&cpg SH7750_CPG_ICK>; + clock-names = "ick"; + icache-size = <16384>; + icache-line-size = <32>; + dcache-size = <32768>; + dcache-line-size = <32>; + }; + }; + + xtal: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "xtal"; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&shintc>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cpg: clock-controller@ffc00000 { + #clock-cells = <1>; + #power-domain-cells = <0>; + compatible = "renesas,sh7751r-cpg"; + clocks = <&xtal>; + clock-names = "xtal"; + reg = <0xffc00000 20>, <0xfe0a0000 16>; + reg-names = "FRQCR", "CLKSTP00"; + renesas,mode = <0>; + }; + + shintc: interrupt-controller@ffd00000 { + compatible = "renesas,sh7751-intc"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xffd00000 20>, <0xfe080000 128>; + reg-names = "ICR", "INTPRI00"; + renesas,ipr-map = <0x240 IPRD IPR_B12>, /* IRL0 */ + <0x2a0 IPRD IPR_B8>, /* IRL1 */ + <0x300 IPRD IPR_B4>, /* IRL2 */ + <0x360 IPRD IPR_B0>, /* IRL3 */ + <0x400 IPRA IPR_B12>, /* TMU0 */ + <0x420 IPRA IPR_B8>, /* TMU1 */ + <0x440 IPRA IPR_B4>, /* TMU2 TNUI */ + <0x460 IPRA IPR_B4>, /* TMU2 TICPI */ + <0x480 IPRA IPR_B0>, /* RTC ATI */ + <0x4a0 IPRA IPR_B0>, /* RTC PRI */ + <0x4c0 IPRA IPR_B0>, /* RTC CUI */ + <0x4e0 IPRB IPR_B4>, /* SCI ERI */ + <0x500 IPRB IPR_B4>, /* SCI RXI */ + <0x520 IPRB IPR_B4>, /* SCI TXI */ + <0x540 IPRB IPR_B4>, /* SCI TEI */ + <0x560 IPRB IPR_B12>, /* WDT */ + <0x580 IPRB IPR_B8>, /* REF RCMI */ + <0x5a0 IPRB IPR_B4>, /* REF ROVI */ + <0x600 IPRC IPR_B0>, /* H-UDI */ + <0x620 IPRC IPR_B12>, /* GPIO */ + <0x640 IPRC IPR_B8>, /* DMAC DMTE0 */ + <0x660 IPRC IPR_B8>, /* DMAC DMTE1 */ + <0x680 IPRC IPR_B8>, /* DMAC DMTE2 */ + <0x6a0 IPRC IPR_B8>, /* DMAC DMTE3 */ + <0x6c0 IPRC IPR_B8>, /* DMAC DMAE */ + <0x700 IPRC IPR_B4>, /* SCIF ERI */ + <0x720 IPRC IPR_B4>, /* SCIF RXI */ + <0x740 IPRC IPR_B4>, /* SCIF BRI */ + <0x760 IPRC IPR_B4>, /* SCIF TXI */ + <0x780 IPRC IPR_B8>, /* DMAC DMTE4 */ + <0x7a0 IPRC IPR_B8>, /* DMAC DMTE5 */ + <0x7c0 IPRC IPR_B8>, /* DMAC DMTE6 */ + <0x7e0 IPRC IPR_B8>, /* DMAC DMTE7 */ + <0xa00 INTPRI00 IPR_B0>, /* PCIC PCISERR */ + <0xa20 INTPRI00 IPR_B4>, /* PCIC PCIDMA3 */ + <0xa40 INTPRI00 IPR_B4>, /* PCIC PCIDMA2 */ + <0xa60 INTPRI00 IPR_B4>, /* PCIC PCIDMA1 */ + <0xa80 INTPRI00 IPR_B4>, /* PCIC PCIDMA0 */ + <0xaa0 INTPRI00 IPR_B4>, /* PCIC PCIPWON */ + <0xac0 INTPRI00 IPR_B4>, /* PCIC PCIPWDWN */ + <0xae0 INTPRI00 IPR_B4>, /* PCIC PCIERR */ + <0xb00 INTPRI00 IPR_B8>, /* TMU3 */ + <0xb80 INTPRI00 IPR_B12>; /* TMU4 */ + }; + + /* sci0 is rarely used, so it is not defined here. */ + scif1: serial@ffe80000 { + compatible = "renesas,scif-sh7751", "renesas,scif"; + reg = <0xffe80000 0x100>; + interrupts = <0x700>, + <0x720>, + <0x760>, + <0x740>; + interrupt-names = "eri", "rxi", "txi", "bri"; + clocks = <&cpg SH7750_MSTP_SCIF>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + /* Normally ch0 and ch1 are used, so we will define ch0 to ch2 here. */ + tmu0: timer@ffd80000 { + compatible = "renesas,tmu-sh7750", "renesas,tmu"; + reg = <0xffd80000 12>; + interrupts = <0x400>, + <0x420>, + <0x440>, + <0x460>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg SH7750_MSTP_TMU012>; + clock-names = "fck"; + power-domains = <&cpg>; + #renesas,channels = <3>; + }; + + pcic: pci@fe200000 { + compatible = "renesas,sh7751-pci"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + bus-range = <0 0>; + reg = <0xfe200000 0x0400>, + <0xff800000 0x0100>; + status = "disabled"; + }; + }; +};
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 30/37 sh: add RTS7751R2D Plus DTS
In reply to Yoshinori SatoRenesas RTS7751R2D Plus devicetree.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/boot/dts/rts7751r2dplus.dts | 180 ++++++++++++++++++++++++++++ arch/sh/boot/dts/sh7751r.dtsi | 4 + 2 files changed, 184 insertions(+) create mode 100644 arch/sh/boot/dts/rts7751r2dplus.dts
arch/sh/boot/dts/rts7751r2dplus.dts new file +180 -0
@@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Renesas RTS7751R2D Plus + */ + +/dts-v1/; + +#include "sh7751r.dtsi" + +/ { + model = "Renesas RTS7715R2D Plus"; + compatible = "renesas,rts7751r2d", "renesas,sh7751r"; + + aliases { + serial0 = &scif1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@c000000 { + device_type = "memory"; + reg = <0x0c000000 0x4000000>; + }; + + r2dintc: interrupt-controller@a4000000 { + compatible = "renesas,sh7751-irl-ext"; + reg = <0xa4000000 0x02>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + renesas,enable-bit = <0 11>, /* PCI INTD */ + <1 9>, /* CF IDE */ + <2 8>, /* CF CD */ + <3 12>, /* PCI INTC */ + <4 10>, /* SM501 */ + <5 6>, /* KEY */ + <6 5>, /* RTC ALARM */ + <7 4>, /* RTC T */ + <8 7>, /* SDCARD */ + <9 14>, /* PCI INTA */ + <10 13>, /* PCI INTB */ + <11 0>, /* EXT */ + <12 15>; /* TP */ + }; + + display@0 { + compatible = "smi,sm501"; + reg = <0x10000000 0x03e00000 + 0x13e00000 0x00200000>; + interrupt-parent = <&r2dintc>; + interrupts = <4>; + mode = "640x480-16@60"; + little-endian; + smi,devices = "usb-host", "uart0"; + swap-fb-endian; + + crt { + smi,flags = "use-init-done", + "disable-at-exit", + "use-hwcursor", + "use-hwaccel"; + }; + + panel { + bpp = <16>; + edid = [00 ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00 + 00 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 f0 0a 80 fb 20 e0 25 10 32 60 + 02 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bd]; + smi,flags = "use-init-done", + "disable-at-exit", + "use-hwcursor", + "use-hwaccel"; + }; + misc-timing { + ex = <16>; + xc = "internal-pll"; + us = "disable"; + }; + misc-control { + pad = <24>; + usbclk = "crystal"; + sh = "active-low"; + }; + gpio-pin-control { + pin@0 { + gpio-port; + }; + pin@1 { + function; + }; + }; + + gpio-i2c { + i2c@0 { + sda = <1>; + scl = <2>; + delay = <100>; + timeout = <1000>; + }; + }; + }; + + compact-flash@b4001000 { + compatible = "renesas,rts7751r2d-ata", "ata-generic"; + reg = <0xb4001000 0x0e>, <0xb400080c 2>; + reg-shift = <1>; + interrupt-parent = <&r2dintc>; + interrupts = <1>; + }; + + flash@0 { + compatible = "cfi-flash"; + reg = <0x00000000 0x02000000>; + device-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x00000000 0x00040000>; + }; + + partition@1 { + label = "Environemt"; + reg = <0x00040000 0x00040000>; + }; + + partition@2 { + label = "Kernel"; + reg = <0x00080000 0x001c0000>; + }; + + partition@3 { + label = "Flash_FS"; + reg = <0x00240000 0x00dc0000>; + }; + }; +}; + +&xtal { + clock-frequency = <22222222>; +}; + +&cpg { + renesas,mode = <5>; +}; + +&scif1 { + status = "okay"; +}; + +&pcic { + ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>, + <0x01000000 0 0x00000000 0xfe240000 0 0x00040000>; + dma-ranges = <0x02000000 0 0x0c000000 0x0c000000 0 0x04000000>; + + interrupt-map = <0x0000 0 0 1 &r2dintc 9>, + <0x0000 0 0 2 &r2dintc 10>, + <0x0000 0 0 3 &r2dintc 3>, + <0x0000 0 0 4 &r2dintc 0>, + <0x0800 0 0 1 &r2dintc 10>, + <0x0800 0 0 2 &r2dintc 3>, + <0x0800 0 0 3 &r2dintc 0>, + <0x0800 0 0 4 &r2dintc 9>, + <0x1000 0 0 1 &r2dintc 3>, + <0x1000 0 0 2 &r2dintc 0>, + <0x1000 0 0 3 &r2dintc 9>, + <0x1000 0 0 4 &r2dintc 10>; + interrupt-map-mask = <0x1800 0 0 7>; + pci-bar = <0 0xab000001>, <2 0xd0000000>; + pci-command-reg-io-space; + status = "okay"; +};
arch/sh/boot/dts/sh7751r.dtsi +4 -0
@@ -142,6 +142,10 @@ pcic: pci@fe200000 { bus-range = <0 0>; reg = <0xfe200000 0x0400>, <0xff800000 0x0100>; + pci-command-reg-special-cycle; + pci-command-reg-parity-error-response; + pci-command-reg-bus-master; + pci-command-reg-memory-space; status = "disabled"; }; };
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 31/37 sh: Add IO DATA LANDISK dts
In reply to Yoshinori SatoIO DATA DEVICE Inc. LANDISK HDL-U devicetree.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/boot/dts/landisk.dts | 75 ++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 arch/sh/boot/dts/landisk.dts
arch/sh/boot/dts/landisk.dts new file +75 -0
@@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the IO DATA DEVICE LANDISK + */ + +/dts-v1/; + +#include "sh7751r.dtsi" + +/ { + model = "IO DATA Device LANDISK"; + compatible = "iodata,landisk", "renesas,sh7751r"; + + aliases { + serial0 = &scif1; + }; + + chosen { + stdout-path = "serial0:9600n8"; + }; + + memory@c000000 { + device_type = "memory"; + reg = <0x0c000000 0x4000000>; + }; + + julianintc: interrupt-controller@b0000005 { + compatible = "renesas,sh7751-irl-ext"; + reg = <0xb0000005 0x01>; + interrupt-controller; + #interrupt-cells = <1>; + renesas,enable-bit = <5 0>, /* PCI INTA */ + <6 1>, /* PCI INTB */ + <7 2>, /* PCI INTC */ + <8 3>, /* PCI INTD */ + <9 4>, /* ATA */ + <10 5>, /* CF */ + <11 6>, /* Power Switch */ + <12 7>; /* Button */ + }; +}; + +&xtal { + clock-frequency = <22222222>; +}; + +&cpg { + renesas,mode = <5>; +}; + +&scif1 { + status = "okay"; +}; + +&pcic { + ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>, + <0x01000000 0 0x00000000 0xfe240000 0 0x00040000>; + dma-ranges = <0x02000000 0 0x0c000000 0x0c000000 0 0x04000000>; + interrupt-map = <0x0000 0 0 1 &julianintc 5>, + <0x0000 0 0 2 &julianintc 6>, + <0x0000 0 0 3 &julianintc 7>, + <0x0000 0 0 4 &julianintc 8>, + <0x0800 0 0 1 &julianintc 6>, + <0x0800 0 0 2 &julianintc 7>, + <0x0800 0 0 3 &julianintc 8>, + <0x0800 0 0 4 &julianintc 5>, + <0x1000 0 0 1 &julianintc 7>, + <0x1000 0 0 2 &julianintc 8>, + <0x1000 0 0 3 &julianintc 5>, + <0x1000 0 0 4 &julianintc 6>; + interrupt-map-mask = <0x1800 0 0 7>; + pci-bar = <2 0xd0000000>; + pci-command-reg-io-space; + status = "okay"; +};
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 32/37 sh: Add IO DATA USL-5P dts
In reply to Yoshinori SatoIO DATA DEVICE Inc. USL-5P devicetree.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/boot/dts/usl-5p.dts | 83 +++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 arch/sh/boot/dts/usl-5p.dts
arch/sh/boot/dts/usl-5p.dts new file +83 -0
@@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the IO DATA DEVICE USL-5P + */ + +/dts-v1/; + +#include "sh7751r.dtsi" + +/ { + model = "IO-DATA Device USL-5P"; + compatible = "iodata,usl-5p", "renesas,sh7751r"; + + aliases { + serial0 = &scif1; + }; + + chosen { + stdout-path = "serial0:9600n8"; + }; + + memory@c000000 { + device_type = "memory"; + reg = <0x0c000000 0x4000000>; + }; + + julianintc: interrupt-controller@b0000005 { + compatible = "renesas,sh7751-irl-ext"; + reg = <0xb0000005 0x01>; + interrupt-controller; + #interrupt-cells = <1>; + renesas,enable-bit = <5 0>, /* PCI INTA */ + <6 1>, /* PCI INTB */ + <7 2>, /* PCI INTC */ + <8 3>, /* PCI INTD */ + <9 4>, /* ATA */ + <10 5>, /* CF */ + <11 6>, /* Power Switch */ + <12 7>; /* Button */ + }; + + compact-flash@b4000040 { + compatible = "iodata,usl-5p-ata", "ata-generic"; + reg = <0xb4000040 0x0e>, <0xb400002c 2>; + reg-shift = <1>; + interrupt-parent = <&julianintc>; + interrupts = <10>; + }; +}; + +&xtal { + clock-frequency = <22222222>; +}; + +&cpg { + renesas,mode = <5>; +}; + +&scif1 { + status = "okay"; +}; + +&pcic { + ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>, + <0x01000000 0 0x00000000 0xfe240000 0 0x00040000>; + dma-ranges = <0x02000000 0 0x0c000000 0x0c000000 0 0x04000000>; + interrupt-map = <0x0000 0 0 1 &julianintc 5>, + <0x0000 0 0 2 &julianintc 6>, + <0x0000 0 0 3 &julianintc 7>, + <0x0000 0 0 4 &julianintc 8>, + <0x0800 0 0 1 &julianintc 6>, + <0x0800 0 0 2 &julianintc 7>, + <0x0800 0 0 3 &julianintc 8>, + <0x0800 0 0 4 &julianintc 5>, + <0x1000 0 0 1 &julianintc 7>, + <0x1000 0 0 2 &julianintc 8>, + <0x1000 0 0 3 &julianintc 5>, + <0x1000 0 0 4 &julianintc 6>; + interrupt-map-mask = <0x1800 0 0 7>; + pci-bar = <2 0xd0000000>; + pci-command-reg-io-space; + status = "okay"; +};
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 33/37 sh: j2_mimas_v2.dts update
In reply to Yoshinori SatoSigned-off-by Yoshinori Sato <[email protected]>
--- arch/sh/boot/dts/j2_mimas_v2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/sh/boot/dts/j2_mimas_v2.dts +1 -1
@@ -16,7 +16,7 @@ cpus { cpu@0 { device_type = "cpu"; - compatible = "jcore,j2"; + compatible = "jcore,j2", "renesas,sh2"; reg = <0>; clock-frequency = <50000000>; d-cache-size = <8192>;
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 33/37] sh: j2_mimas_v2.dts update
Hi Sato-san,
Quoted 1 line · Yoshinori Sato
Signed-off-by Yoshinori Sato <[email protected]>
Thanks for your patch!
Please enhance the one-line summary, e.g.
sh: j2_mimas_v2: Update CPU compatible value
For the actual changes:
Reviewed-by Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
Signature · 5 lines
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Yoshinori Sato
maintainerPATCH v6 34/37 sh: Add dtbs target support.
In reply to Yoshinori SatoSigned-off-by Yoshinori Sato <[email protected]>
--- arch/sh/boot/dts/Makefile | 5 +++++ 1 file changed, 5 insertions(+)
arch/sh/boot/dts/Makefile +5 -0
@@ -1,2 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_USE_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_SOURCE)) + +dtb-$(CONFIG_CPU_J2) += j2_mimas_v2.dtb +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += landisk.dtb +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += rts7751r2dplus.dtb +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += usl-5p.dtb
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v6 34/37] sh: Add dtbs target support.
Quoted 1 line · Yoshinori Sato
Signed-off-by Yoshinori Sato <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
Signature · 5 lines
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Yoshinori Sato
maintainerPATCH v6 35/37 sh: RTS7751R2D Plus OF defconfig
In reply to Yoshinori SatoSigned-off-by Yoshinori Sato <[email protected]>
--- arch/sh/configs/rts7751r2dplus-of_defconfig | 80 +++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 arch/sh/configs/rts7751r2dplus-of_defconfig
arch/sh/configs/rts7751r2dplus-of_defconfig new file +80 -0
@@ -0,0 +1,80 @@ +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_PROFILING=y +CONFIG_CPU_SUBTYPE_SH7751R=y +CONFIG_MEMORY_START=0x0c000000 +CONFIG_SH_OF_BOARD=y +CONFIG_HEARTBEAT=y +CONFIG_ZERO_PAGE_OFFSET=0x00010000 +CONFIG_MODULES=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IPV6 is not set +CONFIG_PCI=y +CONFIG_HOTPLUG_PCI=y +CONFIG_PCI_SH7751=y +CONFIG_UEVENT_HELPER=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_PHYSMAP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_SD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ATA=y +CONFIG_PATA_OF_PLATFORM=y +CONFIG_NETDEVICES=y +CONFIG_8139CP=y +CONFIG_8139TOO=y +# CONFIG_8139TOO_PIO is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_SH_SCI=y +CONFIG_HW_RANDOM=y +CONFIG_SPI=y +CONFIG_SPI_SH_SCI=y +CONFIG_MFD_SM501=y +CONFIG_FB=y +CONFIG_FB_SH_MOBILE_LCDC=m +CONFIG_FB_SM501=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +# CONFIG_LOGO_SUPERH_MONO is not set +# CONFIG_LOGO_SUPERH_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=m +CONFIG_SND_YMFPCI=m +CONFIG_HID_GYRATION=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SUNPLUS=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_R9701=y +CONFIG_RENESAS_SH7751_INTC=y +CONFIG_RENESAS_SH7751IRL_INTC=y +CONFIG_EXT2_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_MINIX_FS=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_CRC_T10DIF=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_FS=y +# CONFIG_FTRACE is not set
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 36/37 sh: LANDISK OF defconfig
In reply to Yoshinori SatoSigned-off-by Yoshinori Sato <[email protected]>
--- arch/sh/configs/landisk-of_defconfig | 104 +++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 arch/sh/configs/landisk-of_defconfig
arch/sh/configs/landisk-of_defconfig new file +104 -0
@@ -0,0 +1,104 @@ +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_KEXEC=y +CONFIG_CPU_SUBTYPE_SH7751R=y +CONFIG_MEMORY_START=0x0c000000 +CONFIG_SH_OF_BOARD=y +CONFIG_HEARTBEAT=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_PNP=y +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +CONFIG_ATALK=m +CONFIG_PCI=y +CONFIG_PCI_SH7751=y +CONFIG_PCCARD=y +CONFIG_YENTA=y +CONFIG_UEVENT_HELPER=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ATA=y +CONFIG_PATA_ARTOP=y +CONFIG_PATA_OF_PLATFORM=y +CONFIG_ATA_GENERIC=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_NETDEVICES=y +CONFIG_TUN=m +CONFIG_8139CP=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_HW_RANDOM=y +CONFIG_SOUND=m +CONFIG_HID_A4TECH=m +CONFIG_HID_BELKIN=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GYRATION=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SUNPLUS=m +CONFIG_USB_HID=m +CONFIG_USB=y +CONFIG_USB_MON=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_PRINTER=m +CONFIG_USB_STORAGE=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_SISUSBVGA=m +CONFIG_RENESAS_SH7751_INTC=y +CONFIG_RENESAS_SH7751IRL_INTC=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_REISERFS_FS=y +CONFIG_ISO9660_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y +CONFIG_TMPFS=y +CONFIG_ROMFS_FS=y +CONFIG_UFS_FS=m +CONFIG_NFS_FS=m +CONFIG_NFSD=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_INIT_STACK_NONE=y +CONFIG_CRC_T10DIF=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_FTRACE is not set +CONFIG_SH_STANDARD_BIOS=y
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v6 37/37 sh: j2_defconfig: update
In reply to Yoshinori SatoI've changed some symbols related to DeviceTree,
so let's take care of those changes.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/configs/j2_defconfig | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-)
arch/sh/configs/j2_defconfig +3 -8
@@ -1,18 +1,15 @@ -CONFIG_SMP=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_CPU_SUBTYPE_J2=y CONFIG_MEMORY_START=0x10000000 -CONFIG_MEMORY_SIZE=0x04000000 CONFIG_CPU_BIG_ENDIAN=y -CONFIG_SH_DEVICE_TREE=y -CONFIG_SH_JCORE_SOC=y +CONFIG_SH_OF_BOARD=y CONFIG_HZ_100=y +CONFIG_SMP=y CONFIG_CMDLINE_OVERWRITE=y CONFIG_CMDLINE="console=ttyUL0 earlycon" -CONFIG_BINFMT_ELF_FDPIC=y CONFIG_BINFMT_FLAT=y CONFIG_NET=y CONFIG_PACKET=y
@@ -21,7 +18,6 @@ CONFIG_INET=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_NETDEVICES=y -CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_UARTLITE=y CONFIG_SERIAL_UARTLITE_CONSOLE=y CONFIG_I2C=y
@@ -30,8 +26,6 @@ CONFIG_SPI_JCORE=y CONFIG_WATCHDOG=y CONFIG_MMC=y CONFIG_MMC_SPI=y -CONFIG_CLKSRC_JCORE_PIT=y -CONFIG_JCORE_AIC=y CONFIG_EXT4_FS=y CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
@@ -40,3 +34,4 @@ CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_UTF8=y +CONFIG_INIT_STACK_NONE=y
Signature · 1 line
2.39.2