riscv: sophgo: add reset support for SG2042
cover riscv: sophgo: add reset support for SG2042
From: Chen Wang <[email protected]>
This series adds reset controller support for Sophgo SG2042 using reset-simple driver.
Chen Wang (4):
dt-bindings: reset: sophgo: support SG2042
reset: sophgo: add SG2042 reset generator driver
riscv: dts: add reset generator for Sophgo SG2042 SoC
riscv: dts: add resets property for uart node
.../bindings/reset/sophgo,sg2042-reset.yaml | 35 ++++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 9 ++ drivers/reset/Kconfig | 1 + drivers/reset/reset-simple.c | 2 + drivers/reset/sophgo/Kconfig | 10 +++ .../dt-bindings/reset/sophgo,sg2042-reset.h | 88 +++++++++++++++++++ 6 files changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml create mode 100644 drivers/reset/sophgo/Kconfig create mode 100644 include/dt-bindings/reset/sophgo,sg2042-reset.h
base-commit: 0dd3ee31125508cd67f7e7172247f05b7fd1753a
Signature · 1 line
2.25.1
PATCH 1/4 dt-bindings: reset: sophgo: support SG2042
From: Chen Wang <[email protected]>
Add bindings for the reset generator on the SOPHGO SG2042 RISC-V SoC.
--- .../bindings/reset/sophgo,sg2042-reset.yaml | 35 ++++++++ .../dt-bindings/reset/sophgo,sg2042-reset.h | 88 +++++++++++++++++++ 2 files changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml create mode 100644 include/dt-bindings/reset/sophgo,sg2042-reset.h
Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml new file +35 -0
@@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/sophgo,sg2042-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 SoC Reset Controller + +maintainers: + - Chen Wang <[email protected]> + +properties: + compatible: + const: sophgo,sg2042-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + rstgen: reset-controller@c00 { + compatible = "sophgo,sg2042-reset"; + reg = <0xc00 0xc>; + #reset-cells = <1>; + };
include/dt-bindings/reset/sophgo,sg2042-reset.h new file +88 -0
88 lines not on this page · raw message
Signature · 1 line
2.25.1
Re: [PATCH 1/4] dt-bindings: reset: sophgo: support SG2042
Quoted 5 lines · Chen Wang
From: Chen Wang <[email protected]>
Add bindings for the reset generator on the SOPHGO SG2042 RISC-V SoC.
Signed-off-by Chen Wang <[email protected]>
...
include/dt-bindings/reset/sophgo,sg2042-reset.h line 42
Quoted 3 lines
include/dt-bindings/reset/sophgo,sg2042-reset.h new file +3
-0+#define RST_UART2 31 + +#define RST_UART3 32
No need for blank line above UART3. If there is going to be new version/resend, please fix it.
Anyway:
---
This is an automated instruction, just in case, because many review tags are being ignored. If you know the process, you can skip it (please do not feel offended by me posting it here - no bad intentions intended). If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions, under or above your Signed-off-by tag. Tag is "received", when provided in a message replied to you on the mailing list. Tools like b4 can help here. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for tags received on the version they apply.
https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577
Best regards,
Krzysztof
Re: [PATCH 1/4] dt-bindings: reset: sophgo: support SG2042
Quoted 5 lines · Krzysztof Kozlowski
Quoted 4 lines · Chen Wang
From: Chen Wang <[email protected]>
Add bindings for the reset generator on the SOPHGO SG2042 RISC-V SoC.
Quoted 8 lines
Quoted 1 line
Signed-off-by Chen Wang <[email protected]>...
include/dt-bindings/reset/sophgo,sg2042-reset.h line 42
Quoted 3 lines
include/dt-bindings/reset/sophgo,sg2042-reset.h new file +3
-0+#define RST_UART2 31 + +#define RST_UART3 32No need for blank line above UART3. If there is going to be new version/resend, please fix it.
Ok, let's wait a while for other review comments, then I will fix it in next version.
Quoted 25 lines
Anyway:
Reviewed-by Krzysztof Kozlowski <[email protected]>---
This is an automated instruction, just in case, because many review tags are being ignored. If you know the process, you can skip it (please do not feel offended by me posting it here - no bad intentions intended). If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions, under or above your Signed-off-by tag. Tag is "received", when provided in a message replied to you on the mailing list. Tools like b4 can help here. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for tags received on the version they apply.
https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577
Best regards,
Krzysztof
PATCH 2/4 reset: sophgo: add SG2042 reset generator driver
In reply to Chen WangFrom: Chen Wang <[email protected]>
Reuse reset-simple driver for the Sophgo SG2042 reset generator.
--- drivers/reset/Kconfig | 1 + drivers/reset/reset-simple.c | 2 ++ drivers/reset/sophgo/Kconfig | 10 ++++++++++ 3 files changed, 13 insertions(+) create mode 100644 drivers/reset/sophgo/Kconfig
drivers/reset/Kconfig +1 -0
@@ -318,6 +318,7 @@ config RESET_ZYNQ help This enables the reset controller driver for Xilinx Zynq SoCs. +source "drivers/reset/sophgo/Kconfig" source "drivers/reset/starfive/Kconfig" source "drivers/reset/sti/Kconfig" source "drivers/reset/hisilicon/Kconfig"
drivers/reset/reset-simple.c +2 -0
@@ -151,6 +151,8 @@ static const struct of_device_id reset_simple_dt_ids[] = { { .compatible = "snps,dw-high-reset" }, { .compatible = "snps,dw-low-reset", .data = &reset_simple_active_low }, + { .compatible = "sophgo,sg2042-reset", + .data = &reset_simple_active_low }, { /* sentinel */ }, };
drivers/reset/sophgo/Kconfig new file +10 -0
@@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config RESET_SOPHGO_SG2042 + bool "Sophgo SG2042 Reset Driver" + depends on ARCH_SOPHGO || COMPILE_TEST + select RESET_SIMPLE + default ARCH_SOPHGO + help + This enables the reset controller driver for the Sophgo SG2042 SoC. +
Signature · 1 line
2.25.1
PATCH 3/4 riscv: dts: add reset generator for Sophgo SG2042 SoC
In reply to Chen WangFrom: Chen Wang <[email protected]>
Add reset generator node to device tree for SG2042.
--- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)
arch/riscv/boot/dts/sophgo/sg2042.dtsi +8 -0
@@ -6,6 +6,8 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/reset/sophgo,sg2042-reset.h> + #include "sg2042-cpus.dtsi" / {
@@ -311,6 +313,12 @@ intc: interrupt-controller@7090000000 { riscv,ndev = <224>; }; + rstgen: reset-controller@7030013000 { + compatible = "sophgo,sg2042-reset"; + reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; + #reset-cells = <1>; + }; + uart0: serial@7040000000 { compatible = "snps,dw-apb-uart"; reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
Signature · 1 line
2.25.1
PATCH 4/4 riscv: dts: add resets property for uart node
In reply to Chen WangFrom: Chen Wang <[email protected]>
Add resets property for uart0 for completeness, although it is deasserted by default.
--- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/riscv/boot/dts/sophgo/sg2042.dtsi +1 -0
@@ -327,6 +327,7 @@ uart0: serial@7040000000 { clock-frequency = <500000000>; reg-shift = <2>; reg-io-width = <4>; + resets = <&rstgen RST_UART0>; status = "disabled"; }; };
Signature · 1 line
2.25.1