riscv: sophgo: add reset support for SG2042

From: Chen Wang <[email protected]>

From: Chen Wang <[email protected]>

This series adds reset controller support for Sophgo SG2042 using reset-simple driver.

Thanks,
Chen

---

Changes in v2:
This patch series is based on v6.8-rc1.
- fixed some minor formatting issues.
Note that if you need to pass dtb check, you need to apply a patch. This patch is missing in v6.8-rc1. For details, please see [2].

Changes in v1:
The patch series is based on v6.7. You can simply review or test the patches at the link [1].

---

Chen Wang (4):
dt-bindings: reset: sophgo: support SG2042
reset: sophgo: add SG2042 reset generator driver
riscv: dts: add reset generator for Sophgo SG2042 SoC
riscv: dts: add resets property for uart node

 .../bindings/reset/sophgo,sg2042-reset.yaml   | 35 ++++++++
 arch/riscv/boot/dts/sophgo/sg2042.dtsi        |  9 ++
 drivers/reset/Kconfig                         |  1 +
 drivers/reset/reset-simple.c                  |  2 +
 drivers/reset/sophgo/Kconfig                  | 10 +++
 .../dt-bindings/reset/sophgo,sg2042-reset.h   | 87 +++++++++++++++++++
 6 files changed, 144 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
 create mode 100644 drivers/reset/sophgo/Kconfig
 create mode 100644 include/dt-bindings/reset/sophgo,sg2042-reset.h

base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d

2.25.1

From: Chen Wang <[email protected]>

Add bindings for the reset generator on the SOPHGO SG2042 RISC-V SoC.

---
 .../bindings/reset/sophgo,sg2042-reset.yaml   | 35 ++++++++
 .../dt-bindings/reset/sophgo,sg2042-reset.h   | 87 +++++++++++++++++++
 2 files changed, 122 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
 create mode 100644 include/dt-bindings/reset/sophgo,sg2042-reset.h

new file mode 100644
index 000000000000..76e1931f0908
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/sophgo,sg2042-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 SoC Reset Controller
+
+maintainers:
+  - Chen Wang <[email protected]>
+
+properties:
+  compatible:
+    const: sophgo,sg2042-reset
+
+  reg:
+    maxItems: 1
+
+  "#reset-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    rstgen: reset-controller@c00 {
+        compatible = "sophgo,sg2042-reset";
+        reg = <0xc00 0xc>;
+        #reset-cells = <1>;
+    };

2.25.1

From: Chen Wang <[email protected]>

Reuse reset-simple driver for the Sophgo SG2042 reset generator.

---
 drivers/reset/Kconfig        |  1 +
 drivers/reset/reset-simple.c |  2 ++
 drivers/reset/sophgo/Kconfig | 10 ++++++++++
 3 files changed, 13 insertions(+)
 create mode 100644 drivers/reset/sophgo/Kconfig

index ccd59ddd7610..09ba59cc4bc5 100644
@@ -318,6 +318,7 @@ config RESET_ZYNQ
 	help
 	  This enables the reset controller driver for Xilinx Zynq SoCs.
 
+source "drivers/reset/sophgo/Kconfig"
 source "drivers/reset/starfive/Kconfig"
 source "drivers/reset/sti/Kconfig"
 source "drivers/reset/hisilicon/Kconfig"

index 818cabcc9fb7..276067839830 100644
@@ -151,6 +151,8 @@ static const struct of_device_id reset_simple_dt_ids[] = {
 	{ .compatible = "snps,dw-high-reset" },
 	{ .compatible = "snps,dw-low-reset",
 		.data = &reset_simple_active_low },
+	{ .compatible = "sophgo,sg2042-reset",
+		.data = &reset_simple_active_low },
 	{ /* sentinel */ },
 };
 

new file mode 100644
index 000000000000..9ad96e49e1dd
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config RESET_SOPHGO_SG2042
+	bool "Sophgo SG2042 Reset Driver"
+	depends on ARCH_SOPHGO || COMPILE_TEST
+	select RESET_SIMPLE
+	default ARCH_SOPHGO
+	help
+	  This enables the reset controller driver for the Sophgo SG2042 SoC.
+

2.25.1

Subject prefix should be "reset: simple: "

[...]

Ok.

hi，Philipp,

The purpose of my adding Kconfig is to consider that other socs under sophgo may not use RESET_SIMPLE. I'm worried that the coverage is too large when default y if ARCH_SOPHGO? What do you think?

Thanks,

Chen

If ARCH_SOPHGO coverage is considered too wide, it's not correct to make RESET_SOPHGO_SG2024 "default ARCH_SOPHGO" either, so there's no significant difference.

The question is whether you need it at all. Can SG2042 boot, possibly with reduced functionality, into a useful system without the reset controller? If so, maybe it is enough to rely on a defconfig to enable RESET_SIMPLE? Otherwise, reset-simple could be considered small enough to accept carrying it around for non-SG2042 SoCs by default, it can be disabled manually, after all.

regards
Philipp

From: Chen Wang <[email protected]>

Add reset generator node to device tree for SG2042.

---
 arch/riscv/boot/dts/sophgo/sg2042.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

index 93256540d078..f59081d4f0ee 100644
@@ -6,6 +6,8 @@
 /dts-v1/;
 #include <dt-bindings/interrupt-controller/irq.h>
 
+#include <dt-bindings/reset/sophgo,sg2042-reset.h>
+
 #include "sg2042-cpus.dtsi"
 
 / {

@@ -311,6 +313,12 @@ intc: interrupt-controller@7090000000 {
 			riscv,ndev = <224>;
 		};
 
+		rstgen: reset-controller@7030013000 {
+			compatible = "sophgo,sg2042-reset";
+			reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
+			#reset-cells = <1>;
+		};
+
 		uart0: serial@7040000000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x00000070 0x40000000 0x00000000 0x00001000>;

2.25.1

From: Chen Wang <[email protected]>

Add resets property for uart0 for completeness, although it is deasserted by default.

---
 arch/riscv/boot/dts/sophgo/sg2042.dtsi | 1 +
 1 file changed, 1 insertion(+)

index f59081d4f0ee..03266f216021 100644
@@ -327,6 +327,7 @@ uart0: serial@7040000000 {
 			clock-frequency = <500000000>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
+			resets = <&rstgen RST_UART0>;
 			status = "disabled";
 		};
 	};

2.25.1