hwrng: add hwrng support for Rockchip RK3568

PATCH Applied Daniel Golle 4 participants 8 messages Jul 30, 2024 – Aug 15, 2024

Subsystems (5)

Device tree bindings Crypto API Arm Rockchip Hardware random number generator core +1 more subsystems

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Daniel Golle

author maintainer

2024-07-30 16:08 UTC #0 lore raw

v9 cover hwrng: add hwrng support for Rockchip RK3568

Rockchip SoCs used to have a random number generator as part of their crypto device.

However newer Rockchip SoCs like the RK3568 have an independent True Random Number Generator device. This patchset adds a driver for it and enables it in the device tree for RK3568.

It turns out the HW RNG returns very low quality on RK3566, so while it is theoretically also present on that SoC, only enable it on RK3568 for now on which the quality expectations are met.

Tested on FriendlyARM NanoPi R5C.

v8 -> v9:
* Patch 1: revert to v7

* Patch 2: revert to v7, use 922 as quality

* Patch 3: drop new properties, but enable only in rk3568.dtsi

v7 -> v8:
* Patch 1: document new properties
- introduce 'rockchip,sample-count'
- require to specify 'quality' (0~1024)

* Patch 2:
- read sample-count and quality from DT

* Patch 3:
- disable hwrng in rk356x.dtsi, enable only in rk3568.dtsi
- set sample-count 1000 and quality 900 (87.9%) as before

v6 -> v7:
* Patch 1: unchanged

* Patch 2: bring back rk_rng_write_ctl()
- bring back rk_rng_write_ctl() with improved comment to describe the hardware.

* Patch 3: unchaned

v5 -> v6:
* Patch 1: unchanged

* Patch 2: get rid of #ifdef
- use if (IS_ENABLED(...)) { ... }instead of #ifdef inside functions
- use __maybe_unused for functions previously enclosed by #ifdef'ery

* Patch 3: unchanged

v4 -> v5:
* Patch 1: always use RK3568 name
- use full RK3568 name in patch description
- add RK3568 to title in binding

* Patch 2: full name and cosmetics
- also always mention RK3568 as there may be other RNG in other (future) Rockchip SoCs
- remove debug output on successful probe
- use MODULE_AUTHOR several times instead of single comma-separated

* Patch 3: unchanged

v3 -> v4:
* Patch 1: minor corrections
- fix Rokchip -> Rockchip typo
- change commit title as requested

* Patch 2: improved error handling and resource management
- Always use writel() instead of writel_relaxed()
- Use pm_runtime_resume_and_get
- Correctly return error code in rk_rng_read()
- Make use of devm_reset_control_array_get_exclusive
- Use devm_pm_runtime_enable and there by get rid of rk_rng_remove()

* Patch 3:
- Move node to conform with ordering by address

v2 -> v3: patch adopted by Daniel Golle
* Patch 1: address comments of Krzysztof Kozlowski, add MAINTAINERS
- improved description
- meaningful clock-names
- add entry in MAINTAINERS files

* Patch 2: numerous code-style improvements
- drop misleading rk_rng_write_ctl(), simplify I/O writes
- drop unused TRNG_RNG_DOUT_[1-7] macros
- handle error handling for pm_runtime_get_sync()
- use memcpy_fromio() instead of open coding for-loop
- some minor white-spaces fixes

* Patch 3:
- use clock-names as defined in dt-bindings

v1 -> v2:
* Patch 1: fix issues reported by Rob Herring and Krzysztof Kozlowski:
- Rename rockchip-rng.yaml into rockchip,rk3568-rng.yaml
- Fix binding title and description
- Fix compatible property
- Rename clocks and add the corresponding descriptions
- Drop reset-names
- Add a bus definition with #address-cells and #size-cells to the example.

* Patch 2: fix issue reported by kernel test robot <[email protected]>
- Do not read the random registers as big endian, looking at the RK3568 TRM this is actually not needed. This fixes a sparse warning.

* Patch 3: unchanged

Aurelien Jarno (3):
dt-bindings: rng: Add Rockchip RK3568 TRNG
hwrng: add hwrng driver for Rockchip RK3568 SoC
arm64: dts: rockchip: add DT entry for RNG to RK356x

 .../bindings/rng/rockchip,rk3568-rng.yaml     |  61 +++++
 MAINTAINERS                                   |   7 +
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      |   4 +
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  10 +
 drivers/char/hw_random/Kconfig                |  14 ++
 drivers/char/hw_random/Makefile               |   1 +
 drivers/char/hw_random/rockchip-rng.c         | 227 ++++++++++++++++++
 7 files changed, 324 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
 create mode 100644 drivers/char/hw_random/rockchip-rng.c

Signature · 1 line

2.45.2

Daniel Golle

author maintainer

2024-07-30 16:08 UTC #1 lore raw

PATCH v9 1/3 dt-bindings: rng: Add Rockchip RK3568 TRNG

From: Aurelien Jarno <[email protected]>

Add the True Random Number Generator on the Rockchip RK3568 SoC.

Signed-off-by Aurelien Jarno <[email protected]>

Signed-off-by Daniel Golle <[email protected]>

Reviewed-by Krzysztof Kozlowski <[email protected]>

---
 .../bindings/rng/rockchip,rk3568-rng.yaml     | 61 +++++++++++++++++++
 MAINTAINERS                                   |  6 ++
 2 files changed, 67 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml

Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml new file +61 -0

new file mode 100644
index 0000000000000..e0595814a6d98
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rng/rockchip,rk3568-rng.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3568 TRNG
+
+description: True Random Number Generator on Rockchip RK3568 SoC
+
+maintainers:
+  - Aurelien Jarno <[email protected]>
+  - Daniel Golle <[email protected]>
+
+properties:
+  compatible:
+    enum:
+      - rockchip,rk3568-rng
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: TRNG clock
+      - description: TRNG AHB clock
+
+  clock-names:
+    items:
+      - const: core
+      - const: ahb
+
+  resets:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/rk3568-cru.h>
+    bus {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      rng@fe388000 {
+        compatible = "rockchip,rk3568-rng";
+        reg = <0x0 0xfe388000 0x0 0x4000>;
+        clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
+        clock-names = "core", "ahb";
+        resets = <&cru SRST_TRNG_NS>;
+      };
+    };
+
+...

MAINTAINERS +6 -0

index 12b870712da4a..9b75626b54e16 100644
@@ -19722,6 +19722,12 @@ F:	Documentation/userspace-api/media/v4l/metafmt-rkisp1.rst
 F:	drivers/media/platform/rockchip/rkisp1
 F:	include/uapi/linux/rkisp1-config.h
 
+ROCKCHIP RK3568 RANDOM NUMBER GENERATOR SUPPORT
+M:	Daniel Golle <[email protected]>
+M:	Aurelien Jarno <[email protected]>
+S:	Maintained
+F:	Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
+
 ROCKCHIP RASTER 2D GRAPHIC ACCELERATION UNIT DRIVER
 M:	Jacob Chen <[email protected]>
 M:	Ezequiel Garcia <[email protected]>

Signature · 1 line

2.45.2

Daniel Golle

author maintainer

2024-07-30 16:11 UTC #2 lore raw

PATCH v9 2/3 hwrng: add hwrng driver for Rockchip RK3568 SoC

In reply to Daniel Golle

From: Aurelien Jarno <[email protected]>

Rockchip SoCs used to have a random number generator as part of their crypto device, and support for it has to be added to the corresponding driver. However newer Rockchip SoCs like the RK3568 have an independent True Random Number Generator device. This patch adds a driver for it, greatly inspired from the downstream driver.

The TRNG device does not seem to have a signal conditionner and the FIPS 140-2 test returns a lot of failures. They can be reduced by increasing RK_RNG_SAMPLE_CNT, in a tradeoff between quality and speed. This value has been adjusted to get ~90% of successes and the quality value has been set accordingly.

Signed-off-by Aurelien Jarno <[email protected]>

[[email protected]: code style fixes]

Signed-off-by Daniel Golle <[email protected]>

Acked-by Krzysztof Kozlowski <[email protected]>

---
 MAINTAINERS                           |   1 +
 drivers/char/hw_random/Kconfig        |  14 ++
 drivers/char/hw_random/Makefile       |   1 +
 drivers/char/hw_random/rockchip-rng.c | 227 ++++++++++++++++++++++++++
 4 files changed, 243 insertions(+)
 create mode 100644 drivers/char/hw_random/rockchip-rng.c

MAINTAINERS +1 -0

index 9b75626b54e16..369778c7ddcc4 100644
@@ -19727,6 +19727,7 @@ M:	Daniel Golle <[email protected]>
 M:	Aurelien Jarno <[email protected]>
 S:	Maintained
 F:	Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
+F:	drivers/char/hw_random/rockchip-rng.c
 
 ROCKCHIP RASTER 2D GRAPHIC ACCELERATION UNIT DRIVER
 M:	Jacob Chen <[email protected]>

drivers/char/hw_random/Kconfig +14 -0

index 01e2e1ef82cf9..4a339c18a3ccc 100644
@@ -572,6 +572,20 @@ config HW_RANDOM_JH7110
 	  To compile this driver as a module, choose M here.
 	  The module will be called jh7110-trng.
 
+config HW_RANDOM_ROCKCHIP
+	tristate "Rockchip True Random Number Generator"
+	depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST)
+	depends on HAS_IOMEM
+	default HW_RANDOM
+	help
+	  This driver provides kernel-side support for the True Random Number
+	  Generator hardware found on some Rockchip SoC like RK3566 or RK3568.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called rockchip-rng.
+
+	  If unsure, say Y.
+
 endif # HW_RANDOM
 
 config UML_RANDOM

drivers/char/hw_random/Makefile +1 -0

index 32549a1186dc5..01f012eab4400 100644
@@ -48,4 +48,5 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphera-trng.o
 obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
 obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
 obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
 obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o

drivers/char/hw_random/rockchip-rng.c new file +227 -0

227 lines not on this page · raw message

Signature · 1 line

2.45.2

Daniel Golle

author maintainer

2024-07-30 16:11 UTC #3 lore raw

PATCH v9 3/3 arm64: dts: rockchip: add DT entry for RNG to RK356x

In reply to Daniel Golle

From: Aurelien Jarno <[email protected]>

Include the just added Rockchip RNG driver for RK356x SoCs and enable it on RK3568.

Signed-off-by Aurelien Jarno <[email protected]>

Signed-off-by Daniel Golle <[email protected]>

---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi |  4 ++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 ++++++++++
 2 files changed, 14 insertions(+)

arch/arm64/boot/dts/rockchip/rk3568.dtsi +4 -0

index f1be76a54ceb0..2a6ca20e607fd 100644
@@ -257,6 +257,10 @@ power-domain@RK3568_PD_PIPE {
 	};
 };
 
+&rng {
+	status = "okay";
+};
+
 &usb_host0_xhci {
 	phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
 	phy-names = "usb2-phy", "usb3-phy";

arch/arm64/boot/dts/rockchip/rk356x.dtsi +10 -0

index 4690be841a1cd..d160a23fd4959 100644
@@ -1113,6 +1113,16 @@ sdhci: mmc@fe310000 {
 		status = "disabled";
 	};
 
+	rng: rng@fe388000 {
+		compatible = "rockchip,rk3568-rng";
+		reg = <0x0 0xfe388000 0x0 0x4000>;
+		clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
+		clock-names = "core", "ahb";
+		resets = <&cru SRST_TRNG_NS>;
+		reset-names = "reset";
+		status = "disabled";
+	};
+
 	i2s0_8ch: i2s@fe400000 {
 		compatible = "rockchip,rk3568-i2s-tdm";
 		reg = <0x0 0xfe400000 0x0 0x1000>;

Signature · 1 line

2.45.2

Rob Herring

maintainer

2024-08-13 14:17 UTC #4 lore raw

Re: [PATCH v9 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x

Quoted 33 lines · Daniel Golle

From: Aurelien Jarno <[email protected]>
Include the just added Rockchip RNG driver for RK356x SoCs and enable it on RK3568.
Signed-off-by Aurelien Jarno <[email protected]>
Signed-off-by Daniel Golle <[email protected]>
---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi |  4 ++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 ++++++++++
 2 files changed, 14 insertions(+)
arch/arm64/boot/dts/rockchip/rk3568.dtsi +4 -0
index f1be76a54ceb0..2a6ca20e607fd 100644
@@ -257,6 +257,10 @@ power-domain@RK3568_PD_PIPE {
        };
 };
 
+&rng {
+       status = "okay";
+};
+
 &usb_host0_xhci {
        phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
        phy-names = "usb2-phy", "usb3-phy";
arch/arm64/boot/dts/rockchip/rk356x.dtsi +0 -0
index 4690be841a1cd..d160a23fd4959 100644

arch/arm64/boot/dts/rockchip/rk356x.dtsi sdhci: mmc@fe310000 { · line 1122

Quoted 10 lines

arch/arm64/boot/dts/rockchip/rk356x.dtsi +7 -0

@@ -1113,6 +1113,16 @@ sdhci: mmc@fe310000 {
                status = "disabled";
        };
 
+       rng: rng@fe388000 {
+               compatible = "rockchip,rk3568-rng";
+               reg = <0x0 0xfe388000 0x0 0x4000>;
+               clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
+               clock-names = "core", "ahb";
+               resets = <&cru SRST_TRNG_NS>;
+               reset-names = "reset";

This adds a new warning:

rng@fe388000: 'reset-names' does not match any of the regexes: 'pinctrl-[0-9]+'

Heiko Stübner

maintainer

2024-08-15 16:26 UTC #5 lore raw

Re: [PATCH v9 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x

Am Dienstag, 13. August 2024, 16:17:05 CEST schrieb Rob Herring:

Quoted 47 lines · Daniel Golle

Quoted 33 lines
From: Aurelien Jarno <[email protected]>
Include the just added Rockchip RNG driver for RK356x SoCs and enable it on RK3568.
Signed-off-by Aurelien Jarno <[email protected]>
Signed-off-by Daniel Golle <[email protected]>
---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi |  4 ++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 ++++++++++
 2 files changed, 14 insertions(+)
arch/arm64/boot/dts/rockchip/rk3568.dtsi +4 -0
index f1be76a54ceb0..2a6ca20e607fd 100644
@@ -257,6 +257,10 @@ power-domain@RK3568_PD_PIPE {
        };
 };
 
+&rng {
+       status = "okay";
+};
+
 &usb_host0_xhci {
        phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
        phy-names = "usb2-phy", "usb3-phy";
arch/arm64/boot/dts/rockchip/rk356x.dtsi +0 -0
index 4690be841a1cd..d160a23fd4959 100644
arch/arm64/boot/dts/rockchip/rk356x.dtsi sdhci: mmc@fe310000 { · line 1122
Quoted 10 lines
arch/arm64/boot/dts/rockchip/rk356x.dtsi +7 -0
@@ -1113,6 +1113,16 @@ sdhci: mmc@fe310000 {
                status = "disabled";
        };
 
+       rng: rng@fe388000 {
+               compatible = "rockchip,rk3568-rng";
+               reg = <0x0 0xfe388000 0x0 0x4000>;
+               clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
+               clock-names = "core", "ahb";
+               resets = <&cru SRST_TRNG_NS>;
+               reset-names = "reset";
This adds a new warning:

Quoted 1 line

rng@fe388000: 'reset-names' does not match any of the regexes: 'pinctrl-[0-9]+'

I've created and sent a patch to remove the reset-names now.

Herbert Xu

maintainer

2024-08-10 06:24 UTC #6 lore raw

In reply to Daniel Golle

Quoted 117 lines · Daniel Golle

Rockchip SoCs used to have a random number generator as part of their crypto device.
However newer Rockchip SoCs like the RK3568 have an independent True Random Number Generator device. This patchset adds a driver for it and enables it in the device tree for RK3568.
It turns out the HW RNG returns very low quality on RK3566, so while it is theoretically also present on that SoC, only enable it on RK3568 for now on which the quality expectations are met.
Tested on FriendlyARM NanoPi R5C.
v8 -> v9:
* Patch 1: revert to v7
* Patch 2: revert to v7, use 922 as quality
* Patch 3: drop new properties, but enable only in rk3568.dtsi
v7 -> v8:
* Patch 1: document new properties
- introduce 'rockchip,sample-count'
- require to specify 'quality' (0~1024)
* Patch 2:
- read sample-count and quality from DT
* Patch 3:
- disable hwrng in rk356x.dtsi, enable only in rk3568.dtsi
- set sample-count 1000 and quality 900 (87.9%) as before
v6 -> v7:
* Patch 1: unchanged
* Patch 2: bring back rk_rng_write_ctl()
- bring back rk_rng_write_ctl() with improved comment to describe the hardware.
* Patch 3: unchaned
v5 -> v6:
* Patch 1: unchanged
* Patch 2: get rid of #ifdef
- use if (IS_ENABLED(...)) { ... }instead of #ifdef inside functions
- use __maybe_unused for functions previously enclosed by #ifdef'ery
* Patch 3: unchanged
v4 -> v5:
* Patch 1: always use RK3568 name
- use full RK3568 name in patch description
- add RK3568 to title in binding
* Patch 2: full name and cosmetics
- also always mention RK3568 as there may be other RNG in other (future) Rockchip SoCs
- remove debug output on successful probe
- use MODULE_AUTHOR several times instead of single comma-separated
* Patch 3: unchanged
v3 -> v4:
* Patch 1: minor corrections
- fix Rokchip -> Rockchip typo
- change commit title as requested
* Patch 2: improved error handling and resource management
- Always use writel() instead of writel_relaxed()
- Use pm_runtime_resume_and_get
- Correctly return error code in rk_rng_read()
- Make use of devm_reset_control_array_get_exclusive
- Use devm_pm_runtime_enable and there by get rid of rk_rng_remove()
* Patch 3:
- Move node to conform with ordering by address
v2 -> v3: patch adopted by Daniel Golle
* Patch 1: address comments of Krzysztof Kozlowski, add MAINTAINERS
- improved description
- meaningful clock-names
- add entry in MAINTAINERS files
* Patch 2: numerous code-style improvements
- drop misleading rk_rng_write_ctl(), simplify I/O writes
- drop unused TRNG_RNG_DOUT_[1-7] macros
- handle error handling for pm_runtime_get_sync()
- use memcpy_fromio() instead of open coding for-loop
- some minor white-spaces fixes
* Patch 3:
- use clock-names as defined in dt-bindings
v1 -> v2:
* Patch 1: fix issues reported by Rob Herring and Krzysztof Kozlowski:
- Rename rockchip-rng.yaml into rockchip,rk3568-rng.yaml
- Fix binding title and description
- Fix compatible property
- Rename clocks and add the corresponding descriptions
- Drop reset-names
- Add a bus definition with #address-cells and #size-cells to the example.
* Patch 2: fix issue reported by kernel test robot <[email protected]>
- Do not read the random registers as big endian, looking at the RK3568 TRM this is actually not needed. This fixes a sparse warning.
* Patch 3: unchanged
Aurelien Jarno (3):
dt-bindings: rng: Add Rockchip RK3568 TRNG
hwrng: add hwrng driver for Rockchip RK3568 SoC
arm64: dts: rockchip: add DT entry for RNG to RK356x

Quoted 13 lines

 .../bindings/rng/rockchip,rk3568-rng.yaml     |  61 +++++
 MAINTAINERS                                   |   7 +
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      |   4 +
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  10 +
 drivers/char/hw_random/Kconfig                |  14 ++
 drivers/char/hw_random/Makefile               |   1 +
 drivers/char/hw_random/rockchip-rng.c         | 227 ++++++++++++++++++
 7 files changed, 324 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
 create mode 100644 drivers/char/hw_random/rockchip-rng.c

Signature · 1 line

2.45.2

Patches 1-2 applied. Thanks.

Signature · 3 lines

Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

Heiko Stuebner

maintainer Applied

2024-08-10 19:16 UTC #7 lore raw

Re: (subset) [PATCH v9 0/3] hwrng: add hwrng support for Rockchip RK3568

In reply to Daniel Golle

Quoted 8 lines · Daniel Golle

Rockchip SoCs used to have a random number generator as part of their crypto device.
However newer Rockchip SoCs like the RK3568 have an independent True Random Number Generator device. This patchset adds a driver for it and enables it in the device tree for RK3568.
[...]

Applied, thanks!

[3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x

      commit: afeccc4084963aaa932931b734c8def55613c483

Best regards,

Signature · 1 line

Heiko Stuebner <[email protected]>