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hwrng: add hwrng support for Rockchip RK3568

PATCH Superseded Daniel Golle 3 participants 8 messages Jul 21, 2024

Subsystems (5)

v8 of 9 Superseded Latest is v9 →

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Daniel Golle

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#0 lore raw

v8 cover hwrng: add hwrng support for Rockchip RK3568

Rockchip SoCs used to have a random number generator as part of their crypto device.

However newer Rockchip SoCs like the RK3568 have an independent True Random Number Generator device. This patchset adds a driver for it and enables it in the device tree for RTK3568.

Tested on FriendlyARM NanoPi R5C.

v7 -> v8:
* Patch 1: document new properties
- introduce 'rockchip,sample-count'
- require to specify 'quality' (0~1024)

* Patch 2:
- read sample-count and quality from DT

* Patch 3:
- disable hwrng in rk356x.dtsi, enable only in rk3568.dtsi
- set sample-count 1000 and quality 900 (87.9%) as before

v6 -> v7:
* Patch 1: unchanged

* Patch 2: bring back rk_rng_write_ctl()
- bring back rk_rng_write_ctl() with improved comment to describe the hardware.

* Patch 3: unchaned

v5 -> v6:
* Patch 1: unchanged

* Patch 2: get rid of #ifdef
- use if (IS_ENABLED(...)) { ... }instead of #ifdef inside functions
- use __maybe_unused for functions previously enclosed by #ifdef'ery

* Patch 3: unchanged

v4 -> v5:
* Patch 1: always use RK3568 name
- use full RK3568 name in patch description
- add RK3568 to title in binding

* Patch 2: full name and cosmetics
- also always mention RK3568 as there may be other RNG in other (future) Rockchip SoCs
- remove debug output on successful probe
- use MODULE_AUTHOR several times instead of single comma-separated

* Patch 3: unchanged

v3 -> v4:
* Patch 1: minor corrections
- fix Rokchip -> Rockchip typo
- change commit title as requested

* Patch 2: improved error handling and resource management
- Always use writel() instead of writel_relaxed()
- Use pm_runtime_resume_and_get
- Correctly return error code in rk_rng_read()
- Make use of devm_reset_control_array_get_exclusive
- Use devm_pm_runtime_enable and there by get rid of rk_rng_remove()

* Patch 3:
- Move node to conform with ordering by address

v2 -> v3: patch adopted by Daniel Golle
* Patch 1: address comments of Krzysztof Kozlowski, add MAINTAINERS
- improved description
- meaningful clock-names
- add entry in MAINTAINERS files

* Patch 2: numerous code-style improvements
- drop misleading rk_rng_write_ctl(), simplify I/O writes
- drop unused TRNG_RNG_DOUT_[1-7] macros
- handle error handling for pm_runtime_get_sync()
- use memcpy_fromio() instead of open coding for-loop
- some minor white-spaces fixes

* Patch 3:
- use clock-names as defined in dt-bindings

v1 -> v2:
* Patch 1: fix issues reported by Rob Herring and Krzysztof Kozlowski:
- Rename rockchip-rng.yaml into rockchip,rk3568-rng.yaml
- Fix binding title and description
- Fix compatible property
- Rename clocks and add the corresponding descriptions
- Drop reset-names
- Add a bus definition with #address-cells and #size-cells to the example.

* Patch 2: fix issue reported by kernel test robot <[email protected]>
- Do not read the random registers as big endian, looking at the RK3568 TRM this is actually not needed. This fixes a sparse warning.

* Patch 3: unchanged

Aurelien Jarno (3):
dt-bindings: rng: Add Rockchip RK3568 TRNG
hwrng: add hwrng driver for Rockchip RK3568 SoC
arm64: dts: rockchip: add DT entry for RNG to RK356x

 .../bindings/rng/rockchip,rk3568-rng.yaml     |  82 +++++++
 MAINTAINERS                                   |   7 +
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      |   7 +
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  10 +
 drivers/char/hw_random/Kconfig                |  14 ++
 drivers/char/hw_random/Makefile               |   1 +
 drivers/char/hw_random/rockchip-rng.c         | 230 ++++++++++++++++++
 7 files changed, 351 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
 create mode 100644 drivers/char/hw_random/rockchip-rng.c
Signature · 1 line
2.45.2
author maintainer
#1 lore raw

PATCH v8 1/3 dt-bindings: rng: Add Rockchip RK3568 TRNG

From: Aurelien Jarno <[email protected]>

Add the True Random Number Generator on the Rockchip RK3568 SoC.

---
 .../bindings/rng/rockchip,rk3568-rng.yaml     | 82 +++++++++++++++++++
 MAINTAINERS                                   |  6 ++
 2 files changed, 88 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml new file +82 -0
new file mode 100644
index 000000000000..383a39e60ad8
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rng/rockchip,rk3568-rng.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3568 TRNG
+
+description: True Random Number Generator on Rockchip RK3568 SoC
+
+maintainers:
+  - Aurelien Jarno <[email protected]>
+  - Daniel Golle <[email protected]>
+
+properties:
+  compatible:
+    enum:
+      - rockchip,rk3568-rng
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: TRNG clock
+      - description: TRNG AHB clock
+
+  clock-names:
+    items:
+      - const: core
+      - const: ahb
+
+  quality:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+    description:
+      Estimated number of bits of true entropy per 1024 bits read from the rng.
+      Defaults to zero which causes the kernel's default quality to be used
+      instead.  Note that the default quality is usually zero which disables
+      using this rng to automatically fill the kernel's entropy pool.
+
+  rockchip,sample-count:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 1000
+    description:
+      Bits to skip on TRNG osc ring output before collection.
+      The value is a tradeoff between speed and quality, the higher the slower
+      and the better quality.
+
+  resets:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - quality
+  - resets
+  - rockchip,sample-count
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/rk3568-cru.h>
+    bus {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      rng@fe388000 {
+        compatible = "rockchip,rk3568-rng";
+        reg = <0x0 0xfe388000 0x0 0x4000>;
+        clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
+        clock-names = "core", "ahb";
+        quality = <900>;
+        resets = <&cru SRST_TRNG_NS>;
+        rockchip,sample-count = <1000>;
+      };
+    };
+
+...
MAINTAINERS +6 -0
index 61053a8c625e..41aecf9736c9 100644
@@ -19707,6 +19707,12 @@ F:	Documentation/userspace-api/media/v4l/metafmt-rkisp1.rst
 F:	drivers/media/platform/rockchip/rkisp1
 F:	include/uapi/linux/rkisp1-config.h
 
+ROCKCHIP RK3568 RANDOM NUMBER GENERATOR SUPPORT
+M:	Daniel Golle <[email protected]>
+M:	Aurelien Jarno <[email protected]>
+S:	Maintained
+F:	Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
+
 ROCKCHIP RASTER 2D GRAPHIC ACCELERATION UNIT DRIVER
 M:	Jacob Chen <[email protected]>
 M:	Ezequiel Garcia <[email protected]>
Signature · 1 line
2.45.2
author maintainer
#2 lore raw

PATCH v8 2/3 hwrng: add hwrng driver for Rockchip RK3568 SoC

In reply to Daniel Golle

From: Aurelien Jarno <[email protected]>

Rockchip SoCs used to have a random number generator as part of their crypto device, and support for it has to be added to the corresponding driver. However newer Rockchip SoCs like the RK3568 have an independent True Random Number Generator device. This patch adds a driver for it, greatly inspired from the downstream driver.

The TRNG device does not seem to have a signal conditionner and the FIPS 140-2 test returns a lot of failures. They can be reduced by increasing rockchip,sample-count in DT, in a tradeoff between quality and speed.

---
 MAINTAINERS                           |   1 +
 drivers/char/hw_random/Kconfig        |  14 ++
 drivers/char/hw_random/Makefile       |   1 +
 drivers/char/hw_random/rockchip-rng.c | 230 ++++++++++++++++++++++++++
 4 files changed, 246 insertions(+)
 create mode 100644 drivers/char/hw_random/rockchip-rng.c
MAINTAINERS +1 -0
index 41aecf9736c9..64b21b434acd 100644
@@ -19712,6 +19712,7 @@ M:	Daniel Golle <[email protected]>
 M:	Aurelien Jarno <[email protected]>
 S:	Maintained
 F:	Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
+F:	drivers/char/hw_random/rockchip-rng.c
 
 ROCKCHIP RASTER 2D GRAPHIC ACCELERATION UNIT DRIVER
 M:	Jacob Chen <[email protected]>
drivers/char/hw_random/Kconfig +14 -0
index 01e2e1ef82cf..4a339c18a3cc 100644
@@ -572,6 +572,20 @@ config HW_RANDOM_JH7110
 	  To compile this driver as a module, choose M here.
 	  The module will be called jh7110-trng.
 
+config HW_RANDOM_ROCKCHIP
+	tristate "Rockchip True Random Number Generator"
+	depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST)
+	depends on HAS_IOMEM
+	default HW_RANDOM
+	help
+	  This driver provides kernel-side support for the True Random Number
+	  Generator hardware found on some Rockchip SoC like RK3566 or RK3568.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called rockchip-rng.
+
+	  If unsure, say Y.
+
 endif # HW_RANDOM
 
 config UML_RANDOM
drivers/char/hw_random/Makefile +1 -0
index 32549a1186dc..01f012eab440 100644
@@ -48,4 +48,5 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphera-trng.o
 obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
 obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
 obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
 obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o
drivers/char/hw_random/rockchip-rng.c new file +230 -0

230 lines not on this page · raw message

Signature · 1 line
2.45.2
author maintainer
#3 lore raw

PATCH v8 3/3 arm64: dts: rockchip: add DT entry for RNG to RK356x

In reply to Daniel Golle

From: Aurelien Jarno <[email protected]>

Enable the just added Rockchip RNG driver for RK356x SoCs.

---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi |  7 +++++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 ++++++++++
 2 files changed, 17 insertions(+)
arch/arm64/boot/dts/rockchip/rk3568.dtsi +7 -0
index f1be76a54ceb..b9c6b2dc87fa 100644
@@ -257,6 +257,13 @@ power-domain@RK3568_PD_PIPE {
 	};
 };
 
+&rng {
+	rockchip,sample-count = <1000>;
+	quality = <900>;
+
+	status = "okay";
+};
+
 &usb_host0_xhci {
 	phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
 	phy-names = "usb2-phy", "usb3-phy";
arch/arm64/boot/dts/rockchip/rk356x.dtsi +10 -0
index 4690be841a1c..d160a23fd495 100644
@@ -1113,6 +1113,16 @@ sdhci: mmc@fe310000 {
 		status = "disabled";
 	};
 
+	rng: rng@fe388000 {
+		compatible = "rockchip,rk3568-rng";
+		reg = <0x0 0xfe388000 0x0 0x4000>;
+		clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
+		clock-names = "core", "ahb";
+		resets = <&cru SRST_TRNG_NS>;
+		reset-names = "reset";
+		status = "disabled";
+	};
+
 	i2s0_8ch: i2s@fe400000 {
 		compatible = "rockchip,rk3568-i2s-tdm";
 		reg = <0x0 0xfe400000 0x0 0x1000>;
Signature · 1 line
2.45.2
#4 lore raw

Re: [PATCH v8 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x

Quoted 16 lines · Daniel Golle

From: Aurelien Jarno <[email protected]>

Enable the just added Rockchip RNG driver for RK356x SoCs.

---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi |  7 +++++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 ++++++++++
 2 files changed, 17 insertions(+)
arch/arm64/boot/dts/rockchip/rk3568.dtsi +0 -0
index f1be76a54ceb..b9c6b2dc87fa 100644

arch/arm64/boot/dts/rockchip/rk3568.dtsi power-domain@RK3568_PD_PIPE { · line 262

Quoted 6 lines
arch/arm64/boot/dts/rockchip/rk3568.dtsi +3 -0
@@ -257,6 +257,13 @@ power-domain@RK3568_PD_PIPE {
 	};
 };
 
+&rng {
+	rockchip,sample-count = <1000>;
+	quality = <900>;

As I already wrote you for v7, quality is out of 1024, not 1000, so this won't hit 90% as you intend.

But also, I think putting this in the DT is a mistake. Other drivers don't generally do this, and if the hardware is actually the same piece to piece (it is...), then there's not per-manufactured unit tweaking needed. So keep this in the actual driver C like other drivers.

Jason

#5 lore raw

Re: [PATCH v8 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x

Hello all,

Quoted 27 lines · Jason A. Donenfeld
Quoted 16 lines · Daniel Golle

From: Aurelien Jarno <[email protected]>

Enable the just added Rockchip RNG driver for RK356x SoCs.

---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi |  7 +++++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 ++++++++++
 2 files changed, 17 insertions(+)
arch/arm64/boot/dts/rockchip/rk3568.dtsi +0 -0
index f1be76a54ceb..b9c6b2dc87fa 100644

arch/arm64/boot/dts/rockchip/rk3568.dtsi power-domain@RK3568_PD_PIPE { · line 262

Quoted 6 lines
arch/arm64/boot/dts/rockchip/rk3568.dtsi +3 -0
@@ -257,6 +257,13 @@ power-domain@RK3568_PD_PIPE {
 	};
 };
 
+&rng {
+	rockchip,sample-count = <1000>;
+	quality = <900>;

As I already wrote you for v7, quality is out of 1024, not 1000, so this won't hit 90% as you intend.

Quoted 4 lines

But also, I think putting this in the DT is a mistake. Other drivers don't generally do this, and if the hardware is actually the same piece to piece (it is...), then there's not per-manufactured unit tweaking needed. So keep this in the actual driver C like other drivers.

Actually, if we find out that some samples of RK3568 have HWRNG that performs poorly, we'll be able to regrettably conclude that this driver cannot be used at all. As we remember, RK3566 has been already proven to have inconsistent HRWNG that may perform poorly, which basically disqualifies the RK3566 from using this driver.

Thus, I agree that the per-SoC-variant parameters should be moved to the driver code in the final version. However, this is still a development version that has the parameters in the DT specifically to allow easier testing of the different parameter values.

author maintainer
#6 lore raw

Re: [PATCH v8 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x

In reply to Jason A. Donenfeld
Quoted 20 lines · Jason A. Donenfeld
Quoted 19 lines · Daniel Golle

From: Aurelien Jarno <[email protected]>

Enable the just added Rockchip RNG driver for RK356x SoCs.

---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi |  7 +++++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 ++++++++++
 2 files changed, 17 insertions(+)
arch/arm64/boot/dts/rockchip/rk3568.dtsi +0 -0
index f1be76a54ceb..b9c6b2dc87fa 100644
@@ -257,6 +257,13 @@ power-domain@RK3568_PD_PIPE {
 	};
 };
 
Quoted 6 lines

arch/arm64/boot/dts/rockchip/rk3568.dtsi power-domain@RK3568_PD_PIPE { · line 262

Quoted 3 lines
arch/arm64/boot/dts/rockchip/rk3568.dtsi +3 -0
+&rng {
+	rockchip,sample-count = <1000>;
+	quality = <900>;

As I already wrote you for v7, quality is out of 1024, not 1000, so this won't hit 90% as you intend.

It's not actually 90%. Around 125 out of 1000 test runs are failing on the R5C boards I got here, so that makes it 87.5% which is pretty close to the 87.9% of the 900/1024 figure there, hence I kept it 900 despite your comment.

Quoted 5 lines

But also, I think putting this in the DT is a mistake. Other drivers don't generally do this, and if the hardware is actually the same piece to piece (it is...), then there's not per-manufactured unit tweaking needed. So keep this in the actual driver C like other drivers.

So quality should be assigned using the DT compatible, right? And if needed we should have several of them, one for each SoC (if testing now turns out to show that the results are specific for the SoC rather than for the board).

#7 lore raw

Re: [PATCH v8 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x

Quoted 29 lines · Daniel Golle
Quoted 20 lines · Jason A. Donenfeld
Quoted 19 lines · Daniel Golle

From: Aurelien Jarno <[email protected]>

Enable the just added Rockchip RNG driver for RK356x SoCs.

---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi |  7 +++++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 ++++++++++
 2 files changed, 17 insertions(+)
arch/arm64/boot/dts/rockchip/rk3568.dtsi +0 -0
index f1be76a54ceb..b9c6b2dc87fa 100644
@@ -257,6 +257,13 @@ power-domain@RK3568_PD_PIPE {
    };
 };
 
Quoted 6 lines

arch/arm64/boot/dts/rockchip/rk3568.dtsi power-domain@RK3568_PD_PIPE { · line 262

Quoted 3 lines
arch/arm64/boot/dts/rockchip/rk3568.dtsi +3 -0
+&rng {
+   rockchip,sample-count = <1000>;
+   quality = <900>;

As I already wrote you for v7, quality is out of 1024, not 1000, so this won't hit 90% as you intend.

Quoted 4 lines

It's not actually 90%. Around 125 out of 1000 test runs are failing on the R5C boards I got here, so that makes it 87.5% which is pretty close to the 87.9% of the 900/1024 figure there, hence I kept it 900 despite your comment.

Just do 922?

Quoted 11 lines
Quoted 6 lines

But also, I think putting this in the DT is a mistake. Other drivers don't generally do this, and if the hardware is actually the same piece to piece (it is...), then there's not per-manufactured unit tweaking needed. So keep this in the actual driver C like other drivers.

So quality should be assigned using the DT compatible, right? And if needed we should have several of them, one for each SoC (if testing now turns out to show that the results are specific for the SoC rather than for the board).

No, do it in the C. If you don't have evidence of such crazy complexity and diversity, don't overengineer for it. Nothing else does this in the DT.