AT91 SAMA7 SoC Clock Adjustments

PATCH Superseded [email protected] 2 participants 7 messages May 6, 2025 – May 12, 2025

Subsystems (3)

Device tree bindings Common clk Arm/Microchip (AT91) SoC support

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[email protected]

author

2025-05-06 20:05 UTC #0 lore raw

v3 cover AT91 SAMA7 SoC Clock Adjustments

From: Ryan Wanner <[email protected]>

This set has clock system adjustments for the AT91 clock system for sama7 SoC family.

The first is to adjust the slow clock driver to account for the updated DT node-naming for clocks and xtals and ensuring the driver is still backwards compatible.

The second and third are adding a missing clk_hw struct that are not added into parent_data struct causing a incorrect parent for main_osc for both sama7d65 and sama7g54 SoCs.

The last patch updates the device tree phandle formatting for the sama7g54 SoC.

Changes v1 -> v2:
- Add clk_hw struct to parent_data adjustment for the sama7g5.c driver.
- Add correction to sama7g54 dtsi main xtal phandles.

Changes v2 -> v3:
- Removed the empty line after the fixes tag.
- Correct commit messages to better explain the issue that this is fixing.
- Initialize parent_data index to 0.

Ryan Wanner (4):
clk: at91: sckc: Fix parent_data struct for slow osc
clk: at91: sama7d65: Add missing clk_hw to parent_data
clk: at91: sama7g5: Add missing clk_hw to parent_data
ARM: dts: microchip: sama7g5: Adjust clock xtal phandle

 arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 18 ++++++++----------
 arch/arm/boot/dts/microchip/sama7g5.dtsi       |  4 ++--
 drivers/clk/at91/sama7d65.c                    |  3 ++-
 drivers/clk/at91/sama7g5.c                     |  3 ++-
 drivers/clk/at91/sckc.c                        | 12 ++++++------
 5 files changed, 20 insertions(+), 20 deletions(-)

Signature · 1 line

2.43.0

[email protected]

author

2025-05-06 20:05 UTC #1 lore raw

PATCH v3 1/4 clk: at91: sckc: Fix parent_data struct for slow osc

From: Ryan Wanner <[email protected]>

The slow xtal is not described correctly as a parent, the driver looks for a "slow_xtal" string which is incorrect and will not work with the new formating of xtals.

To avoid this and keep this driver backwards compatible the parent_data.fw_name is replaced with parent_data.name and the original parent_data.name is replaced with parent_data.index. Using the index is safe due to the driver requiring only 1 xtal.

Fixes 8aa1db9ccee0e ("clk: at91: sckc: switch to parent_data/parent_hw")

Signed-off-by Ryan Wanner <[email protected]>

---
 drivers/clk/at91/sckc.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

drivers/clk/at91/sckc.c +6 -6

index 021d1b412af4..952a805b6f7e 100644
@@ -374,7 +374,7 @@ static void __init at91sam9x5_sckc_register(struct device_node *np,
 	const char *xtal_name;
 	struct clk_hw *slow_rc, *slow_osc, *slowck;
 	static struct clk_parent_data parent_data = {
-		.name = "slow_xtal",
+		.index = 0,
 	};
 	const struct clk_hw *parent_hws[2];
 	bool bypass;

@@ -407,7 +407,7 @@ static void __init at91sam9x5_sckc_register(struct device_node *np,
 	if (!xtal_name)
 		goto unregister_slow_rc;
 
-	parent_data.fw_name = xtal_name;
+	parent_data.name = xtal_name;
 
 	slow_osc = at91_clk_register_slow_osc(regbase, "slow_osc",
 					      &parent_data, 1200000, bypass, bits);

@@ -476,7 +476,7 @@ static void __init of_sam9x60_sckc_setup(struct device_node *np)
 	const char *xtal_name;
 	const struct clk_hw *parent_hws[2];
 	static struct clk_parent_data parent_data = {
-		.name = "slow_xtal",
+		.index = 0,
 	};
 	bool bypass;
 	int ret;

@@ -494,7 +494,7 @@ static void __init of_sam9x60_sckc_setup(struct device_node *np)
 	if (!xtal_name)
 		goto unregister_slow_rc;
 
-	parent_data.fw_name = xtal_name;
+	parent_data.name = xtal_name;
 	bypass = of_property_read_bool(np, "atmel,osc-bypass");
 	slow_osc = at91_clk_register_slow_osc(regbase, "slow_osc",
 					      &parent_data, 5000000, bypass,

@@ -592,7 +592,7 @@ static void __init of_sama5d4_sckc_setup(struct device_node *np)
 	const char *xtal_name;
 	const struct clk_hw *parent_hws[2];
 	static struct clk_parent_data parent_data = {
-		.name = "slow_xtal",
+		.index = 0,
 	};
 	int ret;

@@ -609,7 +609,7 @@ static void __init of_sama5d4_sckc_setup(struct device_node *np)
 	xtal_name = of_clk_get_parent_name(np, 0);
 	if (!xtal_name)
 		goto unregister_slow_rc;
-	parent_data.fw_name = xtal_name;
+	parent_data.name = xtal_name;
 
 	osc = kzalloc(sizeof(*osc), GFP_KERNEL);
 	if (!osc)

Signature · 1 line

2.43.0

[email protected]

author

2025-05-06 20:05 UTC #2 lore raw

PATCH v3 2/4 clk: at91: sama7d65: Add missing clk_hw to parent_data

In reply to [email protected]

From: Ryan Wanner <[email protected]>

The main_xtal clk_hw struct is not passed into parent_data.hw causing the main_osc to not have a parent causing a corrupted clock tree. Passing the main_xtal struct into the parent_data struct will ensure the correct parent structure for main_osc and a correct clock tree.

Signed-off-by Ryan Wanner <[email protected]>

---
 drivers/clk/at91/sama7d65.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

drivers/clk/at91/sama7d65.c +2 -1

index a5d40df8b2f2..1e9d3c393883 100644
@@ -1100,7 +1100,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
 	struct regmap *regmap;
 	struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw;
 	struct clk_hw *td_slck_hw, *md_slck_hw;
-	static struct clk_parent_data parent_data;
+	static struct clk_parent_data parent_data = {0};
 	struct clk_hw *parent_hws[10];
 	bool bypass;
 	int i, j;

@@ -1138,6 +1138,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
 
 	parent_data.name = main_xtal_name;
 	parent_data.fw_name = main_xtal_name;
+	parent_data.hw = main_xtal_hw;
 	main_osc_hw = at91_clk_register_main_osc(regmap, "main_osc", NULL,
 						 &parent_data, bypass);
 	if (IS_ERR(main_osc_hw))

Signature · 1 line

2.43.0

Claudiu Beznea

maintainer

2025-05-12 14:47 UTC #3 lore raw

Re: [PATCH v3 2/4] clk: at91: sama7d65: Add missing clk_hw to parent_data

Hi, Ryan,

Quoted 27 lines · On 06.05.2025 23:04, [email protected] wrote:

From: Ryan Wanner <[email protected]>
The main_xtal clk_hw struct is not passed into parent_data.hw causing the main_osc to not have a parent causing a corrupted clock tree. Passing the main_xtal struct into the parent_data struct will ensure the correct parent structure for main_osc and a correct clock tree.
Signed-off-by Ryan Wanner <[email protected]>
---
 drivers/clk/at91/sama7d65.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/clk/at91/sama7d65.c +1 -1
index a5d40df8b2f2..1e9d3c393883 100644
@@ -1100,7 +1100,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
 	struct regmap *regmap;
 	struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw;
 	struct clk_hw *td_slck_hw, *md_slck_hw;
-	static struct clk_parent_data parent_data;
+	static struct clk_parent_data parent_data = {0};
 	struct clk_hw *parent_hws[10];
 	bool bypass;
 	int i, j;

drivers/clk/at91/sama7d65.c static void __init sama7d65_pmc_setup(struct device_node *np) · line 1141

Quoted 4 lines

drivers/clk/at91/sama7d65.c +1 -0

@@ -1138,6 +1138,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
 
 	parent_data.name = main_xtal_name;
 	parent_data.fw_name = main_xtal_name;
+	parent_data.hw = main_xtal_hw;

Is this line still needed with the initialization of parent data above:

	static struct clk_parent_data parent_data = {0};

Quoted 3 lines

drivers/clk/at91/sama7d65.c +0 -0

 	main_osc_hw = at91_clk_register_main_osc(regmap, "main_osc", NULL,
 						 &parent_data, bypass);
 	if (IS_ERR(main_osc_hw))

[email protected]

author

2025-05-12 19:38 UTC #4 lore raw

Re: [PATCH v3 2/4] clk: at91: sama7d65: Add missing clk_hw to parent_data

Hi Claudiu,

Quoted 33 lines · Claudiu Beznea

EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
Hi, Ryan,
Quoted 28 lines · On 06.05.2025 23:04, [email protected] wrote:
From: Ryan Wanner <[email protected]>
The main_xtal clk_hw struct is not passed into parent_data.hw causing the main_osc to not have a parent causing a corrupted clock tree. Passing the main_xtal struct into the parent_data struct will ensure the correct parent structure for main_osc and a correct clock tree.
Signed-off-by Ryan Wanner <[email protected]>
---
 drivers/clk/at91/sama7d65.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/clk/at91/sama7d65.c +1 -1
index a5d40df8b2f2..1e9d3c393883 100644
@@ -1100,7 +1100,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
      struct regmap *regmap;
      struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw;
      struct clk_hw *td_slck_hw, *md_slck_hw;
-     static struct clk_parent_data parent_data;
+     static struct clk_parent_data parent_data = {0};
      struct clk_hw *parent_hws[10];
      bool bypass;
      int i, j;
@@ -1138,6 +1138,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
 

Quoted 5 lines

drivers/clk/at91/sama7d65.c static void __init sama7d65_pmc_setup(struct device_node *np) · line 1141
Quoted 3 lines
drivers/clk/at91/sama7d65.c +1 -0
      parent_data.name = main_xtal_name;
      parent_data.fw_name = main_xtal_name;
+     parent_data.hw = main_xtal_hw;
Is this line still needed with the initialization of parent data above:

Yes it is still needed because the clk_hw struct still needs to be passed into the parent_data struct. If not the wrong parent will be set.

Quoted 7 lines

        static struct clk_parent_data parent_data = {0};

Quoted 3 lines

drivers/clk/at91/sama7d65.c +0 -0

      main_osc_hw = at91_clk_register_main_osc(regmap, "main_osc", NULL,
                                               &parent_data, bypass);
      if (IS_ERR(main_osc_hw))

[email protected]

author

2025-05-06 20:05 UTC #5 lore raw

PATCH v3 3/4 clk: at91: sama7g5: Add missing clk_hw to parent_data

In reply to [email protected]

From: Ryan Wanner <[email protected]>

The main_xtal clk_hw struct is not passed into parent_data.hw causing the main_osc to not have a parent and corrupting the clock tree. Passing the main_xtal struct into the parent_data struct will ensure the correct parent structure.

Signed-off-by Ryan Wanner <[email protected]>

---
 drivers/clk/at91/sama7g5.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

drivers/clk/at91/sama7g5.c +2 -1

index 8385badc1c70..b4eefca0b6d5 100644
@@ -979,7 +979,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
 	struct regmap *regmap;
 	struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw;
 	struct clk_hw *td_slck_hw, *md_slck_hw;
-	static struct clk_parent_data parent_data;
+	static struct clk_parent_data parent_data = {0};
 	struct clk_hw *parent_hws[10];
 	bool bypass;
 	int i, j;

@@ -1017,6 +1017,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
 
 	parent_data.name = main_xtal_name;
 	parent_data.fw_name = main_xtal_name;
+	parent_data.hw = main_xtal_hw;
 	main_osc_hw = at91_clk_register_main_osc(regmap, "main_osc", NULL,
 						 &parent_data, bypass);
 	if (IS_ERR(main_osc_hw))

Signature · 1 line

2.43.0

[email protected]

author

2025-05-06 20:05 UTC #6 lore raw

PATCH v3 4/4 ARM: dts: microchip: sama7g5: Adjust clock xtal phandle

In reply to [email protected]

From: Ryan Wanner <[email protected]>

Adjust clock xtal phandles to match the new xtal phandle formatting.

Signed-off-by Ryan Wanner <[email protected]>

---
 arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 18 ++++++++----------
 arch/arm/boot/dts/microchip/sama7g5.dtsi       |  4 ++--
 2 files changed, 10 insertions(+), 12 deletions(-)

arch/arm/boot/dts/microchip/at91-sama7g5ek.dts +8 ~~-10~~

index 2543599013b1..79bf58f8c02e 100644
@@ -35,16 +35,6 @@ aliases {
 		i2c2 = &i2c9;
 	};
 
-	clocks {
-		slow_xtal {
-			clock-frequency = <32768>;
-		};
-
-		main_xtal {
-			clock-frequency = <24000000>;
-		};
-	};
-
 	gpio-keys {
 		compatible = "gpio-keys";

@@ -512,6 +502,10 @@ spi11: spi@400 {
 	};
 };
 
+&main_xtal {
+	clock-frequency = <24000000>;
+};
+
 &gmac0 {
 	#address-cells = <1>;
 	#size-cells = <0>;

@@ -917,3 +911,7 @@ &vddout25 {
 	vin-supply = <&vdd_3v3>;
 	status = "okay";
 };
+
+&slow_xtal {
+	clock-frequency = <32768>;
+};

arch/arm/boot/dts/microchip/sama7g5.dtsi +2 -2

index 17bcdcf0cf4a..250c9e98a8bb 100644
@@ -117,12 +117,12 @@ map1 {
 	};
 
 	clocks {
-		slow_xtal: slow_xtal {
+		slow_xtal: clock-slowxtal {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 		};
 
-		main_xtal: main_xtal {
+		main_xtal: clock-mainxtal {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 		};

Signature · 1 line

2.43.0