AT91 SAMA7 SoC Clock Adjustments
Subsystems (2)
v5 cover AT91 SAMA7 SoC Clock Adjustments
From: Ryan Wanner <[email protected]>
This set has clock system adjustments for the AT91 clock system for sama7 SoC family.
The patch set updates the device tree phandle formatting for the sama7g54 SoC. This also adds names to the xtals so the driver can correclty find and name them in the clock tree.
Changes v1 -> v2:
- Add clk_hw struct to parent_data adjustment for the sama7g5.c driver.
- Add correction to sama7g54 dtsi main xtal phandles.
Changes v2 -> v3:
- Removed the empty line after the fixes tag.
- Correct commit messages to better explain the issue that this is fixing.
- Initialize parent_data index to 0.
Changes v3 -> v4:
- Add clock-output-names to the xtal nodes.
- Remove the clock driver changes since those are not needed for this set.
- Adjust cover letter message to reflect the changes in the v4.
Changes v4 -> v5:
- Correct alphabetical issues.
- Add adjustment USB_CLK name to fit the formatting.
- Add clock names to SAM9X75 SoC.
Ryan Wanner (3):
ARM: dts: microchip: sama7g5: Adjust clock xtal phandle
ARM: dts: microchip: sama7d65: Add clock name property
ARM: dts: microchip: sam9x7: Add clock name property
arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 18 ++++++++---------- arch/arm/boot/dts/microchip/sam9x7.dtsi | 2 ++ arch/arm/boot/dts/microchip/sama7d65.dtsi | 2 ++ arch/arm/boot/dts/microchip/sama7g5.dtsi | 9 ++++++--- 4 files changed, 18 insertions(+), 13 deletions(-)
Signature · 1 line
2.43.0
PATCH v5 1/3 ARM: dts: microchip: sama7g5: Adjust clock xtal phandle
From: Ryan Wanner <[email protected]>
Adjust clock xtal phandles to match the new xtal phandle formatting.
--- arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 18 ++++++++---------- arch/arm/boot/dts/microchip/sama7g5.dtsi | 9 ++++++--- 2 files changed, 14 insertions(+), 13 deletions(-)
arch/arm/boot/dts/microchip/at91-sama7g5ek.dts +8 -10
@@ -35,16 +35,6 @@ aliases { i2c2 = &i2c9; }; - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <24000000>; - }; - }; - gpio-keys { compatible = "gpio-keys";
@@ -556,6 +546,10 @@ &i2s0 { pinctrl-0 = <&pinctrl_i2s0_default>; }; +&main_xtal { + clock-frequency = <24000000>; +}; + &pdmc0 { #sound-dai-cells = <0>; microchip,mic-pos = <MCHP_PDMC_DS0 MCHP_PDMC_CLK_NEGATIVE>, /* MIC 1 */
@@ -885,6 +879,10 @@ input@0 { }; }; +&slow_xtal { + clock-frequency = <32768>; +}; + &spdifrx { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spdifrx_default>;
arch/arm/boot/dts/microchip/sama7g5.dtsi +6 -3
@@ -117,19 +117,22 @@ map1 { }; clocks { - slow_xtal: slow_xtal { + slow_xtal: clock-slowxtal { compatible = "fixed-clock"; + clock-output-names = "slow_xtal"; #clock-cells = <0>; }; - main_xtal: main_xtal { + main_xtal: clock-mainxtal { compatible = "fixed-clock"; + clock-output-names = "main_xtal"; #clock-cells = <0>; }; - usb_clk: usb_clk { + usb_clk: clock-usbclk { compatible = "fixed-clock"; #clock-cells = <0>; + clock-output-names = "usb_clk"; clock-frequency = <48000000>; }; };
Signature · 1 line
2.43.0
PATCH v5 2/3 ARM: dts: microchip: sama7d65: Add clock name property
In reply to [email protected]From: Ryan Wanner <[email protected]>
Add clock-output-names to the xtal nodes, so the driver can correctly register the main and slow xtal.
This fixes the issue of the SoC clock driver not being able to find the main xtal and slow xtal correctly causing a bad clock tree.
--- arch/arm/boot/dts/microchip/sama7d65.dtsi | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/boot/dts/microchip/sama7d65.dtsi +2 -0
@@ -38,11 +38,13 @@ cpu0: cpu@0 { clocks { main_xtal: clock-mainxtal { compatible = "fixed-clock"; + clock-output-names = "main_xtal"; #clock-cells = <0>; }; slow_xtal: clock-slowxtal { compatible = "fixed-clock"; + clock-output-names = "slow_xtal"; #clock-cells = <0>; }; };
Signature · 1 line
2.43.0
PATCH v5 3/3 ARM: dts: microchip: sam9x7: Add clock name property
In reply to [email protected]From: Ryan Wanner <[email protected]>
Add clock-output-names to the xtal nodes, so the driver can correctly register the main and slow xtal.
This fixes the issue of the SoC clock driver not being able to find the main xtal and slow xtal correctly causing a bad clock tree.
--- arch/arm/boot/dts/microchip/sam9x7.dtsi | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/boot/dts/microchip/sam9x7.dtsi +2 -0
@@ -45,11 +45,13 @@ cpu@0 { clocks { slow_xtal: clock-slowxtal { compatible = "fixed-clock"; + clock-output-names = "slow_xtal"; #clock-cells = <0>; }; main_xtal: clock-mainxtal { compatible = "fixed-clock"; + clock-output-names = "main_xtal"; #clock-cells = <0>; }; };
Signature · 1 line
2.43.0
Quoted 4 lines · On 17.06.2025 19:08, [email protected] wrote:
Ryan Wanner (3):
ARM: dts: microchip: sama7g5: Adjust clock xtal phandle
ARM: dts: microchip: sama7d65: Add clock name property
ARM: dts: microchip: sam9x7: Add clock name property
Applied to at91-dt, thanks!