PCI: rockchip: Improve quality of driver
Subsystems (5)
v4 cover PCI: rockchip: Improve quality of driver
During a 30-day debugging-run fighting quirky PCIe devices on RK3399 some quality improvements began to take form and this is my attempt at upstreaming it. It will ensure maximum chance of retraining to Gen2 5.0GT/s, on all four lanes and plus if anybody is debugging the PHY they'll now get real values from TEST_I[3:0] for every TEST_ADDR[4:0] without risk of locking up kernel like with present broken async strobe TEST_WRITE.
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V3 -> V4: fix TLS setting-up in Link Control and Status Register 2 and adjust commit titles
V2 -> V3: correctly clean-up with standard PCIe defines as per Bjorn's suggestion
V1 -> V2: use standard PCIe defines as suggested by Bjorn
Geraldo Nascimento (4):
PCI: rockchip: Drop unused custom registers and bitfields
PCI: rockchip: Set Target Link Speed before retraining
phy: rockchip-pcie: Enable all four lanes
phy: rockchip-pcie: Adjust read mask and write
drivers/pci/controller/pcie-rockchip-host.c | 4 ++++ drivers/pci/controller/pcie-rockchip.h | 11 +---------- drivers/phy/rockchip/phy-rockchip-pcie.c | 16 +++++++++------- 3 files changed, 14 insertions(+), 17 deletions(-)
Signature · 1 line
2.49.0
RFC PATCH v4 1/4 PCI: rockchip: Drop unused custom registers and bitfields
Since we are now using standard PCIe defines, drop unused custom-defined ones, which are now referenced from offset at added Capabilities Register.
--- drivers/pci/controller/pcie-rockchip.h | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-)
drivers/pci/controller/pcie-rockchip.h +1 -10
@@ -155,16 +155,7 @@#define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00)#define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0)#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) -#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) -#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 -#define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff -#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 -#define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8) -#define PCIE_RC_CONFIG_DCSR_MPS_MASK GENMASK(7, 5) -#define PCIE_RC_CONFIG_DCSR_MPS_256 (0x1 << 5) -#define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) -#define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10) -#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) +#define PCIE_RC_CONFIG_CR (PCIE_RC_CONFIG_BASE + 0xc0)#define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0)#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)#define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
Signature · 1 line
2.49.0
Quoted 21 lines · Geraldo Nascimento
During a 30-day debugging-run fighting quirky PCIe devices on RK3399 some quality improvements began to take form and this is my attempt at upstreaming it. It will ensure maximum chance of retraining to Gen2 5.0GT/s, on all four lanes and plus if anybody is debugging the PHY they'll now get real values from TEST_I[3:0] for every TEST_ADDR[4:0] without risk of locking up kernel like with present broken async strobe
TEST_WRITE.---
V3 -> V4: fix TLS setting-up in Link Control and Status Register 2 and adjust commit titles
V2 -> V3: correctly clean-up with standard PCIe defines as per Bjorn's suggestion
V1 -> V2: use standard PCIe defines as suggested by BjornGeraldo Nascimento (4):
PCI: rockchip: Drop unused custom registers and bitfields
PCI: rockchip: Set Target Link Speed before retraining
phy: rockchip-pcie: Enable all four lanes
phy: rockchip-pcie: Adjust read mask and write
Quoted 8 lines
drivers/pci/controller/pcie-rockchip-host.c | 4 ++++ drivers/pci/controller/pcie-rockchip.h | 11 +---------- drivers/phy/rockchip/phy-rockchip-pcie.c | 16 +++++++++------- 3 files changed, 14 insertions(+), 17 deletions(-)Signature · 1 line
2.49.0
I somehow have screwed-up threading again. Please ignore. Resending now.
Geraldo Nascimento