Skip to contentSkip to conversation

Add SMMU-V3-PMCG and L2/L3 cache nodes in Agilex5 DTSI

PATCH New [email protected] 1 participant 3 messages Jun 17, 2025 Device tree bindings

lore
Share & tools
lore

[email protected]

author
#0 lore raw

v2 cover Add SMMU-V3-PMCG and L2/L3 cache nodes in Agilex5 DTSI

From: Adrian Ng Ho Yin <[email protected]>

This patchset include the following changes:
-Add SMMU-V3-PMCG node for Agilex5
-Add L2 and L3 cache node for Agilex5

v2:
-Move MMIO nodes into soc@0

Adrian Ng Ho Yin (2):
arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes
arm64: dts: socfpga: agilex5: Add L2 and L3 cache

 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 80 +++++++++++++++++++
 1 file changed, 80 insertions(+)
Signature · 1 line
2.49.GIT
author
#1 lore raw

PATCH v2 1/2 arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes

From: Adrian Ng Ho Yin <[email protected]>

Add SMMU-V3 PMCG nodes for Agilex5.

Signed-off-by Adrian Ng Ho Yin <[email protected]>
Reviewed-by Matthew Gerlach <[email protected]>
---
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +62 -0
index 7d9394a04302..216bb9793ce5 100644
@@ -133,6 +133,12 @@ usbphy0: usbphy {
 		compatible = "usb-nop-xceiv";
 	};
 
+	pmu0: pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
 	soc: soc@0 {
 		compatible = "simple-bus";
 		ranges = <0 0 0 0xffffffff>;

@@ -486,5 +492,61 @@ qspi: spi@108d2000 {
 			clocks = <&qspi_clk>;
 			status = "disabled";
 		};
+
+		pmu0_tcu: pmu@16002000 {
+			compatible = "arm,smmu-v3-pmcg";
+			reg = <0x16002000 0x1000>,
+				<0x16022000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pmu0_tbu0: pmu@16042000 {
+			compatible = "arm,smmu-v3-pmcg";
+			reg = <0x16042000 0x1000>,
+				<0x16052000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pmu0_tbu1: pmu@16062000 {
+			compatible = "arm,smmu-v3-pmcg";
+			reg = <0x16062000 0x1000>,
+				<0x16072000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pmu0_tbu2: pmu@16082000 {
+			compatible = "arm,smmu-v3-pmcg";
+			reg = <0x16082000 0x1000>,
+				<0x16092000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pmu0_tbu3: pmu@160a2000 {
+			compatible = "arm,smmu-v3-pmcg";
+			reg = <0x160A2000 0x1000>,
+				<0x160B2000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pmu0_tbu4: pmu@160c2000 {
+			compatible = "arm,smmu-v3-pmcg";
+			reg = <0x160C2000 0x1000>,
+				<0x160D2000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pmu0_tbu5: pmu@160e2000 {
+			compatible = "arm,smmu-v3-pmcg";
+			reg = <0x160E2000 0x1000>,
+				<0x160F2000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
+		};
 	};
 };
Signature · 1 line
2.49.GIT
author
#2 lore raw

PATCH v2 2/2 arm64: dts: socfpga: agilex5: Add L2 and L3 cache

In reply to [email protected]

From: Adrian Ng Ho Yin <[email protected]>

Add L2 and L3 cache to fix the cacheinfo warning "unable to detect cache hierarchy".

Signed-off-by Kah Jing Lee <[email protected]>
Signed-off-by Adrian Ng Ho Yin <[email protected]>
Reviewed-by Matthew Gerlach <[email protected]>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +18 -0
index 216bb9793ce5..f08cb60791a2 100644
@@ -37,6 +37,7 @@ cpu0: cpu@0 {
 			reg = <0x0>;
 			device_type = "cpu";
 			enable-method = "psci";
+			next-level-cache = <&L2>;
 		};
 
 		cpu1: cpu@1 {

@@ -44,6 +45,7 @@ cpu1: cpu@1 {
 			reg = <0x100>;
 			device_type = "cpu";
 			enable-method = "psci";
+			next-level-cache = <&L2>;
 		};
 
 		cpu2: cpu@2 {

@@ -51,6 +53,7 @@ cpu2: cpu@2 {
 			reg = <0x200>;
 			device_type = "cpu";
 			enable-method = "psci";
+			next-level-cache = <&L2>;
 		};
 
 		cpu3: cpu@3 {

@@ -58,7 +61,22 @@ cpu3: cpu@3 {
 			reg = <0x300>;
 			device_type = "cpu";
 			enable-method = "psci";
+			next-level-cache = <&L2>;
 		};
+
+		L2: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+			next-level-cache = <&L3>;
+			cache-unified;
+		};
+
+		L3: l3-cache {
+			compatible = "cache";
+			cache-level = <3>;
+			cache-unified;
+		};
+
 	};
 
 	psci {
Signature · 1 line
2.49.GIT