Add SMMU-V3-PMCG and L2/L3 cache nodes in Agilex5 DTSI
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b4 am [email protected]Versions newest first · linked by author and title
- v2 Latest2 patches 0 repliesNew
- v1 posting 2/22 patches 2 repliesSuperseded
- v1 posting 1/22 patches 0 repliesSuperseded
Changes in v2 from the cover letter
-Move MMIO nodes into soc@0
Patches in v2 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/2 | arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodesarch/ | +62 | 0 replies | |
| 2/2 | arm64: dts: socfpga: agilex5: Add L2 and L3 cachearch/ | +18 | 0 replies |
Reviews trailers per patch
All 2 patches have a Reviewed-by or Acked-by.
| Patch | Matthew Gerlach |
|---|---|
| 1/2 | R-b |
| 2/2 | R-b |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [PATCH v2 0/2] Add SMMU-V3-PMCG and L2/L3 cache nodes in Agilex5 DTSI
From: Adrian Ng Ho Yin <[email protected]>
This patchset include the following changes:
-Add SMMU-V3-PMCG node for Agilex5
-Add L2 and L3 cache node for Agilex5
v2:
-Move MMIO nodes into soc@0
Adrian Ng Ho Yin (2):
arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes
arm64: dts: socfpga: agilex5: Add L2 and L3 cache
.../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+)
Signature · 1 line
2.49.GIT