Add Altera Agilex5 DWC3 support

From: Adrian Ng Ho Yin <[email protected]>

Add a device tree binding document for the Altera wrapper around the Synopsys DesignWare USB3 (DWC3) controller. The wrapper manages SoC-specific integration such as clock and reset control for the USB subsystem.

A parent–child node structure is used to comply with the generic DWC3

Documentation/devicetree/bindings/usb/dwc3-altera.yaml new file +6 -0

+
+examples:
+  - |
+    usb@11000000 {
+        compatible = "altr,agilex5-dwc3";
+        reg = <0x11000000 0x100000>;

From: Adrian Ng Ho Yin <[email protected]>

Add a device tree binding document for the Altera wrapper around the Synopsys DesignWare USB3 (DWC3) controller. The wrapper manages SoC-specific integration such as clock and reset control for the USB subsystem.

A parent–child node structure is used to comply with the generic DWC3 binding, which restricts the core node to a single clock and reset. The wrapper node provides the additional clocks, resets, and address translation required for the Agilex5 integration.

From: Adrian Ng Ho Yin <[email protected]>

Add device tree nodes for the USB3.1 controller on the Agilex5 SoC and enable it on the SoCDK board. The USB3.1 block consists of a SoC-specific wrapper around the Synopsys DWC3 core that handles clock, reset, and address translation configuration.

The DWC3 core is described as a child of the wrapper to reflect the hardware hierarchy and comply with the DWC3 binding requirements.

This commit also disables the DWC2 USB controller node, as the daughter card does not support simultaneous operation of both USB controllers.

Signed-off-by Adrian Ng Ho Yin <[email protected]>

---
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 24 +++++++++++++++++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  9 ++++++-

From: Adrian Ng Ho Yin <[email protected]>

Add the compatible string "altr,agilex5-dwc3" to the dwc3-of-simple driver match table to enable support for the DWC3 controller on Agilex5 SoCFPGA platform.

The DWC3 controller on Agilex5 is instantiated as a child node under the DWC3 simple glue layer. The simple glue layer is sufficient for Agilex5 as no platform-specific initialization or custom control logic is required.

Signed-off-by Adrian Ng Ho Yin <[email protected]>

---
 drivers/usb/dwc3/dwc3-of-simple.c | 1 +
 1 file changed, 1 insertion(+)

drivers/usb/dwc3/dwc3-of-simple.c +1 -0

index a4954a21be93..52f9ee236a1e 100644
@@ -174,6 +174,7 @@ static const struct of_device_id of_dwc3_simple_match[] = {
 	{ .compatible = "hisilicon,hi3670-dwc3" },
 	{ .compatible = "hisilicon,hi3798mv200-dwc3" },
 	{ .compatible = "intel,keembay-dwc3" },
+	{ .compatible = "altr,agilex5-dwc3" },
 	{ /* Sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, of_dwc3_simple_match);

Signature · 1 line

2.49.GIT

From: Adrian Ng Ho Yin <[email protected]>

Add support for configuring the DMA addressable bit width in the Synopsys DesignWare USB3 (DWC3) core driver.

Altera Agilex5 supports only 40-bit DMA addressing. Setting an incorrect DMA mask (such as the default 64-bit) can lead to address truncation or translation faults when the SMMU is enabled.

This commit introduces a new field, dma_addressable_bits, in the dwc3 structure to track the platform’s supported DMA width. The default value is set to 64 bits, but for Agilex5 platforms (altr,agilex5-dwc3), the value is overridden to 40 bits. This field is then used when setting the DMA mask to ensure compatibility with the system’s actual address bus capabilities.

Signed-off-by Adrian Ng Ho Yin <[email protected]>

---
 drivers/usb/dwc3/core.c | 9 ++++++++-
 drivers/usb/dwc3/core.h | 3 +++
 2 files changed, 11 insertions(+), 1 deletion(-)

drivers/usb/dwc3/core.c +3 -0

index ae140c356295..20e655364135 100644
@@ -2179,6 +2179,9 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
 	dwc->xhci_resources[0].flags = res->flags;
 	dwc->xhci_resources[0].name = res->name;
 
+	/* Initialize dma addressable bit to 64 bits as default */
+	dwc->dma_addressable_bits = 64;
+
 	/*
 	 * Request memory region but exclude xHCI regs,
 	 * since it will be requested by the xhci-plat driver.

From: Adrian Ng Ho Yin <[email protected]>

Add support for configuring the DMA addressable bit width in the Synopsys DesignWare USB3 (DWC3) core driver.

Altera Agilex5 supports only 40-bit DMA addressing. Setting an incorrect DMA mask (such as the default 64-bit) can lead to address truncation or translation faults when the SMMU is enabled.

This commit introduces a new field, dma_addressable_bits, in the dwc3 structure to track the platform’s supported DMA width. The default value is set to 64 bits, but for Agilex5 platforms (altr,agilex5-dwc3), the value is overridden to 40 bits. This field is then used when setting the DMA mask to ensure compatibility with the system’s actual address bus capabilities.

Signed-off-by Adrian Ng Ho Yin <[email protected]>

---
 drivers/usb/dwc3/core.c | 9 ++++++++-
 drivers/usb/dwc3/core.h | 3 +++
 2 files changed, 11 insertions(+), 1 deletion(-)

drivers/usb/dwc3/core.c +0 -0

index ae140c356295..20e655364135 100644

drivers/usb/dwc3/core.c +4 -1

+			dwc->dma_addressable_bits = 40;
+
 		of_node_put(parent);
 	}
 

@@ -2243,7 +2249,8 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
 
 	if (!dwc->sysdev_is_parent &&
 	    DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
-		ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
+		ret = dma_set_mask_and_coherent(dwc->sysdev,
+						DMA_BIT_MASK(dwc->dma_addressable_bits));
 		if (ret)
 			goto err_disable_clks;
 	}

drivers/usb/dwc3/core.h +3 -0

index a5fc92c4ffa3..ddc42c88da93 100644
@@ -1180,6 +1180,8 @@ struct dwc3_glue_ops {
  * @wakeup_pending_funcs: Indicates whether any interface has requested for
  *			 function wakeup in bitmap format where bit position
  *			 represents interface_id.
+ * @dma_addressable_bits: set if we need to configure a different
+ *			dma-bit-mask other than 64 bits.
  */
 struct dwc3 {
 	struct work_struct	drd_work;

@@ -1414,6 +1416,7 @@ struct dwc3 {
 	struct dentry		*debug_root;
 	u32			gsbuscfg0_reqinfo;
 	u32			wakeup_pending_funcs;
+	u32			dma_addressable_bits;
 };
 
 #define INCRX_BURST_MODE 0

Signature · 1 line

2.49.GIT