Skip to contentSkip to conversation

clock: versal-clk: Fix Versal NET clock binding and switch to CCF

PATCH Superseded Michal Simek 2 participants 6 messages Mar 5 – May 29

Subsystems (3)
Device tree bindings Common clk Arm/Zynq architecture

v1 of 5 Superseded Latest is v5 →

lore
Share & tools
lore

Michal Simek

author maintainer
#0 lore raw

cover clock: versal-clk: Fix Versal NET clock binding and switch to CCF

This series fixes the Versal NET clock controller DT binding validation and switches the platform to use the firmware-based CCF clock interface.

Patch 1 restructures the if/then conditions in the versal-clk binding schema so that xlnx,versal-net-clk is matched first before falling back to xlnx,versal-clk. This fixes false "too long" validation errors caused by both conditions matching simultaneously when the fallback compatible is present. A dedicated example for the Versal NET 3-clock configuration is added and all examples are split into separate blocks for independent validation.

Patch 2 switches Versal NET from static fixed-clock definitions to the firmware-based CCF clock interface, enabling proper clock management through platform firmware. DT macro headers for clocks, power domains and resets are added.

Thanks,
Michal

Michal Simek (2):
dt-bindings: clock: versal-clk: Reorder if/then conditions for Versal
NET
arm64: zynqmp: Switch Versal NET to firmware clock interface

 .../bindings/clock/xlnx,versal-clk.yaml       |  49 ++-
 .../boot/dts/xilinx/versal-net-clk-ccf.dtsi   | 378 ++++++++++++++++++
 .../xilinx/versal-net-vn-x-b2197-01-revA.dts  |   3 +-
 arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h  | 123 ++++++
 .../boot/dts/xilinx/xlnx-versal-net-clk.h     |  78 ++++
 .../boot/dts/xilinx/xlnx-versal-net-power.h   |  38 ++
 .../boot/dts/xilinx/xlnx-versal-net-resets.h  |  53 +++
 .../arm64/boot/dts/xilinx/xlnx-versal-power.h |  54 +++
 .../boot/dts/xilinx/xlnx-versal-resets.h      | 105 +++++
 9 files changed, 858 insertions(+), 23 deletions(-)
 create mode 100644 arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-power.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h
Signature · 4 lines
2.43.0

base-commit: fbf33803618ad4f531f78fe15cf328fe6c7f9978
branch: zynqmp/dt
author maintainer
#1 lore raw

PATCH 1/2 dt-bindings: clock: versal-clk: Reorder if/then conditions for Versal NET

The Versal NET clock controller compatible is specified as:
compatible = "xlnx,versal-net-clk", "xlnx,versal-clk";

with xlnx,versal-clk listed as fallback. The original binding had two separate if/then blocks - one matching xlnx,versal-clk (2 clocks) and another matching xlnx,versal-net-clk (3 clocks). Since both compatible strings are present, both conditions matched simultaneously and JSON Schema applied the more restrictive 2-clock constraint, causing false "too long" validation errors for Versal NET.

Restructure the allOf conditions to check for xlnx,versal-net-clk first. If matched, allow 3 clocks (ref, pl_alt_ref, alt_ref). Otherwise fall back to the xlnx,versal-clk case with 2 clocks (ref, pl_alt_ref).

Add a dedicated example for the Versal NET 3-clock configuration and split all examples into separate blocks so each compatible variant is validated independently by dt_binding_check.

Signed-off-by Michal Simek <[email protected]>

---

 .../bindings/clock/xlnx,versal-clk.yaml       | 49 ++++++++++---------
 1 file changed, 27 insertions(+), 22 deletions(-)
Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +27 -22
index bef109d163a8..65d926d8f464 100644
@@ -51,28 +51,7 @@ allOf:
       properties:
         compatible:
           contains:
-            enum:
-              - xlnx,versal-clk
-
-    then:
-      properties:
-        clocks:
-          items:
-            - description: reference clock
-            - description: alternate reference clock for programmable logic
-
-        clock-names:
-          items:
-            - const: ref
-            - const: pl_alt_ref
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - xlnx,versal-net-clk
-
+            const: xlnx,versal-net-clk
     then:
       properties:
         clocks:

@@ -86,6 +65,23 @@ allOf:
             - const: ref
             - const: pl_alt_ref
             - const: alt_ref
+    else:
+      if:
+        properties:
+          compatible:
+            contains:
+              const: xlnx,versal-clk
+      then:
+        properties:
+          clocks:
+            items:
+              - description: reference clock
+              - description: alternate reference clock for programmable logic
+
+          clock-names:
+            items:
+              - const: ref
+              - const: pl_alt_ref
 
   - if:
       properties:

@@ -135,6 +131,15 @@ examples:
       };
     };
 
+  - |
+    clock-controller {
+        #clock-cells = <1>;
+        compatible = "xlnx,versal-net-clk", "xlnx,versal-clk";
+        clocks = <&ref>, <&pl_alt_ref>, <&alt_ref>;
+        clock-names = "ref", "pl_alt_ref", "alt_ref";
+    };
+
+  - |
     clock-controller {
         #clock-cells = <1>;
         compatible = "xlnx,zynqmp-clk";
Signature · 1 line
2.43.0
maintainer
#2 lore raw

Re: [PATCH 1/2] dt-bindings: clock: versal-clk: Reorder if/then conditions for Versal NET

Quoted 10 lines · Michal Simek

The Versal NET clock controller compatible is specified as:
compatible = "xlnx,versal-net-clk", "xlnx,versal-clk";

with xlnx,versal-clk listed as fallback. The original binding had two separate if/then blocks - one matching xlnx,versal-clk (2 clocks) and another matching xlnx,versal-net-clk (3 clocks). Since both compatible strings are present, both conditions matched simultaneously and JSON Schema applied the more restrictive 2-clock constraint, causing false "too long" validation errors for Versal NET.

Quoted 8 lines

Restructure the allOf conditions to check for xlnx,versal-net-clk first. If matched, allow 3 clocks (ref, pl_alt_ref, alt_ref). Otherwise fall back to the xlnx,versal-clk case with 2 clocks (ref, pl_alt_ref).

Add a dedicated example for the Versal NET 3-clock configuration and split all examples into separate blocks so each compatible variant is validated independently by dt_binding_check.

Really, the problem is xlnx,zynqmp-clk should be moved to its own schema. The only thing common is #clock-cells==1, but that would be true for hundreds of bindings. If you do that, then the clock-names can be defined at the top-level which is preferred anyway, and the only thing needed in if/then schemas is 'maxItems: 2' and 'minItems: 3'.

Rob

author maintainer
#3 lore raw

PATCH 2/2 arm64: zynqmp: Switch Versal NET to firmware clock interface

In reply to Michal Simek

Switch Versal NET from using fixed clocks (versal-net-clk.dtsi) to the firmware-based CCF clock interface (versal-net-clk-ccf.dtsi). This enables proper clock management through the platform firmware instead of relying on static fixed-clock definitions.

Add DT macro headers for Versal NET and base Versal clocks, power domains and resets that are required by the CCF clock dtsi.

Signed-off-by Michal Simek <[email protected]>

---

 .../boot/dts/xilinx/versal-net-clk-ccf.dtsi   | 378 ++++++++++++++++++
 .../xilinx/versal-net-vn-x-b2197-01-revA.dts  |   3 +-
 arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h  | 123 ++++++
 .../boot/dts/xilinx/xlnx-versal-net-clk.h     |  78 ++++
 .../boot/dts/xilinx/xlnx-versal-net-power.h   |  38 ++
 .../boot/dts/xilinx/xlnx-versal-net-resets.h  |  53 +++
 .../arm64/boot/dts/xilinx/xlnx-versal-power.h |  54 +++
 .../boot/dts/xilinx/xlnx-versal-resets.h      | 105 +++++
 8 files changed, 831 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-power.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h
arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi new file +378 -0
new file mode 100644
index 000000000000..1b8c7bbbcf5c
@@ -0,0 +1,378 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal with PM
+ *
+ * Copyright (C) 2022, Xilinx, Inc.
+ * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <[email protected]>
+ */
+
+#include "xlnx-versal-net-clk.h"
+#include "xlnx-versal-net-power.h"
+#include "xlnx-versal-net-resets.h"
+
+/ {
+	ref_clk: ref-clk {
+		bootph-all;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <33333333>;
+		clock-output-names = "ref_clk";
+	};
+
+	rtc_clk: rtc-clk {
+		bootph-all;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "rtc_clk";
+	};
+
+	can0_clk: can0-clk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&versal_net_clk CAN0_REF_2X>;
+		clock-div = <2>;
+		clock-mult = <1>;
+		clock-output-names = "can0_clk";
+	};
+
+	can1_clk: can1-clk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&versal_net_clk CAN1_REF_2X>;
+		clock-div = <2>;
+		clock-mult = <1>;
+		clock-output-names = "can1_clk";
+	};
+
+	firmware {
+		versal_net_firmware: versal-net-firmware {
+			compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware";
+			bootph-all;
+			method = "smc";
+			#power-domain-cells = <1>;
+
+			versal_net_reset: reset-controller {
+				compatible = "xlnx,versal-net-reset";
+				#reset-cells = <1>;
+			};
+
+			versal_net_clk: clock-controller {
+				bootph-all;
+				#clock-cells = <1>;
+				compatible = "xlnx,versal-net-clk", "xlnx,versal-clk";
+				clocks = <&ref_clk>, <&ref_clk>, <&ref_clk>;
+				clock-names = "ref", "pl_alt_ref", "alt_ref";
+			};
+
+			versal_net_power: power-management { /* untested */
+				compatible = "xlnx,zynqmp-power";
+				interrupt-parent = <&gic>;
+				interrupts = <0 57 4>;
+				mboxes = <&ipi_mailbox_pmu1 0>,
+					 <&ipi_mailbox_pmu1 1>;
+				mbox-names = "tx", "rx";
+			};
+		};
+	};
+
+	zynqmp-ipi {
+		compatible = "xlnx,zynqmp-ipi-mailbox";
+		interrupt-parent = <&gic>;
+		interrupts = <0 57 4>;
+		xlnx,ipi-id = <2>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		ipi_mailbox_pmu1: mailbox@eb3f0440 {
+			compatible = "xlnx,zynqmp-ipi-dest-mailbox";
+			reg = <0 0xeb3f0440 0 0x20>,
+			      <0 0xeb3f0460 0 0x20>,
+			      <0 0xeb3f0280 0 0x20>,
+			      <0 0xeb3f02a0 0 0x20>;
+			reg-names = "local_request_region", "local_response_region",
+				    "remote_request_region", "remote_response_region";
+			#mbox-cells = <1>;
+			xlnx,ipi-id = <1>;
+		};
+	};
+};
+
+&cpu0 {
+	clocks = <&versal_net_clk ACPU_0>;
+};
+
+&cpu100 {
+	clocks = <&versal_net_clk ACPU_0>;
+};
+
+&cpu200 {
+	clocks = <&versal_net_clk ACPU_0>;
+};
+
+&cpu300 {
+	clocks = <&versal_net_clk ACPU_0>;
+};
+
+&cpu10000 {
+	clocks = <&versal_net_clk ACPU_1>;
+};
+
+&cpu10100 {
+	clocks = <&versal_net_clk ACPU_1>;
+};
+
+&cpu10200 {
+	clocks = <&versal_net_clk ACPU_1>;
+};
+
+&cpu10300 {
+	clocks = <&versal_net_clk ACPU_1>;
+};
+
+&cpu20000 {
+	clocks = <&versal_net_clk ACPU_2>;
+};
+
+&cpu20100 {
+	clocks = <&versal_net_clk ACPU_2>;
+};
+
+&cpu20200 {
+	clocks = <&versal_net_clk ACPU_2>;
+};
+
+&cpu20300 {
+	clocks = <&versal_net_clk ACPU_2>;
+};
+
+&cpu30000 {
+	clocks = <&versal_net_clk ACPU_3>;
+};
+
+&cpu30100 {
+	clocks = <&versal_net_clk ACPU_3>;
+};
+
+&cpu30200 {
+	clocks = <&versal_net_clk ACPU_3>;
+};
+
+&cpu30300 {
+	clocks = <&versal_net_clk ACPU_3>;
+};
+
+&can0 {
+	clocks = <&can0_clk>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>;
+};
+
+&can1 {
+	clocks = <&can1_clk>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>;
+};
+
+&gem0 {
+	clocks = <&versal_net_clk LPD_LSBUS>,
+		 <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>,
+		 <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>;
+	power-domains = <&versal_net_firmware PM_DEV_GEM_0>;
+};
+
+&gem1 {
+	clocks = <&versal_net_clk LPD_LSBUS>,
+		 <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>,
+		 <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>;
+	power-domains = <&versal_net_firmware PM_DEV_GEM_1>;
+};
+
+&gpio0 {
+	clocks = <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_GPIO>;
+};
+
+&gpio1 {
+	clocks = <&versal_net_clk PMC_LSBUS_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>;
+};
+
+&i2c0 {
+	clocks = <&versal_net_clk I3C0_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_I2C_0>;
+};
+
+&i2c1 {
+	clocks = <&versal_net_clk I3C1_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_I2C_1>;
+};
+
+&i3c0 {
+	clocks = <&versal_net_clk I3C0_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_I2C_0>;
+};
+
+&i3c1 {
+	clocks = <&versal_net_clk I3C1_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_I2C_1>;
+};
+
+&adma0 {
+	clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_ADMA_0>;
+};
+
+&adma1 {
+	clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_ADMA_1>;
+};
+
+&adma2 {
+	clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_ADMA_2>;
+};
+
+&adma3 {
+	clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_ADMA_3>;
+};
+
+&adma4 {
+	clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_ADMA_4>;
+};
+
+&adma5 {
+	clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_ADMA_5>;
+};
+
+&adma6 {
+	clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_ADMA_6>;
+};
+
+&adma7 {
+	clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_ADMA_7>;
+};
+
+&qspi {
+	clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_QSPI>;
+};
+
+&ospi {
+	clocks = <&versal_net_clk OSPI_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_OSPI>;
+};
+
+&rtc {
+	clocks = <&rtc_clk>;
+	clock-names = "rtc";
+	power-domains = <&versal_net_firmware PM_DEV_RTC>;
+};
+
+&serial0 {
+	clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_UART_0>;
+};
+
+&serial1 {
+	clocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_UART_1>;
+};
+
+&sdhci0 {
+	clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>,
+		 <&versal_net_clk SD_DLL_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_SDIO_0>;
+};
+
+&sdhci1 {
+	clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>,
+		 <&versal_net_clk SD_DLL_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_SDIO_1>;
+};
+
+&spi0 {
+	clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_SPI_0>;
+};
+
+&spi1 {
+	clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_SPI_1>;
+};
+
+&ttc0 {
+	clocks = <&versal_net_clk TTC0>;
+	power-domains = <&versal_net_firmware PM_DEV_TTC_0>;
+};
+
+&ttc1 {
+	clocks = <&versal_net_clk TTC1>;
+	power-domains = <&versal_net_firmware PM_DEV_TTC_1>;
+};
+
+&ttc2 {
+	clocks = <&versal_net_clk TTC2>;
+	power-domains = <&versal_net_firmware PM_DEV_TTC_2>;
+};
+
+&ttc3 {
+	clocks = <&versal_net_clk TTC3>;
+	power-domains = <&versal_net_firmware PM_DEV_TTC_3>;
+};
+
+&usb0 {
+	clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_USB_0>;
+	resets = <&versal_net_reset VERSAL_RST_USB_0>;
+};
+
+&dwc3_0 {
+	clocks = <&versal_net_clk USB0_BUS_REF>;
+};
+
+&usb1 {
+	clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_USB_1>;
+	resets = <&versal_net_reset VERSAL_RST_USB_1>;
+};
+
+&dwc3_1 {
+	clocks = <&versal_net_clk USB1_BUS_REF>;
+};
+
+&wwdt0 {
+	clocks = <&versal_net_clk FPD_WWDT0>;
+	power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>;
+};
+
+&wwdt1 {
+	clocks = <&versal_net_clk FPD_WWDT1>;
+	power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>;
+};
+
+&wwdt2 {
+	clocks = <&versal_net_clk FPD_WWDT2>;
+	power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>;
+};
+
+&wwdt3 {
+	clocks = <&versal_net_clk FPD_WWDT3>;
+	power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>;
+};
+
+&lpd_wwdt0 {
+	clocks = <&versal_net_clk LPD_WWDT0>;
+	power-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_0>;
+};
+
+&lpd_wwdt1 {
+	clocks = <&versal_net_clk LPD_WWDT1>;
+	power-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_1>;
+};
arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts +2 -1
index 06b2301f48a0..322ef8f6340d 100644
@@ -11,8 +11,9 @@
 /dts-v1/;
 
 #include "versal-net.dtsi"
-#include "versal-net-clk.dtsi"
+#include "versal-net-clk-ccf.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include "xlnx-versal-net-power.h"
 
 / {
 	compatible = "xlnx,versal-net-vnx-revA", "xlnx,versal-net-vnx", "xlnx,versal-net";
arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h new file +123 -0

123 lines not on this page · raw message

arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h new file +78 -0

78 lines not on this page · raw message

arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h new file +38 -0
new file mode 100644
index 000000000000..34f99695655d
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022, Xilinx, Inc.
+ * Copyright (C) 2022, Advanced Micro Devices, Inc.
+ */
+
+#ifndef _DT_BINDINGS_VERSAL_NET_POWER_H
+#define _DT_BINDINGS_VERSAL_NET_POWER_H
+
+#include "xlnx-versal-power.h"
+
+#define PM_DEV_USB_1				(0x182240D7U)
+#define PM_DEV_FPD_SWDT_0			(0x182240DBU)
+#define PM_DEV_FPD_SWDT_1			(0x182240DCU)
+#define PM_DEV_FPD_SWDT_2			(0x182240DDU)
+#define PM_DEV_FPD_SWDT_3			(0x182240DEU)
+#define PM_DEV_TCM_A_0A				(0x183180CBU)
+#define PM_DEV_TCM_A_0B				(0x183180CCU)
+#define PM_DEV_TCM_A_0C				(0x183180CDU)
+#define PM_DEV_RPU_A_0				(0x181100BFU)
+#define PM_DEV_LPD_SWDT_0			(0x182240D9U)
+#define PM_DEV_LPD_SWDT_1			(0x182240DAU)
+
+/* Remove Versal specific node IDs */
+#undef PM_DEV_RPU0_0
+#undef PM_DEV_RPU0_1
+#undef PM_DEV_OCM_0
+#undef PM_DEV_OCM_1
+#undef PM_DEV_OCM_2
+#undef PM_DEV_OCM_3
+#undef PM_DEV_TCM_0_A
+#undef PM_DEV_TCM_1_A
+#undef PM_DEV_TCM_0_B
+#undef PM_DEV_TCM_1_B
+#undef PM_DEV_SWDT_FPD
+#undef PM_DEV_AI
+
+#endif
arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h new file +53 -0

53 lines not on this page · raw message

arch/arm64/boot/dts/xilinx/xlnx-versal-power.h new file +54 -0

54 lines not on this page · raw message

arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h new file +105 -0

105 lines not on this page · raw message

Signature · 1 line
2.43.0
maintainer
#4 lore raw

Re: [PATCH 2/2] arm64: zynqmp: Switch Versal NET to firmware clock interface

Quoted 29 lines · Michal Simek

Switch Versal NET from using fixed clocks (versal-net-clk.dtsi) to the firmware-based CCF clock interface (versal-net-clk-ccf.dtsi). This enables proper clock management through the platform firmware instead of relying on static fixed-clock definitions.

Add DT macro headers for Versal NET and base Versal clocks, power domains and resets that are required by the CCF clock dtsi.

Signed-off-by Michal Simek <[email protected]>

---

 .../boot/dts/xilinx/versal-net-clk-ccf.dtsi   | 378 ++++++++++++++++++
 .../xilinx/versal-net-vn-x-b2197-01-revA.dts  |   3 +-
 arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h  | 123 ++++++
 .../boot/dts/xilinx/xlnx-versal-net-clk.h     |  78 ++++
 .../boot/dts/xilinx/xlnx-versal-net-power.h   |  38 ++
 .../boot/dts/xilinx/xlnx-versal-net-resets.h  |  53 +++
 .../arm64/boot/dts/xilinx/xlnx-versal-power.h |  54 +++
 .../boot/dts/xilinx/xlnx-versal-resets.h      | 105 +++++
 8 files changed, 831 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-power.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h

arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi line 16

Quoted 7 lines
arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi new file +7 -0
+
+#include "xlnx-versal-net-clk.h"
+#include "xlnx-versal-net-power.h"
+#include "xlnx-versal-net-resets.h"
+
+/ {
+	ref_clk: ref-clk {

Preferred node name is clock-33333333.

arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi line 24

Quoted 8 lines
arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi new file +8 -0
+		bootph-all;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <33333333>;
+		clock-output-names = "ref_clk";
+	};
+
+	rtc_clk: rtc-clk {

clock-32768

Quoted 72 lines
arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi new file +72 -0
+		bootph-all;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "rtc_clk";
+	};
+
+	can0_clk: can0-clk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&versal_net_clk CAN0_REF_2X>;
+		clock-div = <2>;
+		clock-mult = <1>;
+		clock-output-names = "can0_clk";
+	};
+
+	can1_clk: can1-clk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&versal_net_clk CAN1_REF_2X>;
+		clock-div = <2>;
+		clock-mult = <1>;
+		clock-output-names = "can1_clk";
+	};
+
+	firmware {
+		versal_net_firmware: versal-net-firmware {
+			compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware";
+			bootph-all;
+			method = "smc";
+			#power-domain-cells = <1>;
+
+			versal_net_reset: reset-controller {
+				compatible = "xlnx,versal-net-reset";
+				#reset-cells = <1>;
+			};
+
+			versal_net_clk: clock-controller {
+				bootph-all;
+				#clock-cells = <1>;
+				compatible = "xlnx,versal-net-clk", "xlnx,versal-clk";
+				clocks = <&ref_clk>, <&ref_clk>, <&ref_clk>;
+				clock-names = "ref", "pl_alt_ref", "alt_ref";
+			};
+
+			versal_net_power: power-management { /* untested */
+				compatible = "xlnx,zynqmp-power";
+				interrupt-parent = <&gic>;
+				interrupts = <0 57 4>;
+				mboxes = <&ipi_mailbox_pmu1 0>,
+					 <&ipi_mailbox_pmu1 1>;
+				mbox-names = "tx", "rx";
+			};
+		};
+	};
+
+	zynqmp-ipi {
+		compatible = "xlnx,zynqmp-ipi-mailbox";
+		interrupt-parent = <&gic>;
+		interrupts = <0 57 4>;
+		xlnx,ipi-id = <2>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		ipi_mailbox_pmu1: mailbox@eb3f0440 {
+			compatible = "xlnx,zynqmp-ipi-dest-mailbox";
+			reg = <0 0xeb3f0440 0 0x20>,
+			      <0 0xeb3f0460 0 0x20>,
+			      <0 0xeb3f0280 0 0x20>,
+			      <0 0xeb3f02a0 0 0x20>;
+			reg-names = "local_request_region", "local_response_region",

arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi line 106

Quoted 10 lines
arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi new file +10 -0
+				    "remote_request_region", "remote_response_region";
+			#mbox-cells = <1>;
+			xlnx,ipi-id = <1>;
+		};
+	};
+};
+
+&cpu0 {
+	clocks = <&versal_net_clk ACPU_0>;
+};

This structure is unusual and not great for readability. Imagine if we did a .dtsi for each provider with all the consumer properties.

Quoted 277 lines
arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi new file +272 -0
+
+&cpu100 {
+	clocks = <&versal_net_clk ACPU_0>;
+};
+
+&cpu200 {
+	clocks = <&versal_net_clk ACPU_0>;
+};
+
+&cpu300 {
+	clocks = <&versal_net_clk ACPU_0>;
+};
+
+&cpu10000 {
+	clocks = <&versal_net_clk ACPU_1>;
+};
+
+&cpu10100 {
+	clocks = <&versal_net_clk ACPU_1>;
+};
+
+&cpu10200 {
+	clocks = <&versal_net_clk ACPU_1>;
+};
+
+&cpu10300 {
+	clocks = <&versal_net_clk ACPU_1>;
+};
+
+&cpu20000 {
+	clocks = <&versal_net_clk ACPU_2>;
+};
+
+&cpu20100 {
+	clocks = <&versal_net_clk ACPU_2>;
+};
+
+&cpu20200 {
+	clocks = <&versal_net_clk ACPU_2>;
+};
+
+&cpu20300 {
+	clocks = <&versal_net_clk ACPU_2>;
+};
+
+&cpu30000 {
+	clocks = <&versal_net_clk ACPU_3>;
+};
+
+&cpu30100 {
+	clocks = <&versal_net_clk ACPU_3>;
+};
+
+&cpu30200 {
+	clocks = <&versal_net_clk ACPU_3>;
+};
+
+&cpu30300 {
+	clocks = <&versal_net_clk ACPU_3>;
+};
+
+&can0 {
+	clocks = <&can0_clk>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>;
+};
+
+&can1 {
+	clocks = <&can1_clk>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>;
+};
+
+&gem0 {
+	clocks = <&versal_net_clk LPD_LSBUS>,
+		 <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>,
+		 <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>;
+	power-domains = <&versal_net_firmware PM_DEV_GEM_0>;
+};
+
+&gem1 {
+	clocks = <&versal_net_clk LPD_LSBUS>,
+		 <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>,
+		 <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>;
+	power-domains = <&versal_net_firmware PM_DEV_GEM_1>;
+};
+
+&gpio0 {
+	clocks = <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_GPIO>;
+};
+
+&gpio1 {
+	clocks = <&versal_net_clk PMC_LSBUS_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>;
+};
+
+&i2c0 {
+	clocks = <&versal_net_clk I3C0_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_I2C_0>;
+};
+
+&i2c1 {
+	clocks = <&versal_net_clk I3C1_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_I2C_1>;
+};
+
+&i3c0 {
+	clocks = <&versal_net_clk I3C0_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_I2C_0>;
+};
+
+&i3c1 {
+	clocks = <&versal_net_clk I3C1_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_I2C_1>;
+};
+
+&adma0 {
+	clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_ADMA_0>;
+};
+
+&adma1 {
+	clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_ADMA_1>;
+};
+
+&adma2 {
+	clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_ADMA_2>;
+};
+
+&adma3 {
+	clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_ADMA_3>;
+};
+
+&adma4 {
+	clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_ADMA_4>;
+};
+
+&adma5 {
+	clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_ADMA_5>;
+};
+
+&adma6 {
+	clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_ADMA_6>;
+};
+
+&adma7 {
+	clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_ADMA_7>;
+};
+
+&qspi {
+	clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_QSPI>;
+};
+
+&ospi {
+	clocks = <&versal_net_clk OSPI_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_OSPI>;
+};
+
+&rtc {
+	clocks = <&rtc_clk>;
+	clock-names = "rtc";
+	power-domains = <&versal_net_firmware PM_DEV_RTC>;
+};
+
+&serial0 {
+	clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_UART_0>;
+};
+
+&serial1 {
+	clocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_UART_1>;
+};
+
+&sdhci0 {
+	clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>,
+		 <&versal_net_clk SD_DLL_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_SDIO_0>;
+};
+
+&sdhci1 {
+	clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>,
+		 <&versal_net_clk SD_DLL_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_SDIO_1>;
+};
+
+&spi0 {
+	clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_SPI_0>;
+};
+
+&spi1 {
+	clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>;
+	power-domains = <&versal_net_firmware PM_DEV_SPI_1>;
+};
+
+&ttc0 {
+	clocks = <&versal_net_clk TTC0>;
+	power-domains = <&versal_net_firmware PM_DEV_TTC_0>;
+};
+
+&ttc1 {
+	clocks = <&versal_net_clk TTC1>;
+	power-domains = <&versal_net_firmware PM_DEV_TTC_1>;
+};
+
+&ttc2 {
+	clocks = <&versal_net_clk TTC2>;
+	power-domains = <&versal_net_firmware PM_DEV_TTC_2>;
+};
+
+&ttc3 {
+	clocks = <&versal_net_clk TTC3>;
+	power-domains = <&versal_net_firmware PM_DEV_TTC_3>;
+};
+
+&usb0 {
+	clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_USB_0>;
+	resets = <&versal_net_reset VERSAL_RST_USB_0>;
+};
+
+&dwc3_0 {
+	clocks = <&versal_net_clk USB0_BUS_REF>;
+};
+
+&usb1 {
+	clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>;
+	power-domains = <&versal_net_firmware PM_DEV_USB_1>;
+	resets = <&versal_net_reset VERSAL_RST_USB_1>;
+};
+
+&dwc3_1 {
+	clocks = <&versal_net_clk USB1_BUS_REF>;
+};
+
+&wwdt0 {
+	clocks = <&versal_net_clk FPD_WWDT0>;
+	power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>;
+};
+
+&wwdt1 {
+	clocks = <&versal_net_clk FPD_WWDT1>;
+	power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>;
+};
+
+&wwdt2 {
+	clocks = <&versal_net_clk FPD_WWDT2>;
+	power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>;
+};
+
+&wwdt3 {
+	clocks = <&versal_net_clk FPD_WWDT3>;
+	power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>;
+};
+
+&lpd_wwdt0 {
+	clocks = <&versal_net_clk LPD_WWDT0>;
+	power-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_0>;
+};
+
+&lpd_wwdt1 {
+	clocks = <&versal_net_clk LPD_WWDT1>;
+	power-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_1>;
+};
arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts +0 -0
index 06b2301f48a0..322ef8f6340d 100644

arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts line 14

Quoted 4 lines
arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts +0 -1
@@ -11,8 +11,9 @@
 /dts-v1/;
 
 #include "versal-net.dtsi"
-#include "versal-net-clk.dtsi"

Now this is unused and should be removed.

arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts line 14

Quoted 1 line
arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts +1 -0
+#include "versal-net-clk-ccf.dtsi"

Or perhaps reuse the filename because what does Common Clock Framework have to do with DTS file names?

Quoted 2 lines
arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts +1 -0
 #include <dt-bindings/gpio/gpio.h>
+#include "xlnx-versal-net-power.h"
author maintainer
#5 lore raw

Re: [PATCH 2/2] arm64: zynqmp: Switch Versal NET to firmware clock interface

Quoted 10 lines · Rob Herring
Quoted 9 lines · Michal Simek

Switch Versal NET from using fixed clocks (versal-net-clk.dtsi) to the firmware-based CCF clock interface (versal-net-clk-ccf.dtsi). This enables proper clock management through the platform firmware instead of relying on static fixed-clock definitions.

Add DT macro headers for Versal NET and base Versal clocks, power domains and resets that are required by the CCF clock dtsi.

Signed-off-by Michal Simek <[email protected]>

...

Quoted 52 lines
Quoted 52 lines
arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi new file +52 -0
+	firmware {
+		versal_net_firmware: versal-net-firmware {
+			compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware";
+			bootph-all;
+			method = "smc";
+			#power-domain-cells = <1>;
+
+			versal_net_reset: reset-controller {
+				compatible = "xlnx,versal-net-reset";
+				#reset-cells = <1>;
+			};
+
+			versal_net_clk: clock-controller {
+				bootph-all;
+				#clock-cells = <1>;
+				compatible = "xlnx,versal-net-clk", "xlnx,versal-clk";
+				clocks = <&ref_clk>, <&ref_clk>, <&ref_clk>;
+				clock-names = "ref", "pl_alt_ref", "alt_ref";
+			};
+
+			versal_net_power: power-management { /* untested */
+				compatible = "xlnx,zynqmp-power";
+				interrupt-parent = <&gic>;
+				interrupts = <0 57 4>;
+				mboxes = <&ipi_mailbox_pmu1 0>,
+					 <&ipi_mailbox_pmu1 1>;
+				mbox-names = "tx", "rx";
+			};
+		};
+	};
+
+	zynqmp-ipi {
+		compatible = "xlnx,zynqmp-ipi-mailbox";
+		interrupt-parent = <&gic>;
+		interrupts = <0 57 4>;
+		xlnx,ipi-id = <2>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		ipi_mailbox_pmu1: mailbox@eb3f0440 {
+			compatible = "xlnx,zynqmp-ipi-dest-mailbox";
+			reg = <0 0xeb3f0440 0 0x20>,
+			      <0 0xeb3f0460 0 0x20>,
+			      <0 0xeb3f0280 0 0x20>,
+			      <0 0xeb3f02a0 0 0x20>;
+			reg-names = "local_request_region", "local_response_region",
+				    "remote_request_region", "remote_response_region";
+			#mbox-cells = <1>;
+			xlnx,ipi-id = <1>;
+		};
+	};
Quoted 8 lines

arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi line 106

Quoted 5 lines
arch/arm64/boot/dts/xilinx/versal-net-clk-ccf.dtsi new file +5 -0
+};
+
+&cpu0 {
+	clocks = <&versal_net_clk ACPU_0>;
+};

This structure is unusual and not great for readability. Imagine if we did a .dtsi for each provider with all the consumer properties.

At early stages for the silicon are all clocks enabled because link to coprocessor is not validated yet that's why that fixed clock DTSI happened. And because at this stage power management is not important (because everything is on by default) that properties are not listed. That's why historially we had two files. One with fixed clock and second (with wrong ccf suffix) for firmware interface. In near future we are going to have (not for this cpu) also SCMI one.

And because reset/power domain requires firmware node they are placed to the same file.

And I will do that other changes in v2.

Thanks,
Michal