net: dsa: mt7530: add EcoNet EN7528 built-in switch support
Subsystems (6)
cover net: dsa: mt7530: add EcoNet EN7528 built-in switch support
The EcoNet EN7528 is a MIPS SoC whose platform support is already upstream. It integrates an MT7530 switch, memory-mapped like the built-in switches of the MediaTek MT7988 and Airoha EN7581/AN7583 SoCs, but with a true MT7530 core, four Gigabit PHYs on ports 1-4 and a CPU port at a fixed 1000 Mbps full duplex link.
Patch 1 documents the compatible, patch 2 adds the driver support.
Ahmed Naseef (2):
dt-bindings: net: dsa: mediatek,mt7530: add econet,en7528-switch
net: dsa: mt7530: add EN7528 support
.../bindings/net/dsa/mediatek,mt7530.yaml | 5 ++ drivers/net/dsa/mt7530-mmio.c | 1 + drivers/net/dsa/mt7530.c | 56 ++++++++++++++++++- drivers/net/dsa/mt7530.h | 1 + 4 files changed, 62 insertions(+), 1 deletion(-)
base-commit: fe3e786ef4eb6e47d2901f568a27bd920477bbe9
Signature · 1 line
2.34.1
PATCH 1/2 dt-bindings: net: dsa: mediatek,mt7530: add econet,en7528-switch
The EcoNet EN7528 MIPS SoC integrates an MT7530 Gigabit switch, memory-mapped in the SoC register space like the built-in switches of the MediaTek MT7988 and Airoha EN7581/AN7583 SoCs. Its four user ports are connected to integrated Gigabit PHYs and its CPU port is connected internally to the SoC Ethernet MAC.
Add the econet,en7528-switch compatible, with the same constraints as the other built-in switches.
--- .../devicetree/bindings/net/dsa/mediatek,mt7530.yaml | 5 +++++ 1 file changed, 5 insertions(+)
Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +5 -0
@@ -100,6 +100,10 @@ properties: Built-in switch of the Airoha AN7583 SoC const: airoha,an7583-switch + - description: + Built-in switch of the EcoNet EN7528 SoC + const: econet,en7528-switch + reg: maxItems: 1
@@ -318,6 +322,7 @@ allOf: - mediatek,mt7988-switch - airoha,en7581-switch - airoha,an7583-switch + - econet,en7528-switch then: $ref: "#/$defs/builtin-dsa-port" properties:
Signature · 1 line
2.34.1
Re: [PATCH net-next 1/2] dt-bindings: net: dsa: mediatek,mt7530: add econet,en7528-switch
Quoted 5 lines · Ahmed Naseef
The EcoNet EN7528 MIPS SoC integrates an MT7530 Gigabit switch, memory-mapped in the SoC register space like the built-in switches of the MediaTek MT7988 and Airoha EN7581/AN7583 SoCs. Its four user ports are connected to integrated Gigabit PHYs and its CPU port is connected internally to the SoC Ethernet MAC.
Please note what actually makes this different from the other devices such that it cannot use a fallback. It's not clear from this description if the described features are shared with other devices or unique.
pw-bot: changes-requested
Thanks,
Conor.
Quoted 35 lines
Add the econet,en7528-switch compatible, with the same constraints as the other built-in switches.
Signed-off-by Ahmed Naseef <[email protected]>--- .../devicetree/bindings/net/dsa/mediatek,mt7530.yaml | 5 +++++ 1 file changed, 5 insertions(+)Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +5
-0@@ -100,6 +100,10 @@ properties: Built-in switch of the Airoha AN7583 SoC const: airoha,an7583-switch + - description: + Built-in switch of the EcoNet EN7528 SoC + const: econet,en7528-switch + reg: maxItems: 1@@ -318,6 +322,7 @@ allOf: - mediatek,mt7988-switch - airoha,en7581-switch - airoha,an7583-switch + - econet,en7528-switch then: $ref: "#/$defs/builtin-dsa-port" properties:Signature · 1 line
2.34.1
PATCH 2/2 net: dsa: mt7530: add EN7528 support
In reply to Ahmed NaseefThe EcoNet EN7528 SoC integrates an MT7530 switch (the chip revision register reads 0x7530), memory-mapped in the SoC register space and reached through the same MMIO glue used for the built-in switches of the MediaTek MT7988 and Airoha EN7581/AN7583 SoCs. Its reset sequence and its PHY indirect access registers are the same as on those switches, so add an ID_EN7528 variant bound with the "econet,en7528-switch" compatible, reusing mt7988_setup() and the indirect PHY accessors.
The switch core, however, is an MT7530 and not an MT7531 derivative: it has no MT7531 CFC register, and the CPU port to trap frames to is set through the MT7530-style CPU_EN / CPU_PORT fields of the MFC register, so add it to the MT7530 handling in mt753x_conduit_state_change(). For the same reason the MT7530 mirror and force-mode register layouts already apply to it as the default of the MT753X_*() macros.
The four user ports (1-4) are connected to integrated Gigabit PHYs at MDIO addresses 9-12 of the switch internal MDIO bus. The CPU port (port
6) is connected to the SoC Ethernet MAC at a fixed 1000 Mbps full duplex link, so the port capabilities cannot be shared with the MT7988 and EN7581 switches, whose CPU ports run at 10 Gbps.
The LAN GPHYs advertise EEE by default, but negotiating EEE with some link partners results in an unstable link with dropped frames. Disable EEE advertisement on them at setup time, like mt7531_setup() does for the MT7531 switch PHYs.
--- drivers/net/dsa/mt7530-mmio.c | 1 + drivers/net/dsa/mt7530.c | 56 ++++++++++++++++++++++++++++++++++- drivers/net/dsa/mt7530.h | 1 + 3 files changed, 57 insertions(+), 1 deletion(-)
drivers/net/dsa/mt7530-mmio.c +1 -0
@@ -13,6 +13,7 @@static const struct of_device_id mt7988_of_match[] = { { .compatible ="airoha,an7583-switch" , .data = &mt753x_table[ID_AN7583 ], }, { .compatible ="airoha,en7581-switch" , .data = &mt753x_table[ID_EN7581 ], }, + { .compatible ="econet,en7528-switch" , .data = &mt753x_table[ID_EN7528 ], }, { .compatible ="mediatek,mt7988-switch" , .data = &mt753x_table[ID_MT7988 ], }, {/* sentinel */ }, };
drivers/net/dsa/mt7530.c +55 -1
89 lines not on this page · raw message
drivers/net/dsa/mt7530.h +1 -0
@@ -21,6 +21,7 @@ enum mt753x_id {ID_MT7988 =3 ,ID_EN7581 =4 ,ID_AN7583 =5 , + ID_EN7528 = 6, };#define NUM_TRGMII_CTRL 5
Signature · 1 line
2.34.1
Andrew Lunn
maintainerRe: [PATCH net-next 2/2] net: dsa: mt7530: add EN7528 support
drivers/net/dsa/mt7530.c static int mt7988_setup(struct dsa_switch *ds) · line 3388
Quoted 11 lines
drivers/net/dsa/mt7530.c +11
-0+/* The EN7528 LAN GPHYs advertise EEE by default, but negotiating EEE +* with common link partners (e.g. Realtek GbE NICs) results in an +* unstable link with dropped frames. Disable EEE advertisement on +* them. +*/ +if (priv->id ==ID_EN7528 ) +for (i =EN7528_GPHY_BASE ; + i <EN7528_GPHY_BASE +EN7528_NUM_GPHYS ; i++) +mt7531_ind_c45_phy_write (priv, i,MDIO_MMD_AN , +MDIO_AN_EEE_ADV ,0 ); +
The problem with this is, you can still use ethtool to enable EEE.
Please look at phylink_bringup_phy(), where it calls phy_disable_eee().
Andrew
---
pw-bot: cr
Re: [PATCH net-next 2/2] net: dsa: mt7530: add EN7528 support
Quoted 14 lines · Andrew Lunn
drivers/net/dsa/mt7530.c static int mt7988_setup(struct dsa_switch *ds) · line 3388
Quoted 11 lines
drivers/net/dsa/mt7530.c +11
-0+/* The EN7528 LAN GPHYs advertise EEE by default, but negotiating EEE +* with common link partners (e.g. Realtek GbE NICs) results in an +* unstable link with dropped frames. Disable EEE advertisement on +* them. +*/ +if (priv->id ==ID_EN7528 ) +for (i =EN7528_GPHY_BASE ; + i <EN7528_GPHY_BASE +EN7528_NUM_GPHYS ; i++) +mt7531_ind_c45_phy_write (priv, i,MDIO_MMD_AN , +MDIO_AN_EEE_ADV ,0 ); +The problem with this is, you can still use ethtool to enable EEE.
Quoted 2 lines
Please look at
phylink_bringup_phy(), where it callsphy_disable_eee().
Thanks, you are right , the register write is the wrong approach.
While looking at phylink_bringup_phy(), I noticed that the mt7530 driver sets config->lpi_capabilities but never config->lpi_interfaces. Since
mac_supports_eee = mac_supports_eee_ops && lpi_capabilities &&
!phy_interface_empty(lpi_interfaces);that leaves mac_supports_eee false on all mt753x ports, so phylink already takes the phy_disable_eee() path for every port and phylink_ethtool_set_eee() returns -EOPNOTSUPP. On the EN7528 I confirmed "ethtool --set-eee lan1 eee on" reports "Not supported", so EEE cannot currently be enabled from userspace on this driver at all. That looks like it unintentionally undid the "EEE can now be enabled using ethtool" behaviour from commit 06dfcd4098cf ("net: dsa: mt7530:
fix enabling EEE on MT7531 switch on all boards"), starting with commit 9cf21773f535 ("net: dsa: mt7530: convert to phylink managed EEE"). That is pre-existing and outside the scope of this series, just flagging it.
For the EN7528 the GPHYs report EEE capability, but the link stops passing traffic once LPI is entered, so EEE must stay off regardless. The register loop cannot express that to phylib, as you noted.
My plan for v2 is to not advertise lpi_capabilities for the EN7528, so mac_supports_eee stays false by design and phylink disables EEE on these PHYs via phy_disable_eee() and refuses to enable it from userspace. Does that sound like the right approach to you, or would you prefer it handled differently?
Thanks,
Ahmed
Quoted 5 lines
Andrew
---
pw-bot: cr
Andrew Lunn
maintainerRe: [PATCH net-next 2/2] net: dsa: mt7530: add EN7528 support
Quoted 5 lines
My plan for v2 is to not advertise
lpi_capabilitiesfor the EN7528, somac_supports_eeestays false by design and phylink disables EEE on these PHYs viaphy_disable_eee()and refuses to enable it from userspace. Does that sound like the right approach to you, or would you prefer it handled differently?
That sounds like the correct thing to do.
Andrew
[email protected]
AI reviewRe: [PATCH net-next 2/2] net: dsa: mt7530: add EN7528 support
In reply to Ahmed NaseefThank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
New issues:
- [Medium] ID_EN7528 writes to an MT7531-specific register, MT7531_DBG_CNT(i), inside mt7531_setup_common().
- [Medium] Missing stabilization delay after hardware reset of PHYs before issuing MDIO writes.
Pre-existing issues:
- [High] ID_AN7583 incorrectly falls back to MT7530_MIRROR_EN (BIT 3) while using the MT7531_CFC register format, failing port mirroring and corrupting CPU packet forwarding logic.
- [High] ID_EN7581 and ID_AN7583 are missing from the MT753X_FORCE_MODE macro, causing them to use the MT7530 bitmask instead of the MT7531 bitmask. --
--- Patch [2]: [PATCH net-next 2/2] net: dsa: mt7530: add EN7528 support --- commit 6e316acbfa461fc0e2739fe9d461c2511b9c012c
Author: Ahmed Naseef <[email protected]>
net: dsa: mt7530: add EN7528 support
This patch adds support for the EcoNet EN7528 SoC switch. It introduces the ID_EN7528 variant, reusing mt7988_setup() and indirect PHY accessors, while handling the switch core as an MT7530 derivative rather than MT7531.
Quoted 4 lines
drivers/net/dsa/mt7530.c +0
-0
[ ... ]
Quoted 4 lines
drivers/net/dsa/mt7530.c +0
-0@@ -3342,6 +3375,17 @@ static int mt7988_setup(struct dsa_switch *ds)/* Reset the switch PHYs */ mt7530_write (priv,MT7530_SYS_CTRL ,SYS_CTRL_PHY_RST );
drivers/net/dsa/mt7530.c static int mt7988_setup(struct dsa_switch *ds) · line 3387
Quoted 10 lines
drivers/net/dsa/mt7530.c +10
-0+/* The EN7528 LAN GPHYs advertise EEE by default, but negotiating EEE +* with common link partners (e.g. Realtek GbE NICs) results in an +* unstable link with dropped frames. Disable EEE advertisement on +* them. +*/ +if (priv->id ==ID_EN7528 ) +for (i =EN7528_GPHY_BASE ; + i <EN7528_GPHY_BASE +EN7528_NUM_GPHYS ; i++) +mt7531_ind_c45_phy_write (priv, i,MDIO_MMD_AN , +MDIO_AN_EEE_ADV ,0 );
[Severity: Medium]
Does this sequence need a stabilization delay before issuing MDIO writes?
The switch PHYs are hardware reset via SYS_CTRL_PHY_RST just before this, and hardware PHYs typically require a few milliseconds to exit the reset state and initialize their management logic.
Could issuing MDIO C45 writes immediately after asserting the reset result in the PHYs ignoring the transaction or the MDIO controller timing out?
drivers/net/dsa/mt7530.c static int mt7988_setup(struct dsa_switch *ds) · line 3389
Quoted 2 lines
drivers/net/dsa/mt7530.c +0
-0return mt7531_setup_common (ds);
[Severity: Medium]
Does mt7531_setup_common() write to MT7531-specific registers that shouldn't be accessed by the EN7528?
The commit message states that the EN7528 switch core is an MT7530 derivative and not an MT7531 derivative. However, mt7988_setup() returns by calling mt7531_setup_common(), which executes:
mt7531_setup_common() {
...
for (i = 0; i < priv->ds->num_ports; i++) {
...
mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);Could writing MT7531_DIS_CLR to the MT7531_DBG_CNT(i) offset on an MT7530 derivative cause hardware errors or state corruption?
Quoted 6 lines
drivers/net/dsa/mt7530.c +0
-0}drivers/net/dsa/mt7530.h +0
-0
[ ... ]
drivers/net/dsa/mt7530.h enum mt753x_id { · line 24
Quoted 5 lines
drivers/net/dsa/mt7530.h +1
-0@@ -21,6 +21,7 @@ enum mt753x_id {ID_MT7988 =3 ,ID_EN7581 =4 ,ID_AN7583 =5 , + ID_EN7528 = 6,
[Severity: High]
This isn't a bug introduced by this patch, but are ID_AN7583 and ID_EN7581 missing from the MT753X_MIRROR_EN and MT753X_FORCE_MODE macros?
In drivers/net/dsa/mt7530.h, MT753X_MIRROR_EN is defined as:
#define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \
id == ID_MT7988 || \
id == ID_EN7581) ? \
MT7531_MIRROR_EN : MT7530_MIRROR_EN)Because ID_AN7583 is omitted, it falls back to MT7530_MIRROR_EN (BIT 3). When mt753x_port_mirror_add() uses the MT7531_CFC register format for ID_AN7583, it applies BIT 3. In MT7531_CFC, BIT 3 is part of MT7531_CPU_PMAP_MASK, which controls CPU packet forwarding logic.
Does this break port mirroring and corrupt the CPU forward control for ID_AN7583?
Similarly, MT753X_FORCE_MODE is defined as:
#define MT753X_FORCE_MODE(id) ((id == ID_MT7531 || \
id == ID_MT7988) ? \
MT7531_FORCE_MODE_MASK : \
MT7530_FORCE_MODE)Both ID_EN7581 and ID_AN7583 are missing here. When mt7531_setup_common() attempts to force all port links down during setup, it applies MT7530_FORCE_MODE (BIT 15) instead of MT7531_FORCE_MODE_MASK.
Does this fail to correctly disable the port links during switch initialization?
Quoted 3 lines
drivers/net/dsa/mt7530.h +0
-0};#define NUM_TRGMII_CTRL 5
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2