To: [email protected]
---
V2: Add compatible string for SN65DSI84, since this is now tested on it
V3: - Add 0x2c as valid i2c address
- Switch to schemas/graph.yaml
- Constraint data-lanes to <1>, <1 2>, <1 2 3>, <1 2 3 4> only
- Indent example by 4 spaces
- Handle dual-link LVDS with two ports and describe the second DSI channel-B port as well. Based on the register defaults of DSI83 and DSI84, it is likely that the LVDS-channel-B and DSI-channel-B hardware is present in all the chips, so just reuse port@0 and 2 for DSI83, port@0,2,3 for DSI84 and all of 0,1,2,3 for DSI85 when that is supported
V4: - Fix typo in port@3 description
- Add RB from Linus Walleij
- Replace oneOf: and const with enum:
- ref /schemas/media/video-interfaces.yaml#
- Drop empty endpoint: and properties:
V5: - Add RB from Rob Herring
V6: - No change

---
 .../bindings/display/bridge/ti,sn65dsi83.yaml | 159 ++++++++++++++++++
 1 file changed, 159 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml

Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml new file +159 -0

new file mode 100644
index 000000000000..d101233ae17f
@@ -0,0 +1,159 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi83.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip
+
+maintainers:
+  - Marek Vasut <[email protected]>
+
+description: |
+  Texas Instruments SN65DSI83 1x Single-link MIPI DSI
+  to 1x Single-link LVDS
+  https://www.ti.com/lit/gpn/sn65dsi83
+  Texas Instruments SN65DSI84 1x Single-link MIPI DSI
+  to 1x Dual-link or 2x Single-link LVDS
+  https://www.ti.com/lit/gpn/sn65dsi84
+
+properties:
+  compatible:
+    enum:
+      - ti,sn65dsi83
+      - ti,sn65dsi84
+
+  reg:
+    enum:
+      - 0x2c
+      - 0x2d
+
+  enable-gpios:
+    maxItems: 1
+    description: GPIO specifier for bridge_en pin (active high).
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Video port for MIPI DSI Channel-A input
+
+        properties:
+          endpoint:
+            $ref: /schemas/media/video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                description: array of physical DSI data lane indexes.
+                minItems: 1
+                maxItems: 4
+                items:
+                  - const: 1
+                  - const: 2
+                  - const: 3
+                  - const: 4
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Video port for MIPI DSI Channel-B input
+
+        properties:
+          endpoint:
+            $ref: /schemas/media/video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                description: array of physical DSI data lane indexes.
+                minItems: 1
+                maxItems: 4
+                items:
+                  - const: 1
+                  - const: 2
+                  - const: 3
+                  - const: 4
+
+      port@2:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Video port for LVDS Channel-A output (panel or bridge).
+
+      port@3:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Video port for LVDS Channel-B output (panel or bridge).
+
+    required:
+      - port@0
+      - port@2
+
+required:
+  - compatible
+  - reg
+  - enable-gpios
+  - ports
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: ti,sn65dsi83
+    then:
+      properties:
+        ports:
+          properties:
+            port@1: false
+            port@3: false
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: ti,sn65dsi84
+    then:
+      properties:
+        ports:
+          properties:
+            port@1: false
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        bridge@2d {
+            compatible = "ti,sn65dsi83";
+            reg = <0x2d>;
+
+            enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+
+                    endpoint {
+                        remote-endpoint = <&dsi0_out>;
+                        data-lanes = <1 2 3 4>;
+                    };
+                };
+
+                port@2 {
+                    reg = <2>;
+
+                    endpoint {
+                        remote-endpoint = <&panel_in_lvds>;
+                    };
+                };
+            };
+        };
+    };

Signature · 1 line

2.30.2

Marek Vasut

author

2021-06-07 17:43 UTC #1 lore raw

PATCH v6 2/2 drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver

Add driver for TI SN65DSI83 Single-link DSI to Single-link LVDS bridge and TI SN65DSI84 Single-link DSI to Dual-link or 2x Single-link LVDS bridge. TI SN65DSI85 is unsupported due to lack of hardware to test on, but easy to add.

The driver operates the chip via I2C bus. Currently the LVDS clock are always derived from DSI clock lane, which is the usual mode of operation. Support for clock from external oscillator is not implemented, but it is easy to add if ever needed. Only RGB888 pixel format is implemented, the LVDS666 is not supported, but could be added if needed.

Reviewed-by Linus Walleij <[email protected]>

Reviewed-by Frieder Schrempf <[email protected]>

Tested-by Frieder Schrempf <[email protected]>

Tested-by Adam Ford <[email protected]>

Signed-off-by Marek Vasut <[email protected]>

Cc Douglas Anderson <[email protected]>

Cc Jagan Teki <[email protected]>

Cc Laurent Pinchart <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Loic Poulain <[email protected]>

Cc Philippe Schenker <[email protected]>

Cc Sam Ravnborg <[email protected]>

Cc Stephen Boyd <[email protected]>

Cc Valentin Raevsky <[email protected]>

To: [email protected]
---
V2: - Use dev_err_probe()
- Set REG_RC_RESET as volatile
- Wait for PLL stabilization by polling REG_RC_LVDS_PLL
- Use ctx->mode = *adj instead of *mode in sn65dsi83_mode_set
- Add tested DSI84 support in dual-link mode
- Correctly set VCOM
- Fill in missing DSI CHB and LVDS CHB bits from DSI84 and DSI85 datasheets, with that all the reserved bits make far more sense as the DSI83 and DSI84 seems to be reduced version of DSI85
V3: - Handle the dual-link LVDS with two port panel or bridge
V4: - Add RB from Linus Walleij
- Rename REG_DSI_LANE_LVDS_LINK_CFG_DUAL to REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE and fill in the remaining DSI link options from DSI85 datasheet. DSI85 can do dual and 2x single DSI mode, but DSI85 is currently unsupported by the driver. Add a comment about DSI85, so that all the places which need to be adjusted for DSI85 are marked accordingly.
- Add REG_DSI_LANE_LEFT_RIGHT_PIXELS bit for DSI
- Add handling for JEIDA18/JEIDA24/SPWG24 LVDS formats. Use SPWG24 as fallback on output bridges until they are all fixed.
- Patch DSI bus format to fixed RGB888_1X24 instead of passing through the LVDS bus format.
V5: - Move bus format patching to mode_fixup
- Use cpu_to_le16() to guarantee endianness in regmap_bulk_write()
V6: - Cast of_device_get_match_data() output to uintptr_t first

---
 drivers/gpu/drm/bridge/Kconfig        |  10 +
 drivers/gpu/drm/bridge/Makefile       |   1 +
 drivers/gpu/drm/bridge/ti-sn65dsi83.c | 709 ++++++++++++++++++++++++++
 3 files changed, 720 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi83.c

drivers/gpu/drm/bridge/Kconfig +10 -0

index 8e15b387e013..1df1704262d0 100644
@@ -300,6 +300,16 @@ config DRM_TI_TFP410
 	help
 	  Texas Instruments TFP410 DVI/HDMI Transmitter driver
 
+config DRM_TI_SN65DSI83
+	tristate "TI SN65DSI83 and SN65DSI84 DSI to LVDS bridge"
+	depends on OF
+	select DRM_KMS_HELPER
+	select REGMAP_I2C
+	select DRM_PANEL
+	select DRM_MIPI_DSI
+	help
+	  Texas Instruments SN65DSI83 and SN65DSI84 DSI to LVDS Bridge driver
+
 config DRM_TI_SN65DSI86
 	tristate "TI SN65DSI86 DSI to eDP bridge"
 	depends on OF

drivers/gpu/drm/bridge/Makefile +1 -0

index e2218e40b3b3..61302be291af 100644
@@ -25,6 +25,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
 obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o
 obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o
 obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
+obj-$(CONFIG_DRM_TI_SN65DSI83) += ti-sn65dsi83.o
 obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
 obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
 obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o

drivers/gpu/drm/bridge/ti-sn65dsi83.c new file +709 -0

709 lines not on this page · raw message

Signature · 1 line

2.30.2

Neil Armstrong

2021-06-08 08:10 UTC #2 lore raw

Re: [PATCH V6 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver

Hi,

Quoted 52 lines · Marek Vasut

Add driver for TI SN65DSI83 Single-link DSI to Single-link LVDS bridge and TI SN65DSI84 Single-link DSI to Dual-link or 2x Single-link LVDS bridge. TI SN65DSI85 is unsupported due to lack of hardware to test on, but easy to add.
The driver operates the chip via I2C bus. Currently the LVDS clock are always derived from DSI clock lane, which is the usual mode of operation. Support for clock from external oscillator is not implemented, but it is easy to add if ever needed. Only RGB888 pixel format is implemented, the LVDS666 is not supported, but could be added if needed.
Reviewed-by Linus Walleij <[email protected]>
Reviewed-by Frieder Schrempf <[email protected]>
Tested-by Frieder Schrempf <[email protected]>
Tested-by Adam Ford <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Douglas Anderson <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Laurent Pinchart <[email protected]>
Cc Linus Walleij <[email protected]>
Cc Loic Poulain <[email protected]>
Cc Philippe Schenker <[email protected]>
Cc Sam Ravnborg <[email protected]>
Cc Stephen Boyd <[email protected]>
Cc Valentin Raevsky <[email protected]>
To: [email protected]
---
V2: - Use dev_err_probe()
- Set REG_RC_RESET as volatile
- Wait for PLL stabilization by polling REG_RC_LVDS_PLL
- Use ctx->mode = *adj instead of *mode in sn65dsi83_mode_set
- Add tested DSI84 support in dual-link mode
- Correctly set VCOM
- Fill in missing DSI CHB and LVDS CHB bits from DSI84 and DSI85 datasheets, with that all the reserved bits make far more sense as the DSI83 and DSI84 seems to be reduced version of DSI85
V3: - Handle the dual-link LVDS with two port panel or bridge
V4: - Add RB from Linus Walleij
- Rename REG_DSI_LANE_LVDS_LINK_CFG_DUAL to REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE and fill in the remaining DSI link options from DSI85 datasheet. DSI85 can do dual and 2x single DSI mode, but DSI85 is currently unsupported by the driver. Add a comment about DSI85, so that all the places which need to be adjusted for DSI85 are marked accordingly.
- Add REG_DSI_LANE_LEFT_RIGHT_PIXELS bit for DSI
- Add handling for JEIDA18/JEIDA24/SPWG24 LVDS formats. Use SPWG24 as fallback on output bridges until they are all fixed.
- Patch DSI bus format to fixed RGB888_1X24 instead of passing through the LVDS bus format.
V5: - Move bus format patching to mode_fixup
- Use cpu_to_le16() to guarantee endianness in regmap_bulk_write()
V6: - Cast of_device_get_match_data() output to uintptr_t first

Quoted 7 lines

---
 drivers/gpu/drm/bridge/Kconfig        |  10 +
 drivers/gpu/drm/bridge/Makefile       |   1 +
 drivers/gpu/drm/bridge/ti-sn65dsi83.c | 709 ++++++++++++++++++++++++++
 3 files changed, 720 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi83.c

Looks complete & well reviewed, LGTM

Rob, Laurent ? is it ok for you ?

Neil

Laurent Pinchart

reviewer

2021-06-08 08:22 UTC #3 lore raw

Re: [PATCH V6 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver

Hi Neil,

Quoted 61 lines · Neil Armstrong

Quoted 52 lines · Marek Vasut
Add driver for TI SN65DSI83 Single-link DSI to Single-link LVDS bridge and TI SN65DSI84 Single-link DSI to Dual-link or 2x Single-link LVDS bridge. TI SN65DSI85 is unsupported due to lack of hardware to test on, but easy to add.
The driver operates the chip via I2C bus. Currently the LVDS clock are always derived from DSI clock lane, which is the usual mode of operation. Support for clock from external oscillator is not implemented, but it is easy to add if ever needed. Only RGB888 pixel format is implemented, the LVDS666 is not supported, but could be added if needed.
Reviewed-by Linus Walleij <[email protected]>
Reviewed-by Frieder Schrempf <[email protected]>
Tested-by Frieder Schrempf <[email protected]>
Tested-by Adam Ford <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Douglas Anderson <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Laurent Pinchart <[email protected]>
Cc Linus Walleij <[email protected]>
Cc Loic Poulain <[email protected]>
Cc Philippe Schenker <[email protected]>
Cc Sam Ravnborg <[email protected]>
Cc Stephen Boyd <[email protected]>
Cc Valentin Raevsky <[email protected]>
To: [email protected]
---
V2: - Use dev_err_probe()
- Set REG_RC_RESET as volatile
- Wait for PLL stabilization by polling REG_RC_LVDS_PLL
- Use ctx->mode = *adj instead of *mode in sn65dsi83_mode_set
- Add tested DSI84 support in dual-link mode
- Correctly set VCOM
- Fill in missing DSI CHB and LVDS CHB bits from DSI84 and DSI85 datasheets, with that all the reserved bits make far more sense as the DSI83 and DSI84 seems to be reduced version of DSI85
V3: - Handle the dual-link LVDS with two port panel or bridge
V4: - Add RB from Linus Walleij
- Rename REG_DSI_LANE_LVDS_LINK_CFG_DUAL to REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE and fill in the remaining DSI link options from DSI85 datasheet. DSI85 can do dual and 2x single DSI mode, but DSI85 is currently unsupported by the driver. Add a comment about DSI85, so that all the places which need to be adjusted for DSI85 are marked accordingly.
- Add REG_DSI_LANE_LEFT_RIGHT_PIXELS bit for DSI
- Add handling for JEIDA18/JEIDA24/SPWG24 LVDS formats. Use SPWG24 as fallback on output bridges until they are all fixed.
- Patch DSI bus format to fixed RGB888_1X24 instead of passing through the LVDS bus format.
V5: - Move bus format patching to mode_fixup
- Use cpu_to_le16() to guarantee endianness in regmap_bulk_write()
V6: - Cast of_device_get_match_data() output to uintptr_t first
Quoted 7 lines
---
 drivers/gpu/drm/bridge/Kconfig        |  10 +
 drivers/gpu/drm/bridge/Makefile       |   1 +
 drivers/gpu/drm/bridge/ti-sn65dsi83.c | 709 ++++++++++++++++++++++++++
 3 files changed, 720 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi83.c

Quoted 3 lines

Looks complete & well reviewed, LGTM
Rob, Laurent ? is it ok for you ?

No objection.

Signature · 3 lines

Regards,

Laurent Pinchart

Robert Foss

2021-06-08 08:52 UTC #4 lore raw

Re: [PATCH V6 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver

In reply to Neil Armstrong

Hey Neil,

Quoted 64 lines · Neil Armstrong

Hi,
Quoted 52 lines · Marek Vasut
Add driver for TI SN65DSI83 Single-link DSI to Single-link LVDS bridge and TI SN65DSI84 Single-link DSI to Dual-link or 2x Single-link LVDS bridge. TI SN65DSI85 is unsupported due to lack of hardware to test on, but easy to add.
The driver operates the chip via I2C bus. Currently the LVDS clock are always derived from DSI clock lane, which is the usual mode of operation. Support for clock from external oscillator is not implemented, but it is easy to add if ever needed. Only RGB888 pixel format is implemented, the LVDS666 is not supported, but could be added if needed.
Reviewed-by Linus Walleij <[email protected]>
Reviewed-by Frieder Schrempf <[email protected]>
Tested-by Frieder Schrempf <[email protected]>
Tested-by Adam Ford <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Douglas Anderson <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Laurent Pinchart <[email protected]>
Cc Linus Walleij <[email protected]>
Cc Loic Poulain <[email protected]>
Cc Philippe Schenker <[email protected]>
Cc Sam Ravnborg <[email protected]>
Cc Stephen Boyd <[email protected]>
Cc Valentin Raevsky <[email protected]>
To: [email protected]
---
V2: - Use dev_err_probe()
- Set REG_RC_RESET as volatile
- Wait for PLL stabilization by polling REG_RC_LVDS_PLL
- Use ctx->mode = *adj instead of *mode in sn65dsi83_mode_set
- Add tested DSI84 support in dual-link mode
- Correctly set VCOM
- Fill in missing DSI CHB and LVDS CHB bits from DSI84 and DSI85 datasheets, with that all the reserved bits make far more sense as the DSI83 and DSI84 seems to be reduced version of DSI85
V3: - Handle the dual-link LVDS with two port panel or bridge
V4: - Add RB from Linus Walleij
- Rename REG_DSI_LANE_LVDS_LINK_CFG_DUAL to REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE and fill in the remaining DSI link options from DSI85 datasheet. DSI85 can do dual and 2x single DSI mode, but DSI85 is currently unsupported by the driver. Add a comment about DSI85, so that all the places which need to be adjusted for DSI85 are marked accordingly.
- Add REG_DSI_LANE_LEFT_RIGHT_PIXELS bit for DSI
- Add handling for JEIDA18/JEIDA24/SPWG24 LVDS formats. Use SPWG24 as fallback on output bridges until they are all fixed.
- Patch DSI bus format to fixed RGB888_1X24 instead of passing through the LVDS bus format.
V5: - Move bus format patching to mode_fixup
- Use cpu_to_le16() to guarantee endianness in regmap_bulk_write()
V6: - Cast of_device_get_match_data() output to uintptr_t first
Quoted 7 lines
---
 drivers/gpu/drm/bridge/Kconfig        |  10 +
 drivers/gpu/drm/bridge/Makefile       |   1 +
 drivers/gpu/drm/bridge/ti-sn65dsi83.c | 709 ++++++++++++++++++++++++++
 3 files changed, 720 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi83.c

Quoted 3 lines

Looks complete & well reviewed, LGTM
Rob, Laurent ? is it ok for you ?

This does look like it is ready. I was just about to merge it, but found some checkpatch --strict formatting warnings. Do you mind fixing those in a real quick v7?

Marek Vasut

author

2021-06-08 09:35 UTC #5 lore raw

Re: [PATCH V6 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver

Quoted 67 lines · Robert Foss

Hey Neil,
Quoted 64 lines · Neil Armstrong
Hi,
Quoted 59 lines · Marek Vasut
Add driver for TI SN65DSI83 Single-link DSI to Single-link LVDS bridge and TI SN65DSI84 Single-link DSI to Dual-link or 2x Single-link LVDS bridge. TI SN65DSI85 is unsupported due to lack of hardware to test on, but easy to add.
The driver operates the chip via I2C bus. Currently the LVDS clock are always derived from DSI clock lane, which is the usual mode of operation. Support for clock from external oscillator is not implemented, but it is easy to add if ever needed. Only RGB888 pixel format is implemented, the LVDS666 is not supported, but could be added if needed.
Reviewed-by Linus Walleij <[email protected]>
Reviewed-by Frieder Schrempf <[email protected]>
Tested-by Frieder Schrempf <[email protected]>
Tested-by Adam Ford <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Douglas Anderson <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Laurent Pinchart <[email protected]>
Cc Linus Walleij <[email protected]>
Cc Loic Poulain <[email protected]>
Cc Philippe Schenker <[email protected]>
Cc Sam Ravnborg <[email protected]>
Cc Stephen Boyd <[email protected]>
Cc Valentin Raevsky <[email protected]>
To: [email protected]
---
V2: - Use dev_err_probe()
- Set REG_RC_RESET as volatile
- Wait for PLL stabilization by polling REG_RC_LVDS_PLL
- Use ctx->mode = *adj instead of *mode in sn65dsi83_mode_set
- Add tested DSI84 support in dual-link mode
- Correctly set VCOM
- Fill in missing DSI CHB and LVDS CHB bits from DSI84 and DSI85 datasheets, with that all the reserved bits make far more sense as the DSI83 and DSI84 seems to be reduced version of DSI85
V3: - Handle the dual-link LVDS with two port panel or bridge
V4: - Add RB from Linus Walleij
- Rename REG_DSI_LANE_LVDS_LINK_CFG_DUAL to REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE and fill in the remaining DSI link options from DSI85 datasheet. DSI85 can do dual and 2x single DSI mode, but DSI85 is currently unsupported by the driver. Add a comment about DSI85, so that all the places which need to be adjusted for DSI85 are marked accordingly.
- Add REG_DSI_LANE_LEFT_RIGHT_PIXELS bit for DSI
- Add handling for JEIDA18/JEIDA24/SPWG24 LVDS formats. Use SPWG24 as fallback on output bridges until they are all fixed.
- Patch DSI bus format to fixed RGB888_1X24 instead of passing through the LVDS bus format.
V5: - Move bus format patching to mode_fixup
- Use cpu_to_le16() to guarantee endianness in regmap_bulk_write()
V6: - Cast of_device_get_match_data() output to uintptr_t first
---
  drivers/gpu/drm/bridge/Kconfig        |  10 +
  drivers/gpu/drm/bridge/Makefile       |   1 +
  drivers/gpu/drm/bridge/ti-sn65dsi83.c | 709 ++++++++++++++++++++++++++
  3 files changed, 720 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi83.c

Quoted 7 lines

Quoted 3 lines
Looks complete & well reviewed, LGTM
Rob, Laurent ? is it ok for you ?
This does look like it is ready. I was just about to merge it, but found some checkpatch --strict formatting warnings. Do you mind fixing those in a real quick v7?

We already discussed this thing with open parenthesis alignment before in one of the previous versions of this series, and the readability of the driver was worse with that change in place.

Is this change now a blocker ?

Robert Foss

2021-06-08 09:42 UTC #6 lore raw

Re: [PATCH V6 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver

Quoted 77 lines · Marek Vasut

Quoted 67 lines · Robert Foss
Hey Neil,
Quoted 64 lines · Neil Armstrong
Hi,
Quoted 59 lines · Marek Vasut
Add driver for TI SN65DSI83 Single-link DSI to Single-link LVDS bridge and TI SN65DSI84 Single-link DSI to Dual-link or 2x Single-link LVDS bridge. TI SN65DSI85 is unsupported due to lack of hardware to test on, but easy to add.
The driver operates the chip via I2C bus. Currently the LVDS clock are always derived from DSI clock lane, which is the usual mode of operation. Support for clock from external oscillator is not implemented, but it is easy to add if ever needed. Only RGB888 pixel format is implemented, the LVDS666 is not supported, but could be added if needed.
Reviewed-by Linus Walleij <[email protected]>
Reviewed-by Frieder Schrempf <[email protected]>
Tested-by Frieder Schrempf <[email protected]>
Tested-by Adam Ford <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Douglas Anderson <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Laurent Pinchart <[email protected]>
Cc Linus Walleij <[email protected]>
Cc Loic Poulain <[email protected]>
Cc Philippe Schenker <[email protected]>
Cc Sam Ravnborg <[email protected]>
Cc Stephen Boyd <[email protected]>
Cc Valentin Raevsky <[email protected]>
To: [email protected]
---
V2: - Use dev_err_probe()
- Set REG_RC_RESET as volatile
- Wait for PLL stabilization by polling REG_RC_LVDS_PLL
- Use ctx->mode = *adj instead of *mode in sn65dsi83_mode_set
- Add tested DSI84 support in dual-link mode
- Correctly set VCOM
- Fill in missing DSI CHB and LVDS CHB bits from DSI84 and DSI85 datasheets, with that all the reserved bits make far more sense as the DSI83 and DSI84 seems to be reduced version of DSI85
V3: - Handle the dual-link LVDS with two port panel or bridge
V4: - Add RB from Linus Walleij
- Rename REG_DSI_LANE_LVDS_LINK_CFG_DUAL to REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE and fill in the remaining DSI link options from DSI85 datasheet. DSI85 can do dual and 2x single DSI mode, but DSI85 is currently unsupported by the driver. Add a comment about DSI85, so that all the places which need to be adjusted for DSI85 are marked accordingly.
- Add REG_DSI_LANE_LEFT_RIGHT_PIXELS bit for DSI
- Add handling for JEIDA18/JEIDA24/SPWG24 LVDS formats. Use SPWG24 as fallback on output bridges until they are all fixed.
- Patch DSI bus format to fixed RGB888_1X24 instead of passing through the LVDS bus format.
V5: - Move bus format patching to mode_fixup
- Use cpu_to_le16() to guarantee endianness in regmap_bulk_write()
V6: - Cast of_device_get_match_data() output to uintptr_t first
---
  drivers/gpu/drm/bridge/Kconfig        |  10 +
  drivers/gpu/drm/bridge/Makefile       |   1 +
  drivers/gpu/drm/bridge/ti-sn65dsi83.c | 709 ++++++++++++++++++++++++++
  3 files changed, 720 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi83.c
Quoted 7 lines
Quoted 3 lines
Looks complete & well reviewed, LGTM
Rob, Laurent ? is it ok for you ?
This does look like it is ready. I was just about to merge it, but found some checkpatch --strict formatting warnings. Do you mind fixing those in a real quick v7?

Quoted 5 lines

We already discussed this thing with open parenthesis alignment before in one of the previous versions of this series, and the readability of the driver was worse with that change in place.
Is this change now a blocker ?

Ah, sorry I missed that part of the conversation. In that case no. Let's go ahead.

Marek Vasut

author

2021-06-08 09:44 UTC #7 lore raw

Re: [PATCH V6 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver

Quoted 78 lines · Robert Foss

Quoted 77 lines · Marek Vasut
Quoted 74 lines · Robert Foss
Hey Neil,
Quoted 64 lines · Neil Armstrong
Hi,
Quoted 52 lines · Marek Vasut
Add driver for TI SN65DSI83 Single-link DSI to Single-link LVDS bridge and TI SN65DSI84 Single-link DSI to Dual-link or 2x Single-link LVDS bridge. TI SN65DSI85 is unsupported due to lack of hardware to test on, but easy to add.
The driver operates the chip via I2C bus. Currently the LVDS clock are always derived from DSI clock lane, which is the usual mode of operation. Support for clock from external oscillator is not implemented, but it is easy to add if ever needed. Only RGB888 pixel format is implemented, the LVDS666 is not supported, but could be added if needed.
Reviewed-by Linus Walleij <[email protected]>
Reviewed-by Frieder Schrempf <[email protected]>
Tested-by Frieder Schrempf <[email protected]>
Tested-by Adam Ford <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Douglas Anderson <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Laurent Pinchart <[email protected]>
Cc Linus Walleij <[email protected]>
Cc Loic Poulain <[email protected]>
Cc Philippe Schenker <[email protected]>
Cc Sam Ravnborg <[email protected]>
Cc Stephen Boyd <[email protected]>
Cc Valentin Raevsky <[email protected]>
To: [email protected]
---
V2: - Use dev_err_probe()
- Set REG_RC_RESET as volatile
- Wait for PLL stabilization by polling REG_RC_LVDS_PLL
- Use ctx->mode = *adj instead of *mode in sn65dsi83_mode_set
- Add tested DSI84 support in dual-link mode
- Correctly set VCOM
- Fill in missing DSI CHB and LVDS CHB bits from DSI84 and DSI85 datasheets, with that all the reserved bits make far more sense as the DSI83 and DSI84 seems to be reduced version of DSI85
V3: - Handle the dual-link LVDS with two port panel or bridge
V4: - Add RB from Linus Walleij
- Rename REG_DSI_LANE_LVDS_LINK_CFG_DUAL to REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE and fill in the remaining DSI link options from DSI85 datasheet. DSI85 can do dual and 2x single DSI mode, but DSI85 is currently unsupported by the driver. Add a comment about DSI85, so that all the places which need to be adjusted for DSI85 are marked accordingly.
- Add REG_DSI_LANE_LEFT_RIGHT_PIXELS bit for DSI
- Add handling for JEIDA18/JEIDA24/SPWG24 LVDS formats. Use SPWG24 as fallback on output bridges until they are all fixed.
- Patch DSI bus format to fixed RGB888_1X24 instead of passing through the LVDS bus format.
V5: - Move bus format patching to mode_fixup
- Use cpu_to_le16() to guarantee endianness in regmap_bulk_write()
V6: - Cast of_device_get_match_data() output to uintptr_t first
Quoted 7 lines
---
   drivers/gpu/drm/bridge/Kconfig        |  10 +
   drivers/gpu/drm/bridge/Makefile       |   1 +
   drivers/gpu/drm/bridge/ti-sn65dsi83.c | 709 ++++++++++++++++++++++++++
   3 files changed, 720 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi83.c
Quoted 3 lines
Looks complete & well reviewed, LGTM
Rob, Laurent ? is it ok for you ?
This does look like it is ready. I was just about to merge it, but found some checkpatch --strict formatting warnings. Do you mind fixing those in a real quick v7?

Quoted 8 lines

Quoted 5 lines
We already discussed this thing with open parenthesis alignment before in one of the previous versions of this series, and the readability of the driver was worse with that change in place.
Is this change now a blocker ?
Ah, sorry I missed that part of the conversation. In that case no. Let's go ahead.

Nevermind, I sent V7. Apparently line over 80 is no longer an issue and line over 100 is, so the result doesn't look so bad. Pick the V7 please.

Robert Foss

Applied

2021-06-08 09:44 UTC #8 lore raw

Re: [PATCH V6 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver

In reply to Robert Foss

Pushed to drm-misc-next.

https://cgit.freedesktop.org/drm/drm-misc/commit/?id=db2aad0ffa7dfec31ddf715017a6ae57aa162045

Quoted 87 lines · Robert Foss

Quoted 77 lines · Marek Vasut
Quoted 67 lines · Robert Foss
Hey Neil,
Quoted 64 lines · Neil Armstrong
Hi,
Quoted 59 lines · Marek Vasut
Add driver for TI SN65DSI83 Single-link DSI to Single-link LVDS bridge and TI SN65DSI84 Single-link DSI to Dual-link or 2x Single-link LVDS bridge. TI SN65DSI85 is unsupported due to lack of hardware to test on, but easy to add.
The driver operates the chip via I2C bus. Currently the LVDS clock are always derived from DSI clock lane, which is the usual mode of operation. Support for clock from external oscillator is not implemented, but it is easy to add if ever needed. Only RGB888 pixel format is implemented, the LVDS666 is not supported, but could be added if needed.
Reviewed-by Linus Walleij <[email protected]>
Reviewed-by Frieder Schrempf <[email protected]>
Tested-by Frieder Schrempf <[email protected]>
Tested-by Adam Ford <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Douglas Anderson <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Laurent Pinchart <[email protected]>
Cc Linus Walleij <[email protected]>
Cc Loic Poulain <[email protected]>
Cc Philippe Schenker <[email protected]>
Cc Sam Ravnborg <[email protected]>
Cc Stephen Boyd <[email protected]>
Cc Valentin Raevsky <[email protected]>
To: [email protected]
---
V2: - Use dev_err_probe()
- Set REG_RC_RESET as volatile
- Wait for PLL stabilization by polling REG_RC_LVDS_PLL
- Use ctx->mode = *adj instead of *mode in sn65dsi83_mode_set
- Add tested DSI84 support in dual-link mode
- Correctly set VCOM
- Fill in missing DSI CHB and LVDS CHB bits from DSI84 and DSI85 datasheets, with that all the reserved bits make far more sense as the DSI83 and DSI84 seems to be reduced version of DSI85
V3: - Handle the dual-link LVDS with two port panel or bridge
V4: - Add RB from Linus Walleij
- Rename REG_DSI_LANE_LVDS_LINK_CFG_DUAL to REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE and fill in the remaining DSI link options from DSI85 datasheet. DSI85 can do dual and 2x single DSI mode, but DSI85 is currently unsupported by the driver. Add a comment about DSI85, so that all the places which need to be adjusted for DSI85 are marked accordingly.
- Add REG_DSI_LANE_LEFT_RIGHT_PIXELS bit for DSI
- Add handling for JEIDA18/JEIDA24/SPWG24 LVDS formats. Use SPWG24 as fallback on output bridges until they are all fixed.
- Patch DSI bus format to fixed RGB888_1X24 instead of passing through the LVDS bus format.
V5: - Move bus format patching to mode_fixup
- Use cpu_to_le16() to guarantee endianness in regmap_bulk_write()
V6: - Cast of_device_get_match_data() output to uintptr_t first
---
  drivers/gpu/drm/bridge/Kconfig        |  10 +
  drivers/gpu/drm/bridge/Makefile       |   1 +
  drivers/gpu/drm/bridge/ti-sn65dsi83.c | 709 ++++++++++++++++++++++++++
  3 files changed, 720 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi83.c
Quoted 7 lines
Quoted 3 lines
Looks complete & well reviewed, LGTM
Rob, Laurent ? is it ok for you ?
This does look like it is ready. I was just about to merge it, but found some checkpatch --strict formatting warnings. Do you mind fixing those in a real quick v7?
Quoted 5 lines
We already discussed this thing with open parenthesis alignment before in one of the previous versions of this series, and the readability of the driver was worse with that change in place.
Is this change now a blocker ?
Ah, sorry I missed that part of the conversation. In that case no. Let's go ahead.

Marek Vasut

author

2021-06-08 09:45 UTC #9 lore raw

Re: [PATCH V6 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver

Quoted 3 lines · Robert Foss

Pushed to drm-misc-next.
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=db2aad0ffa7dfec31ddf715017a6ae57aa162045

Well, then I'll just send a follow up patch.

Robert Foss

2021-06-08 09:45 UTC #10 lore raw

Re: [PATCH V6 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver

Quoted 7 lines · Marek Vasut

Quoted 3 lines · Robert Foss
Pushed to drm-misc-next.
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=db2aad0ffa7dfec31ddf715017a6ae57aa162045
Well, then I'll just send a follow up patch.

Thank you!

Marek Vasut

author

2021-06-08 09:54 UTC #11 lore raw

Re: [PATCH V6 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver

Quoted 10 lines · Robert Foss

Quoted 7 lines · Marek Vasut
Quoted 3 lines · Robert Foss
Pushed to drm-misc-next.
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=db2aad0ffa7dfec31ddf715017a6ae57aa162045
Well, then I'll just send a follow up patch.
Thank you!

See
[PATCH] drm/bridge: ti-sn65dsi83: Fix checkpatch --strict CHECKs posted to dri-devel