x86/cpufeatures.h: Enable A Few New AVX-512 Features
PATCH v3 1/1 x86/cpufeatures.h: Enable A Few New AVX-512 Features
From: Fenghua Yu <[email protected]>
A few new AVX-512 instruction groups/features are added in cpufeatures.h for enuermation: AVX512DQ, AVX512BW, and AVX512VL.
Clear the flags in fpu__xstate_clear_all_cpu_caps().
The specification for latest AVX-512 including the features can be found at
https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf
---
I don't enable the flags in kvm. Hopefully kvm guys can pick up the flags and enable them in kvm.
v3: Clear the flags in fpu__xstate_clear_all_cpu_caps().
v2: Change cpufeature.h to cpufeatures.h to use right file name in latest kernel.
arch/x86/include/asm/cpufeatures.h | 3 +++ arch/x86/kernel/fpu/xstate.c | 3 +++ 2 files changed, 6 insertions(+)
arch/x86/include/asm/cpufeatures.h +3 -0
@@ -220,6 +220,7 @@#define X86_FEATURE_CQM ( 9*32+12)/* Cache QoS Monitoring */ #define X86_FEATURE_MPX ( 9*32+14)/* Memory Protection Extension */ #define X86_FEATURE_AVX512F ( 9*32+16)/* AVX-512 Foundation */ +#define X86_FEATURE_AVX512DQ ( 9*32+17)/* AVX-512 DQ Instructions */ #define X86_FEATURE_RDSEED ( 9*32+18)/* The RDSEED instruction */ #define X86_FEATURE_ADX ( 9*32+19)/* The ADCX and ADOX instructions */ #define X86_FEATURE_SMAP ( 9*32+20)/* Supervisor Mode Access Prevention */
@@ -230,6 +231,8 @@#define X86_FEATURE_AVX512ER ( 9*32+27)/* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28)/* AVX-512 Conflict Detection */ #define X86_FEATURE_SHA_NI ( 9*32+29)/* SHA1/SHA256 Instruction Extensions */ +#define X86_FEATURE_AVX512BW ( 9*32+30)/* AVX-512 BW Instructions */ +#define X86_FEATURE_AVX512VL ( 9*32+31)/* AVX-512 Vector Lengths */ /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0)/* XSAVEOPT */
arch/x86/kernel/fpu/xstate.c +3 -0
@@ -59,6 +59,9 @@ void fpu__xstate_clear_all_cpu_caps(void)setup_clear_cpu_cap (X86_FEATURE_AVX512PF );setup_clear_cpu_cap (X86_FEATURE_AVX512ER );setup_clear_cpu_cap (X86_FEATURE_AVX512CD ); +setup_clear_cpu_cap (X86_FEATURE_AVX512DQ ); +setup_clear_cpu_cap (X86_FEATURE_AVX512BW ); +setup_clear_cpu_cap (X86_FEATURE_AVX512VL );setup_clear_cpu_cap (X86_FEATURE_MPX );setup_clear_cpu_cap (X86_FEATURE_XGETBV1 );setup_clear_cpu_cap (X86_FEATURE_PKU );
Signature · 1 line
2.5.0
arch/x86/include/asm/cpufeatures.h line 235
Quoted 3 lines · Fenghua Yu
arch/x86/include/asm/cpufeatures.h +3
-0+#define X86_FEATURE_AVX512DQ ( 9*32+17)/* AVX-512 DQ Instructions */ +#define X86_FEATURE_AVX512BW ( 9*32+30)/* AVX-512 BW Instructions */ +#define X86_FEATURE_AVX512VL ( 9*32+31)/* AVX-512 Vector Lengths */
Yeah, so I don't think it's obvious to people what the DQ/BW/VL extensions are precisely, so I changed the text to the following, a bit more verbose descriptions:
#define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ #define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */ #define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */
Please holler if you disagree!
Thanks,
Ingo
tip-bot for Fenghua Yu
merge bot[tip:x86/asm] x86/cpufeature: Enable new AVX-512 features
In reply to Fenghua Yux86/cpufeature: Enable new AVX-512 features
Commit-ID: d05004944206cbbf1c453e179768163731c7c6f1 Gitweb: http://git.kernel.org/tip/d05004944206cbbf1c453e179768163731c7c6f1 Author: Fenghua Yu <[email protected]> AuthorDate: Thu, 10 Mar 2016 19:38:18 -0800 Committer: Ingo Molnar <[email protected]> CommitDate: Sat, 12 Mar 2016 17:30:53 +0100
x86/cpufeature: Enable new AVX-512 features
A few new AVX-512 instruction groups/features are added in cpufeatures.h for enuermation: AVX512DQ, AVX512BW, and AVX512VL.
Clear the flags in fpu__xstate_clear_all_cpu_caps().
The specification for latest AVX-512 including the features can be found at:
https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf
Note, I didn't enable the flags in KVM. Hopefully the KVM guys can pick up the flags and enable them in KVM.
--- arch/x86/include/asm/cpufeatures.h | 3 +++ arch/x86/kernel/fpu/xstate.c | 3 +++ 2 files changed, 6 insertions(+)
arch/x86/include/asm/cpufeatures.h +3 -0
@@ -220,6 +220,7 @@#define X86_FEATURE_CQM ( 9*32+12)/* Cache QoS Monitoring */ #define X86_FEATURE_MPX ( 9*32+14)/* Memory Protection Extension */ #define X86_FEATURE_AVX512F ( 9*32+16)/* AVX-512 Foundation */ +#define X86_FEATURE_AVX512DQ ( 9*32+17)/* AVX-512 DQ (Double/Quad granular) Instructions */ #define X86_FEATURE_RDSEED ( 9*32+18)/* The RDSEED instruction */ #define X86_FEATURE_ADX ( 9*32+19)/* The ADCX and ADOX instructions */ #define X86_FEATURE_SMAP ( 9*32+20)/* Supervisor Mode Access Prevention */
@@ -230,6 +231,8 @@#define X86_FEATURE_AVX512ER ( 9*32+27)/* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28)/* AVX-512 Conflict Detection */ #define X86_FEATURE_SHA_NI ( 9*32+29)/* SHA1/SHA256 Instruction Extensions */ +#define X86_FEATURE_AVX512BW ( 9*32+30)/* AVX-512 BW (Byte/Word granular) Instructions */ +#define X86_FEATURE_AVX512VL ( 9*32+31)/* AVX-512 VL (128/256 Vector Length) Extensions */ /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0)/* XSAVEOPT */
arch/x86/kernel/fpu/xstate.c +3 -0
@@ -51,6 +51,9 @@ void fpu__xstate_clear_all_cpu_caps(void)setup_clear_cpu_cap (X86_FEATURE_AVX512PF );setup_clear_cpu_cap (X86_FEATURE_AVX512ER );setup_clear_cpu_cap (X86_FEATURE_AVX512CD ); +setup_clear_cpu_cap (X86_FEATURE_AVX512DQ ); +setup_clear_cpu_cap (X86_FEATURE_AVX512BW ); +setup_clear_cpu_cap (X86_FEATURE_AVX512VL );setup_clear_cpu_cap (X86_FEATURE_MPX );setup_clear_cpu_cap (X86_FEATURE_XGETBV1 ); }