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fsl-ddr: Fix power-down timing settings

Kumar Gala u-boot 1 version New

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  1. v1 Latest4 patches 0 repliesNew

Patches in v1 No applies recorded yet

#Subject and filesSizeRepliesApplied
1/4fsl-ddr: Fix power-down timing settingscpu/mpc8xxx/ddr/ctrl_regs.c+4 -30 replies
1/4fsl-ddr: Fix power-down timing settings+0 -00 replies
2/4fsl-ddr: add the override for write levelingcpu/mpc8xxx/ddr/ctrl_regs.c cpu/mpc8xxx/ddr/options.c include/asm-ppc/fsl_ddr_sdram.h+21 -70 replies
2/4fsl-ddr: add the override for write leveling+0 -00 replies
3/4fsl-ddr: add override for the Rtt_WRcpu/mpc8xxx/ddr/ctrl_regs.c include/asm-ppc/fsl_ddr_sdram.h+8 -31 reply
3/4fsl-ddr: add override for the Rtt_WR+0 -00 replies
3/4fsl-ddr: add override for the Rtt_WR+0 -00 replies
4/4fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleavecpu/mpc8xxx/ddr/ctrl_regs.c+3 -00 replies
4/4fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave+0 -00 replies

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