ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register
Get series with b4
b4 am [email protected]Versions newest first
- v1 Latest1 patch 0 repliesNew
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/1 | ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register | +0 | 0 replies |
Reviews trailers per patch
No Reviewed-by, Acked-by or Tested-by trailers for v1 yet.