clk: sunxi: Specify number of child clocks for divs clocks
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b4 am 20141116165755.GJ6414@lukatherVersions newest first · linked by author and title
- v3 Latest6 patches 0 repliesNew
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Patches in v3 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/6 | clk: sunxi: Specify number of child clocks for divs clocks | +0 | 0 replies | |
| 2/6 | clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output | +0 | 0 replies | |
| 3/6 | ARM: sun6i: DT: Add PLL6 multiple outputs | +0 | 0 replies | |
| 4/6 | clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider | +0 | 1 reply | |
| 4/6 | clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider | +0 | 1 reply | |
| 4/6 | clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider | +0 | 0 replies |
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