Skip to content

KVM RISC-V Conditional Operations

Anup Patel kvm kvm-riscv linux-devicetree linux-kselftest linux-riscv lkml 3 versions – Applied

Status from this message: This series was applied to riscv/linux.git (fixes)

Get series with b4
b4 am [email protected]

Versions newest first · linked by author and title

  1. v3 Latest6 patches 4 repliesApplied 6/6
  2. v29 patches 15 repliesSuperseded
  3. v17 patches 16 repliesSuperseded

Changes in v3 from the cover letter

- Dropped patch1, patch2, and patch5 since these patches don't meet the requirements of patch acceptance policy.

Patches in v3 All 6 applied

#Subject and filesSizeRepliesApplied
1/6dt-bindings: riscv: Add Zicond extension entryDocumentation/devicetree/bindings/riscv/extensions.yaml+6 -00 repliesApplied
2/6RISC-V: Detect Zicond from ISA stringarch/riscv/include/asm/hwcap.h arch/riscv/kernel/cpufeature.c+2 -02 repliesApplied
3/6RISC-V: KVM: Allow Zicond extension for Guest/VMarch/riscv/include/uapi/asm/kvm.h arch/riscv/kvm/vcpu_onereg.c+3 -00 repliesApplied
4/6KVM: riscv: selftests: Add senvcfg register to get-reg-list testtools/testing/selftests/kvm/riscv/get-reg-list.c+3 -00 repliesApplied
5/6KVM: riscv: selftests: Add smstateen registers to get-reg-list testtools/testing/selftests/kvm/riscv/get-reg-list.c+34 -00 repliesApplied
6/6KVM: riscv: selftests: Add condops extensions to get-reg-list testtools/testing/selftests/kvm/riscv/get-reg-list.c+17 -00 repliesApplied

Reviews trailers per patch

All 6 patches have a Reviewed-by or Acked-by.

PatchAndrew JonesConor DooleyPalmer Dabbelt
1/6R-b R-b
2/6R-b R-b A-b
3/6R-b
4/6R-b
5/6R-b
6/6R-b

Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes. Scroll the table sideways for all 3 reviewers.

Read the v3 thread

Cover letter [PATCH v3 0/6] KVM RISC-V Conditional Operations

This series extends KVM RISC-V to allow Guest/VM discover and use conditional operations related ISA extensions (namely XVentanaCondOps and Zicond).

To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1 branch at: https://github.com/avpatel/kvmtool.git

These patches are based upon the latest riscv_kvm_queue and can also be found in the riscv_kvm_condops_v3 branch at:
https://github.com/avpatel/linux.git

Changes since v2:
- Dropped patch1, patch2, and patch5 since these patches don't meet the requirements of patch acceptance policy.

Changes since v1:
- Rebased the series on riscv_kvm_queue
- Split PATCH1 and PATCH2 of v1 series into two patches
- Added separate test configs for XVentanaCondOps and Zicond in PATCH7 of v1 series.

Anup Patel (6):
dt-bindings: riscv: Add Zicond extension entry
RISC-V: Detect Zicond from ISA string
RISC-V: KVM: Allow Zicond extension for Guest/VM
KVM: riscv: selftests: Add senvcfg register to get-reg-list test
KVM: riscv: selftests: Add smstateen registers to get-reg-list test
KVM: riscv: selftests: Add condops extensions to get-reg-list test

 .../devicetree/bindings/riscv/extensions.yaml |  6 +++
 arch/riscv/include/asm/hwcap.h                |  1 +
 arch/riscv/include/uapi/asm/kvm.h             |  1 +
 arch/riscv/kernel/cpufeature.c                |  1 +
 arch/riscv/kvm/vcpu_onereg.c                  |  2 +
 .../selftests/kvm/riscv/get-reg-list.c        | 54 +++++++++++++++++++
 6 files changed, 65 insertions(+)
Signature · 1 line
2.34.1

Read the cover letter in its thread