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perf/x86/intel: Update event constraints and cache_extra_regsfor ADL

Sasha Levin stable 1 version New

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  1. v1 Latest2 patches 0 repliesNew

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#Subject and filesSizeRepliesApplied
1/2perf/x86/intel: Update event constraints and cache_extra_regsfor ADLarch/x86/events/intel/core.c arch/x86/events/intel/ds.c arch/x86/events/perf_event.h+23 -140 replies
2/2perf/x86/intel: Fix GRT PEBS load/store direction for latency events, to fix sample classificationarch/x86/events/intel/ds.c+13 -30 replies

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