FAILED: patch "[PATCH] perf/x86/intel: Fix GRT PEBS load/store direction for latency" failed to apply to 6.6-stable tree
Subsystems (3)
[email protected]
maintainerThe patch below does not apply to the 6.6-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.6.y
git checkout FETCH_HEAD
git cherry-pick -x 89dc568e8c0be60e05e5fcd0b528c79077d7b84b
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2026092920-overjoyed-siren-0a53@gregkh' --subject-prefix 'PATCH 6.6.y' 'HEAD^..'
Possible dependencies:
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 89dc568e8c0be60e05e5fcd0b528c79077d7b84b Mon Sep 17 00:00:00 2001
From: Dapeng Mi <[email protected]>
Date: Thu, 17 Sep 2026 09:52:23 +0800
Subject: [PATCH] perf/x86/intel: Fix GRT PEBS load/store direction for latency
events, to fix sample classification
On Gracemont, intel_grt_pebs_event_constraints[] applies LAT_CONSTRAINT constraints to MEM_UOPS_RETIRED.{LOAD,STORE}_LATENCY, but does not set explicit LOAD/STORE flags for those events.
The PEBS latency path (pebs_latency_data(), via __grt_latency_data()) uses the event flags to determine memory operation direction. Without an explicit STORE flag, samples from MEM_UOPS_RETIRED.STORE_LATENCY can be misclassified as LOADs.
Set explicit LOAD/STORE flags in intel_grt_pebs_event_constraints[] for:
- MEM_UOPS_RETIRED.LOAD_LATENCY
- MEM_UOPS_RETIRED.STORE_LATENCY
Also update __grt_latency_data() to explicitly interpret these flags when assigning the sampled memory operation direction.
This fixes incorrect STORE sample classification.
arch/x86/events/intel/ds.c +13 -3
@@ -455,6 +455,7 @@ static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock)static u64 __grt_latency_data (struct perf_event *event,u64 status,u8 dse,bool tlb,bool lock,bool blk) { +union perf_mem_data_src src;u64 val; WARN_ON_ONCE(is_hybrid() &&
@@ -470,7 +471,16 @@ static u64 __grt_latency_data(struct perf_event *event, u64 status,else val |=P (BLK ,NA ); -return val; + src.val = val; + +if (event->hw.flags & + (PERF_X86_EVENT_PEBS_LDLAT |PERF_X86_EVENT_PEBS_LD_HSW )) + src.mem_op =P (OP ,LOAD ); +if (event->hw.flags & + (PERF_X86_EVENT_PEBS_STLAT |PERF_X86_EVENT_PEBS_ST_HSW )) + src.mem_op =P (OP ,STORE ); + +return src.val; }u64 grt_latency_data (struct perf_event *event,u64 status)
@@ -1291,8 +1301,8 @@ struct event_constraint intel_glm_pebs_event_constraints[] = {struct event_constraint intel_grt_pebs_event_constraints[] = {/* Allow all events as PEBS with no flags */ -INTEL_HYBRID_LAT_CONSTRAINT (0x5d0 ,0x3 ), -INTEL_HYBRID_LAT_CONSTRAINT (0x6d0 ,0x3f ), +INTEL_HYBRID_LDLAT_CONSTRAINT (0x5d0 ,0x3 ), +INTEL_HYBRID_STLAT_CONSTRAINT (0x6d0 ,0x3f ),EVENT_CONSTRAINT_END };
Sasha Levin
maintainerPATCH 1/2 perf/x86/intel: Update event constraints and cache_extra_regsfor ADL
From: Dapeng Mi <[email protected]>
[ Upstream commit 4ef863352bcde482d65722ed721c3fd3967a67d6 ]
Update perf hard-coded event constraints and cache_extra_regs[] for Alderlake according to the latest ADL perfmon events (V1.39).
One important note is that ADL has differences on the L3/node related OCR events although it shares same uarch with SPR server, e.g., ADL has different extra MSR values and no node events. So some variants of structures and functions are introduced to reflect these differences, like adl_glc_hw_cache_event_ids[], adl_glc_hw_cache_extra_regs[] and intel_pmu_init_glc_hybrid(), etc.
Please note these changes would temporarily impact other platforms like MTL/ARL-U which shares hard-coded event structures, but it would be fixed soon in subsequent patches.
ADL perfmon events:
https://github.com/intel/perfmon/blob/main/ADL/events/alderlake_goldencove_core.json
https://github.com/intel/perfmon/blob/main/ADL/events/alderlake_gracemont_core.json
Backport dependency preparation for Linux 6.6:
Retain the Gracemont store-latency counter mask update from 0xf to 0x3f. Drop the unrelated cache tables, offcore register masks and PMU initialization changes: they depend on newer refactoring and are not needed by target 89dc568e8c0be60e05e5fcd0b528c79077d7b84b.
Prepare that target's existing latency path by renaming the ADL helper and callback to __grt_latency_data() and grt_latency_data(), updating all callers and the declaration. These are existing functions, not new ones. Guard the hybrid-only warning with is_hybrid(), retaining the 6.6 cpu_type field and existing data-source mask.
Include only the two hybrid load/store latency constraint macros from 608f6976c3097, preserving the hybrid decoder dispatch while making the target's explicit direction flags available. Leave the actual direction correction to the target commit.
Stable-dep-of: 89dc568e8c0b ("perf/x86/intel: Fix GRT PEBS load/store direction for latency events, to fix sample classification")
--- arch/x86/events/intel/core.c | 4 ++-- arch/x86/events/intel/ds.c | 23 ++++++++++++----------- arch/x86/events/perf_event.h | 10 +++++++++- 3 files changed, 23 insertions(+), 14 deletions(-)
arch/x86/events/intel/core.c +2 -2
@@ -6366,7 +6366,7 @@ __init int intel_pmu_init(void) x86_pmu.flags |=PMU_FL_INSTR_LATENCY ;intel_pmu_pebs_data_source_grt (); - x86_pmu.pebs_latency_data = adl_latency_data_small; + x86_pmu.pebs_latency_data = grt_latency_data; x86_pmu.get_event_constraints = tnt_get_event_constraints; x86_pmu.limit_period = spr_limit_period; td_attr = tnt_events_attrs;
@@ -6786,7 +6786,7 @@ __init int intel_pmu_init(void) x86_pmu.flags |=PMU_FL_NO_HT_SHARING ; x86_pmu.flags |=PMU_FL_INSTR_LATENCY ; x86_pmu.lbr_pt_coexist = true; - x86_pmu.pebs_latency_data = adl_latency_data_small; + x86_pmu.pebs_latency_data = grt_latency_data; x86_pmu.num_topdown_events =8 ;static_call_update (intel_pmu_update_topdown_event, &adl_update_topdown_event);
arch/x86/events/intel/ds.c +12 -11
@@ -256,12 +256,13 @@ static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock) }/* Retrieve the latency data for e-core of ADL */ -static u64 __adl_latency_data_small (struct perf_event *event,u64 status, -u8 dse,bool tlb,bool lock,bool blk) +static u64 __grt_latency_data (struct perf_event *event,u64 status, +u8 dse,bool tlb,bool lock,bool blk) {u64 val; -WARN_ON_ONCE (hybrid_pmu (event->pmu)->cpu_type == hybrid_big); +WARN_ON_ONCE (is_hybrid () && +hybrid_pmu (event->pmu)->cpu_type == hybrid_big); dse &=PERF_PEBS_DATA_SOURCE_MASK ; val =hybrid_var (event->pmu, pebs_data_source)[dse];
@@ -276,15 +277,15 @@ static u64 __adl_latency_data_small(struct perf_event *event, u64 status,return val; } -u64 adl_latency_data_small (struct perf_event *event,u64 status) +u64 grt_latency_data (struct perf_event *event,u64 status) {union intel_x86_pebs_dse dse; dse.val = status; -return __adl_latency_data_small (event, status, dse.ld_dse, - dse.ld_locked, dse.ld_stlb_miss, - dse.ld_data_blk); +return __grt_latency_data (event, status, dse.ld_dse, + dse.ld_locked, dse.ld_stlb_miss, + dse.ld_data_blk); }/* Retrieve the latency data for e-core of MTL */
@@ -294,9 +295,9 @@ u64 mtl_latency_data_small(struct perf_event *event, u64 status) dse.val = status; -return __adl_latency_data_small (event, status, dse.mtl_dse, - dse.mtl_stlb_miss, dse.mtl_locked, - dse.mtl_fwd_blk); +return __grt_latency_data (event, status, dse.mtl_dse, + dse.mtl_stlb_miss, dse.mtl_locked, + dse.mtl_fwd_blk); }static u64 load_latency_data (struct perf_event *event,u64 status)
@@ -892,7 +893,7 @@ struct event_constraint intel_glm_pebs_event_constraints[] = {struct event_constraint intel_grt_pebs_event_constraints[] = {/* Allow all events as PEBS with no flags */ INTEL_HYBRID_LAT_CONSTRAINT (0x5d0 ,0x3 ), -INTEL_HYBRID_LAT_CONSTRAINT (0x6d0 ,0xf ), +INTEL_HYBRID_LAT_CONSTRAINT (0x6d0 ,0x3f ),EVENT_CONSTRAINT_END };
arch/x86/events/perf_event.h +9 -1
@@ -470,6 +470,14 @@ struct cpu_hw_events {__EVENT_CONSTRAINT (c, n,INTEL_ARCH_EVENT_MASK |X86_ALL_EVENT_FLAGS , \ HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID) +#define INTEL_HYBRID_LDLAT_CONSTRAINT (c, n) \ + __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ + HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_LD_HSW) + +#define INTEL_HYBRID_STLAT_CONSTRAINT (c, n) \ + __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ + HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_ST_HSW) +/* Event constraint, but match on all event flags too. */ #define INTEL_FLAGS_EVENT_CONSTRAINT (c, n) \ EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
@@ -1499,7 +1507,7 @@ void intel_pmu_disable_bts(void);int intel_pmu_drain_bts_buffer (void ); -u64 adl_latency_data_small (struct perf_event *event,u64 status); +u64 grt_latency_data (struct perf_event *event,u64 status);u64 mtl_latency_data_small (struct perf_event *event,u64 status);
Signature · 1 line
2.53.0
Sasha Levin
maintainerPATCH 2/2 perf/x86/intel: Fix GRT PEBS load/store direction for latency events, to fix sample classification
From: Dapeng Mi <[email protected]>
[ Upstream commit 89dc568e8c0be60e05e5fcd0b528c79077d7b84b ]
On Gracemont, intel_grt_pebs_event_constraints[] applies LAT_CONSTRAINT constraints to MEM_UOPS_RETIRED.{LOAD,STORE}_LATENCY, but does not set explicit LOAD/STORE flags for those events.
The PEBS latency path (pebs_latency_data(), via __grt_latency_data()) uses the event flags to determine memory operation direction. Without an explicit STORE flag, samples from MEM_UOPS_RETIRED.STORE_LATENCY can be misclassified as LOADs.
Set explicit LOAD/STORE flags in intel_grt_pebs_event_constraints[] for:
- MEM_UOPS_RETIRED.LOAD_LATENCY
- MEM_UOPS_RETIRED.STORE_LATENCY
Also update __grt_latency_data() to explicitly interpret these flags when assigning the sampled memory operation direction.
This fixes incorrect STORE sample classification.
--- arch/x86/events/intel/ds.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-)
arch/x86/events/intel/ds.c +13 -3
@@ -259,6 +259,7 @@ static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock)static u64 __grt_latency_data (struct perf_event *event,u64 status,u8 dse,bool tlb,bool lock,bool blk) { +union perf_mem_data_src src;u64 val; WARN_ON_ONCE(is_hybrid() &&
@@ -274,7 +275,16 @@ static u64 __grt_latency_data(struct perf_event *event, u64 status,else val |=P (BLK ,NA ); -return val; + src.val = val; + +if (event->hw.flags & + (PERF_X86_EVENT_PEBS_LDLAT |PERF_X86_EVENT_PEBS_LD_HSW )) + src.mem_op =P (OP ,LOAD ); +if (event->hw.flags & + (PERF_X86_EVENT_PEBS_STLAT |PERF_X86_EVENT_PEBS_ST_HSW )) + src.mem_op =P (OP ,STORE ); + +return src.val; }u64 grt_latency_data (struct perf_event *event,u64 status)
@@ -892,8 +902,8 @@ struct event_constraint intel_glm_pebs_event_constraints[] = {struct event_constraint intel_grt_pebs_event_constraints[] = {/* Allow all events as PEBS with no flags */ -INTEL_HYBRID_LAT_CONSTRAINT (0x5d0 ,0x3 ), -INTEL_HYBRID_LAT_CONSTRAINT (0x6d0 ,0x3f ), +INTEL_HYBRID_LDLAT_CONSTRAINT (0x5d0 ,0x3 ), +INTEL_HYBRID_STLAT_CONSTRAINT (0x6d0 ,0x3f ),EVENT_CONSTRAINT_END };
Signature · 1 line
2.53.0