socfpga: SPL and DDR init
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b4 am [email protected]Versions newest first
- v1 Latest2 of 172 patches 0 repliesNew
2 of 172 patches are in this archive. The cover letter announces 172.
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 11/172 | arm: socfpga: reset: Replace ad-hoc reset functions | +0 | 1 reply | |
| 12/172 | arm: socfpga: reset: Repair bridge reset handling | +0 | 1 reply |
Reviews trailers per patch
None of the 2 patches has a Reviewed-by or Acked-by of their own; the series has one for all of them.
| Patch | Dinh Nguyen |
|---|---|
| Series | A-b |
| 11/172 | |
| 12/172 |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init
Quoted 7 lines · Marek Vasut
This series fixes the SPL support on SoCFPGA and cleans up the DDR init code such that it is becoming remotely mainlinable. After this series, the SPL is capable of booting from both SD/MMC and QSPI NOR.
There is still work to be done, but I'd like to start picking it up so it can land in 2015.10 . Reviews and comments are welcome.
Thank you so much for putting this series together! For the whole series:
Acked-by Dinh Nguyen <[email protected]>
Dinh