drm/i915/dp: link rate and lane count refactoring

The link rate and lane count management has become quite convoluted. Clean it up. Calculate source/sink/common rates only once. Separate the max link rate and lane count from the source/sink max link rate and lane counts; the former are dynamic and depend on the link conditions, the latter are static properties of the source/sink devices. Reduce link bw code use, and prefer rate throughout.

There are two potential bug fixes in the series, but presumably they can only happen with the link fallback codes. Max sink rate usage was wrong for eDP 1.4. Max lane count was probably wrong for DP MST.

This probably conflicts royally with Manasi's work, but eventually this is where we should go. The current code just conflates and complicates too many things around link parameter management.

BR,
Jani.

Jani Nikula (11):
drm/i915/dp: use known correct array size in rate_to_index drm/i915/dp: return errors from rate_to_index() drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse drm/i915/dp: cache source rates at init
drm/i915/dp: generate and cache sink rate array for all DP, not just

    eDP 1.4

drm/i915/dp: use the sink rates array for max sink rates drm/i915/dp: cache common rates with sink rates drm/i915/dp: fallback link rate seek doesn't need to use rate limit drm/i915/dp: don't call the link parameters sink parameters drm/i915/dp: add functions for max common link rate and lane count drm/i915/mst: use max link not sink lane count

 drivers/gpu/drm/i915/intel_dp.c               | 216 +++++++++++++++-----------
 drivers/gpu/drm/i915/intel_dp_link_training.c |   3 +-
 drivers/gpu/drm/i915/intel_dp_mst.c           |   4 +-
 drivers/gpu/drm/i915/intel_drv.h              |  19 ++-
 4 files changed, 138 insertions(+), 104 deletions(-)

2.1.4

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