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drm/i915/dp: link rate and lane count refactoring

PATCH New Jani Nikula 2 participants 13 messages Jan 21, 2017

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Jani Nikula

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#0 lore raw

cover drm/i915/dp: link rate and lane count refactoring

The link rate and lane count management has become quite convoluted. Clean it up. Calculate source/sink/common rates only once. Separate the max link rate and lane count from the source/sink max link rate and lane counts; the former are dynamic and depend on the link conditions, the latter are static properties of the source/sink devices. Reduce link bw code use, and prefer rate throughout.

There are two potential bug fixes in the series, but presumably they can only happen with the link fallback codes. Max sink rate usage was wrong for eDP 1.4. Max lane count was probably wrong for DP MST.

This probably conflicts royally with Manasi's work, but eventually this is where we should go. The current code just conflates and complicates too many things around link parameter management.

BR,
Jani.

Jani Nikula (11):
drm/i915/dp: use known correct array size in rate_to_index drm/i915/dp: return errors from rate_to_index() drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse drm/i915/dp: cache source rates at init
drm/i915/dp: generate and cache sink rate array for all DP, not just

    eDP 1.4

drm/i915/dp: use the sink rates array for max sink rates drm/i915/dp: cache common rates with sink rates drm/i915/dp: fallback link rate seek doesn't need to use rate limit drm/i915/dp: don't call the link parameters sink parameters drm/i915/dp: add functions for max common link rate and lane count drm/i915/mst: use max link not sink lane count

 drivers/gpu/drm/i915/intel_dp.c               | 216 +++++++++++++++-----------
 drivers/gpu/drm/i915/intel_dp_link_training.c |   3 +-
 drivers/gpu/drm/i915/intel_dp_mst.c           |   4 +-
 drivers/gpu/drm/i915/intel_drv.h              |  19 ++-
 4 files changed, 138 insertions(+), 104 deletions(-)
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#1 lore raw

PATCH 1/11 drm/i915/dp: use known correct array size in rate_to_index

I can't think of a real world bug this could cause now, but this will be required in follow-up work. While at it, change the parameter order to be slightly more sensible.

Signed-off-by Jani Nikula <[email protected]>
---
 drivers/gpu/drm/i915/intel_dp.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +6 -5
index e80d620846c8..af3c3854a432 100644
@@ -1540,12 +1540,12 @@ bool intel_dp_read_desc(struct intel_dp *intel_dp)
 	return true;
 }
 
-static int rate_to_index(int find, const int *rates)
+static int rate_to_index(const int *rates, int len, int rate)
 {
-	int i = 0;
+	int i;
 
-	for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
-		if (find == rates[i])
+	for (i = 0; i < len; i++)
+		if (rate == rates[i])
 			break;
 
 	return i;

@@ -1566,7 +1566,8 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
 
 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
 {
-	return rate_to_index(rate, intel_dp->sink_rates);
+	return rate_to_index(intel_dp->sink_rates, intel_dp->num_sink_rates,
+			     rate);
 }
 
 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
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#2 lore raw

PATCH 2/11 drm/i915/dp: return errors from rate_to_index()

In reply to Jani Nikula

We shouldn't silently use the first element if we can't find the rate we're looking for. Make rate_to_index() more generally useful, and fallback to the first element in the caller, with a big warning.

Signed-off-by Jani Nikula <[email protected]>
---
 drivers/gpu/drm/i915/intel_dp.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +9 -4
index af3c3854a432..420914d08f29 100644
@@ -1546,9 +1546,9 @@ static int rate_to_index(const int *rates, int len, int rate)
 
 	for (i = 0; i < len; i++)
 		if (rate == rates[i])
-			break;
+			return i;
 
-	return i;
+	return -1;
 }
 
 int

@@ -1566,8 +1566,13 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
 
 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
 {
-	return rate_to_index(intel_dp->sink_rates, intel_dp->num_sink_rates,
-			     rate);
+	int i = rate_to_index(intel_dp->sink_rates, intel_dp->num_sink_rates,
+			      rate);
+
+	if (WARN_ON(i < 0))
+		i = 0;
+
+	return i;
 }
 
 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
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#3 lore raw

PATCH 3/11 drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse

In reply to Jani Nikula

Rename the function, move it at the top, and reuse in intel_dp_link_rate_index(). If there was a reason in the past to use reverse search order here, there isn't now.

Signed-off-by Jani Nikula <[email protected]>
---
 drivers/gpu/drm/i915/intel_dp.c | 33 ++++++++++++++-------------------
 1 file changed, 14 insertions(+), 19 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +14 -19
index 420914d08f29..1e34b24cf866 100644
@@ -264,6 +264,17 @@ static int intersect_rates(const int *source_rates, int source_len,
 	return k;
 }
 
+static int intel_dp_find_rate(const int *rates, int len, int rate)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		if (rate == rates[i])
+			return i;
+
+	return -1;
+}
+
 static int intel_dp_common_rates(struct intel_dp *intel_dp,
 				 int *common_rates)
 {

@@ -282,15 +293,10 @@ static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
 				    int *common_rates, int link_rate)
 {
 	int common_len;
-	int index;
 
 	common_len = intel_dp_common_rates(intel_dp, common_rates);
-	for (index = 0; index < common_len; index++) {
-		if (link_rate == common_rates[common_len - index - 1])
-			return common_len - index - 1;
-	}
 
-	return -1;
+	return intel_dp_find_rate(common_rates, common_len, link_rate);
 }
 
 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,

@@ -1540,17 +1546,6 @@ bool intel_dp_read_desc(struct intel_dp *intel_dp)
 	return true;
 }
 
-static int rate_to_index(const int *rates, int len, int rate)
-{
-	int i;
-
-	for (i = 0; i < len; i++)
-		if (rate == rates[i])
-			return i;
-
-	return -1;
-}
-
 int
 intel_dp_max_link_rate(struct intel_dp *intel_dp)
 {

@@ -1566,8 +1561,8 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
 
 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
 {
-	int i = rate_to_index(intel_dp->sink_rates, intel_dp->num_sink_rates,
-			      rate);
+	int i = intel_dp_find_rate(intel_dp->sink_rates,
+				   intel_dp->num_sink_rates, rate);
 
 	if (WARN_ON(i < 0))
 		i = 0;
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#4 lore raw

PATCH 4/11 drm/i915/dp: cache source rates at init

In reply to Jani Nikula

We need the source rates array so often that it makes sense to set it once at init. This reduces function calls when we need the rates, making the code easier to follow.

Signed-off-by Jani Nikula <[email protected]>
---
 drivers/gpu/drm/i915/intel_dp.c  | 35 +++++++++++++++++++++--------------
 drivers/gpu/drm/i915/intel_drv.h |  3 +++
 2 files changed, 24 insertions(+), 14 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +21 -14
index 1e34b24cf866..9426a41d53db 100644
@@ -216,21 +216,25 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 	return (intel_dp->max_sink_link_bw >> 3) + 1;
 }
 
-static int
-intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
+static void
+intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+	const int *source_rates;
 	int size;
 
+	/* This should only be done once */
+	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
+
 	if (IS_GEN9_LP(dev_priv)) {
-		*source_rates = bxt_rates;
+		source_rates = bxt_rates;
 		size = ARRAY_SIZE(bxt_rates);
 	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
-		*source_rates = skl_rates;
+		source_rates = skl_rates;
 		size = ARRAY_SIZE(skl_rates);
 	} else {
-		*source_rates = default_rates;
+		source_rates = default_rates;
 		size = ARRAY_SIZE(default_rates);
 	}
 

@@ -238,7 +242,8 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
 	if (!intel_dp_source_supports_hbr2(intel_dp))
 		size--;
 
-	return size;
+	intel_dp->source_rates = source_rates;
+	intel_dp->num_source_rates = size;
 }
 
 static int intersect_rates(const int *source_rates, int source_len,

@@ -278,13 +283,13 @@ static int intel_dp_find_rate(const int *rates, int len, int rate)
 static int intel_dp_common_rates(struct intel_dp *intel_dp,
 				 int *common_rates)
 {
-	const int *source_rates, *sink_rates;
-	int source_len, sink_len;
+	const int *sink_rates;
+	int sink_len;
 
 	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
-	source_len = intel_dp_source_rates(intel_dp, &source_rates);
 
-	return intersect_rates(source_rates, source_len,
+	return intersect_rates(intel_dp->source_rates,
+			       intel_dp->num_source_rates,
 			       sink_rates, sink_len,
 			       common_rates);
 }

@@ -1494,16 +1499,16 @@ static void snprintf_int_array(char *str, size_t len,
 
 static void intel_dp_print_rates(struct intel_dp *intel_dp)
 {
-	const int *source_rates, *sink_rates;
-	int source_len, sink_len, common_len;
+	const int *sink_rates;
+	int sink_len, common_len;
 	int common_rates[DP_MAX_SUPPORTED_RATES];
 	char str[128]; /* FIXME: too big for stack? */
 
 	if ((drm_debug & DRM_UT_KMS) == 0)
 		return;
 
-	source_len = intel_dp_source_rates(intel_dp, &source_rates);
-	snprintf_int_array(str, sizeof(str), source_rates, source_len);
+	snprintf_int_array(str, sizeof(str),
+			   intel_dp->source_rates, intel_dp->num_source_rates);
 	DRM_DEBUG_KMS("source rates: %s\n", str);
 
 	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);

@@ -5806,6 +5811,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 		 intel_dig_port->max_lanes, port_name(port)))
 		return false;
 
+	intel_dp_set_source_rates(intel_dp);
+
 	intel_dp->pps_pipe = INVALID_PIPE;
 	intel_dp->active_pipe = INVALID_PIPE;
drivers/gpu/drm/i915/intel_drv.h +3 -0
index 0cec0013ace0..f714ac6eb338 100644
@@ -915,6 +915,9 @@ struct intel_dp {
 	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
+	/* source rates */
+	int num_source_rates;
+	const int *source_rates;
 	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 	uint8_t num_sink_rates;
 	int sink_rates[DP_MAX_SUPPORTED_RATES];
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#5 lore raw

PATCH 5/11 drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4

In reply to Jani Nikula

There is some conflation related to sink rates, making this change more complicated than it would otherwise have to be. There are three changes here that are rather difficult to split up:

1) Use the intel_dp->sink_rates array for all DP, not just eDP 1.4. We initialize it from DPCD on eDP 1.4 like before, but generate it based on DP_MAX_LINK_RATE on others. This reduces code complexity when we need to use the sink rates; they are all always in the sink_rates array.

2) Update the sink rate array whenever we read DPCD, and use the information from there. This increases code readability when we need the sink rates.

3) Disentangle fallback rate limiting from sink rates. In the code, the max rate is a dynamic property of the *link*, not of the *sink*. Do the limiting after intersecting the source and sink rates, which are static properties of the devices.

This paves the way for follow-up refactoring that I've refrained from doing here to keep this change as simple as it possibly can.

Signed-off-by Jani Nikula <[email protected]>
---
 drivers/gpu/drm/i915/intel_dp.c               | 76 ++++++++++++++++++---------
 drivers/gpu/drm/i915/intel_dp_link_training.c |  3 +-
 drivers/gpu/drm/i915/intel_drv.h              |  4 +-
 3 files changed, 55 insertions(+), 28 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +51 -25
index 9426a41d53db..4000206bf898 100644
@@ -131,6 +131,34 @@ static void vlv_steal_power_sequencer(struct drm_device *dev,
 				      enum pipe pipe);
 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 
+static int intel_dp_num_rates(u8 link_bw_code)
+{
+	switch (link_bw_code) {
+	default:
+		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
+		     link_bw_code);
+	case DP_LINK_BW_1_62:
+		return 1;
+	case DP_LINK_BW_2_7:
+		return 2;
+	case DP_LINK_BW_5_4:
+		return 3;
+	}
+}
+
+/* update sink rates from dpcd */
+static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
+{
+	int i, num_rates;
+
+	num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]);
+
+	for (i = 0; i < num_rates; i++)
+		intel_dp->sink_rates[i] = default_rates[i];
+
+	intel_dp->num_sink_rates = num_rates;
+}
+
 static int
 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 {

@@ -203,19 +231,6 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 	return max_dotclk;
 }
 
-static int
-intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
-{
-	if (intel_dp->num_sink_rates) {
-		*sink_rates = intel_dp->sink_rates;
-		return intel_dp->num_sink_rates;
-	}
-
-	*sink_rates = default_rates;
-
-	return (intel_dp->max_sink_link_bw >> 3) + 1;
-}
-
 static void
 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {

@@ -283,15 +298,22 @@ static int intel_dp_find_rate(const int *rates, int len, int rate)
 static int intel_dp_common_rates(struct intel_dp *intel_dp,
 				 int *common_rates)
 {
-	const int *sink_rates;
-	int sink_len;
+	int max_rate = drm_dp_bw_code_to_link_rate(intel_dp->max_sink_link_bw);
+	int i, common_len;
 
-	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
+	common_len = intersect_rates(intel_dp->source_rates,
+				     intel_dp->num_source_rates,
+				     intel_dp->sink_rates,
+				     intel_dp->num_sink_rates,
+				     common_rates);
 
-	return intersect_rates(intel_dp->source_rates,
-			       intel_dp->num_source_rates,
-			       sink_rates, sink_len,
-			       common_rates);
+	/* Limit results by potentially reduced max rate */
+	for (i = 0; i < common_len; i++) {
+		if (common_rates[common_len - i - 1] <= max_rate)
+			return common_len - i;
+	}
+
+	return 0;
 }
 
 static int intel_dp_link_rate_index(struct intel_dp *intel_dp,

@@ -1499,8 +1521,7 @@ static void snprintf_int_array(char *str, size_t len,
 
 static void intel_dp_print_rates(struct intel_dp *intel_dp)
 {
-	const int *sink_rates;
-	int sink_len, common_len;
+	int common_len;
 	int common_rates[DP_MAX_SUPPORTED_RATES];
 	char str[128]; /* FIXME: too big for stack? */
 

@@ -1511,8 +1532,8 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
 			   intel_dp->source_rates, intel_dp->num_source_rates);
 	DRM_DEBUG_KMS("source rates: %s\n", str);
 
-	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
-	snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
+	snprintf_int_array(str, sizeof(str),
+			   intel_dp->sink_rates, intel_dp->num_sink_rates);
 	DRM_DEBUG_KMS("sink rates: %s\n", str);
 
 	common_len = intel_dp_common_rates(intel_dp, common_rates);

@@ -1578,7 +1599,8 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 			   uint8_t *link_bw, uint8_t *rate_select)
 {
-	if (intel_dp->num_sink_rates) {
+	/* eDP 1.4 rate select method. */
+	if (is_edp(intel_dp) && intel_dp->edp_dpcd[0] >= 0x03) {
 		*link_bw = 0;
 		*rate_select =
 			intel_dp_rate_select(intel_dp, port_clock);

@@ -3695,6 +3717,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
 			intel_dp->sink_rates[i] = (val * 200) / 10;
 		}
 		intel_dp->num_sink_rates = i;
+	} else {
+		intel_dp_set_sink_rates(intel_dp);
 	}
 
 	return true;

@@ -3707,6 +3731,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 	if (!intel_dp_read_dpcd(intel_dp))
 		return false;
 
+	intel_dp_set_sink_rates(intel_dp);
+
 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
 			     &intel_dp->sink_count, 1) < 0)
 		return false;
drivers/gpu/drm/i915/intel_dp_link_training.c +2 -1
index 0048b520baf7..694ad0ffb523 100644
@@ -146,7 +146,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
 
-	if (intel_dp->num_sink_rates)
+	/* eDP 1.4 rate select method. */
+	if (!link_bw)
 		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
 				  &rate_select, 1);
drivers/gpu/drm/i915/intel_drv.h +2 -2
index f714ac6eb338..49bf3db41408 100644
@@ -918,8 +918,8 @@ struct intel_dp {
 	/* source rates */
 	int num_source_rates;
 	const int *source_rates;
-	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
-	uint8_t num_sink_rates;
+	/* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
+	int num_sink_rates;
 	int sink_rates[DP_MAX_SUPPORTED_RATES];
 	/* Max lane count for the sink as per DPCD registers */
 	uint8_t max_sink_lane_count;
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#6 lore raw

PATCH 6/11 drm/i915/dp: use the sink rates array for max sink rates

In reply to Jani Nikula

Looking at DPCD DP_MAX_LINK_RATE may be completely bogus for eDP 1.4 which is allowed to use link rate select method and have 0 in max link rate. With this change, it makes sense to store the max rate as the actual rate rather than as a bw code.

Signed-off-by Jani Nikula <[email protected]>
---
 drivers/gpu/drm/i915/intel_dp.c  | 28 +++++++---------------------
 drivers/gpu/drm/i915/intel_drv.h |  2 +-
 2 files changed, 8 insertions(+), 22 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +7 -21
index 4000206bf898..bee617c87a14 100644
@@ -159,23 +159,9 @@ static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 	intel_dp->num_sink_rates = num_rates;
 }
 
-static int
-intel_dp_max_link_bw(struct intel_dp  *intel_dp)
+static int intel_dp_max_sink_rate(struct intel_dp *intel_dp)
 {
-	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
-
-	switch (max_link_bw) {
-	case DP_LINK_BW_1_62:
-	case DP_LINK_BW_2_7:
-	case DP_LINK_BW_5_4:
-		break;
-	default:
-		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
-		     max_link_bw);
-		max_link_bw = DP_LINK_BW_1_62;
-		break;
-	}
-	return max_link_bw;
+	return intel_dp->sink_rates[intel_dp->num_sink_rates - 1];
 }
 
 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)

@@ -298,7 +284,7 @@ static int intel_dp_find_rate(const int *rates, int len, int rate)
 static int intel_dp_common_rates(struct intel_dp *intel_dp,
 				 int *common_rates)
 {
-	int max_rate = drm_dp_bw_code_to_link_rate(intel_dp->max_sink_link_bw);
+	int max_rate = intel_dp->max_sink_link_rate;
 	int i, common_len;
 
 	common_len = intersect_rates(intel_dp->source_rates,

@@ -336,10 +322,10 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 						   common_rates,
 						   link_rate);
 	if (link_rate_index > 0) {
-		intel_dp->max_sink_link_bw = drm_dp_link_rate_to_bw_code(common_rates[link_rate_index - 1]);
+		intel_dp->max_sink_link_rate = common_rates[link_rate_index - 1];
 		intel_dp->max_sink_lane_count = lane_count;
 	} else if (lane_count > 1) {
-		intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
+		intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp);
 		intel_dp->max_sink_lane_count = lane_count >> 1;
 	} else {
 		DRM_ERROR("Link Training Unsuccessful\n");

@@ -4544,8 +4530,8 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
 	/* Set the max lane count for sink */
 	intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 
-	/* Set the max link BW for sink */
-	intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
+	/* Set the max link rate for sink */
+	intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp);
 
 	intel_dp_print_rates(intel_dp);
drivers/gpu/drm/i915/intel_drv.h +1 -1
index 49bf3db41408..0ac2b82ab34b 100644
@@ -924,7 +924,7 @@ struct intel_dp {
 	/* Max lane count for the sink as per DPCD registers */
 	uint8_t max_sink_lane_count;
 	/* Max link BW for the sink as per DPCD registers */
-	int max_sink_link_bw;
+	int max_sink_link_rate;
 	/* sink or branch descriptor */
 	struct intel_dp_desc desc;
 	struct drm_dp_aux aux;
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#7 lore raw

PATCH 7/11 drm/i915/dp: cache common rates with sink rates

In reply to Jani Nikula

Now that source rates are static and sink rates are updated whenever DPCD is updated, we can do and cache the intersection of them whenever sink rates are updated. This reduces code complexity, as we don't have to keep calling the functions to intersect. We also get rid of several common rates arrays on stack.

Limiting the common rates by a max link rate can be done by picking the first N elements of the cached common rates.

Signed-off-by Jani Nikula <[email protected]>
---
 drivers/gpu/drm/i915/intel_dp.c  | 63 +++++++++++++++++++++++-----------------
 drivers/gpu/drm/i915/intel_drv.h |  3 ++
 2 files changed, 40 insertions(+), 26 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +37 -26
index bee617c87a14..518b7ff17ad6 100644
@@ -281,17 +281,29 @@ static int intel_dp_find_rate(const int *rates, int len, int rate)
 	return -1;
 }
 
-static int intel_dp_common_rates(struct intel_dp *intel_dp,
-				 int *common_rates)
+static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 {
-	int max_rate = intel_dp->max_sink_link_rate;
-	int i, common_len;
+	WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 
-	common_len = intersect_rates(intel_dp->source_rates,
-				     intel_dp->num_source_rates,
-				     intel_dp->sink_rates,
-				     intel_dp->num_sink_rates,
-				     common_rates);
+	intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
+						     intel_dp->num_source_rates,
+						     intel_dp->sink_rates,
+						     intel_dp->num_sink_rates,
+						     intel_dp->common_rates);
+
+	/* Paranoia, there should always be something in common. */
+	if (WARN_ON(intel_dp->num_common_rates == 0)) {
+		intel_dp->common_rates[0] = default_rates[0];
+		intel_dp->num_common_rates = 1;
+	}
+}
+
+/* get length of common rates potentially limited by max_rate */
+static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
+					  int max_rate)
+{
+	const int *common_rates = intel_dp->common_rates;
+	int i, common_len = intel_dp->num_common_rates;
 
 	/* Limit results by potentially reduced max rate */
 	for (i = 0; i < common_len; i++) {

@@ -302,25 +314,23 @@ static int intel_dp_common_rates(struct intel_dp *intel_dp,
 	return 0;
 }
 
-static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
-				    int *common_rates, int link_rate)
+static int intel_dp_link_rate_index(struct intel_dp *intel_dp, int link_rate)
 {
 	int common_len;
 
-	common_len = intel_dp_common_rates(intel_dp, common_rates);
+	common_len = intel_dp_common_len_rate_limit(intel_dp,
+						    intel_dp->max_sink_link_rate);
 
-	return intel_dp_find_rate(common_rates, common_len, link_rate);
+	return intel_dp_find_rate(intel_dp->common_rates, common_len, link_rate);
 }
 
 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 					    int link_rate, uint8_t lane_count)
 {
-	int common_rates[DP_MAX_SUPPORTED_RATES];
+	const int *common_rates = intel_dp->common_rates;
 	int link_rate_index;
 
-	link_rate_index = intel_dp_link_rate_index(intel_dp,
-						   common_rates,
-						   link_rate);
+	link_rate_index = intel_dp_link_rate_index(intel_dp, link_rate);
 	if (link_rate_index > 0) {
 		intel_dp->max_sink_link_rate = common_rates[link_rate_index - 1];
 		intel_dp->max_sink_lane_count = lane_count;

@@ -1507,8 +1517,6 @@ static void snprintf_int_array(char *str, size_t len,
 
 static void intel_dp_print_rates(struct intel_dp *intel_dp)
 {
-	int common_len;
-	int common_rates[DP_MAX_SUPPORTED_RATES];
 	char str[128]; /* FIXME: too big for stack? */
 
 	if ((drm_debug & DRM_UT_KMS) == 0)

@@ -1522,8 +1530,8 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
 			   intel_dp->sink_rates, intel_dp->num_sink_rates);
 	DRM_DEBUG_KMS("sink rates: %s\n", str);
 
-	common_len = intel_dp_common_rates(intel_dp, common_rates);
-	snprintf_int_array(str, sizeof(str), common_rates, common_len);
+	snprintf_int_array(str, sizeof(str),
+			   intel_dp->common_rates, intel_dp->num_common_rates);
 	DRM_DEBUG_KMS("common rates: %s\n", str);
 }
 

@@ -1561,14 +1569,14 @@ bool intel_dp_read_desc(struct intel_dp *intel_dp)
 int
 intel_dp_max_link_rate(struct intel_dp *intel_dp)
 {
-	int rates[DP_MAX_SUPPORTED_RATES] = {};
 	int len;
 
-	len = intel_dp_common_rates(intel_dp, rates);
+	len = intel_dp_common_len_rate_limit(intel_dp,
+					     intel_dp->max_sink_link_rate);
 	if (WARN_ON(len <= 0))
 		return 162000;
 
-	return rates[len - 1];
+	return intel_dp->common_rates[len - 1];
 }
 
 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)

@@ -1629,11 +1637,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	int max_clock;
 	int bpp, mode_rate;
 	int link_avail, link_clock;
-	int common_rates[DP_MAX_SUPPORTED_RATES] = {};
+	const int *common_rates = intel_dp->common_rates;
 	int common_len;
 	uint8_t link_bw, rate_select;
 
-	common_len = intel_dp_common_rates(intel_dp, common_rates);
+	common_len = intel_dp_common_len_rate_limit(intel_dp,
+						    intel_dp->max_sink_link_rate);
 
 	/* No common link rates between source and sink */
 	WARN_ON(common_len <= 0);

@@ -3706,6 +3715,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
 	} else {
 		intel_dp_set_sink_rates(intel_dp);
 	}
+	intel_dp_set_common_rates(intel_dp);
 
 	return true;
 }

@@ -3718,6 +3728,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 		return false;
 
 	intel_dp_set_sink_rates(intel_dp);
+	intel_dp_set_common_rates(intel_dp);
 
 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
 			     &intel_dp->sink_count, 1) < 0)
drivers/gpu/drm/i915/intel_drv.h +3 -0
index 0ac2b82ab34b..a33691b3500b 100644
@@ -921,6 +921,9 @@ struct intel_dp {
 	/* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
 	int num_sink_rates;
 	int sink_rates[DP_MAX_SUPPORTED_RATES];
+	/* intersection of source and sink rates */
+	int num_common_rates;
+	int common_rates[DP_MAX_SUPPORTED_RATES];
 	/* Max lane count for the sink as per DPCD registers */
 	uint8_t max_sink_lane_count;
 	/* Max link BW for the sink as per DPCD registers */
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#8 lore raw

PATCH 8/11 drm/i915/dp: fallback link rate seek doesn't need to use rate limit

In reply to Jani Nikula

We're trying to find a rate that we know is in a sorted array. We don't need to limit the array using the max rate.

Signed-off-by Jani Nikula <[email protected]>
---
 drivers/gpu/drm/i915/intel_dp.c | 21 ++++++---------------
 1 file changed, 6 insertions(+), 15 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +6 -15
index 518b7ff17ad6..ad62effafaed 100644
@@ -314,25 +314,16 @@ static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
 	return 0;
 }
 
-static int intel_dp_link_rate_index(struct intel_dp *intel_dp, int link_rate)
-{
-	int common_len;
-
-	common_len = intel_dp_common_len_rate_limit(intel_dp,
-						    intel_dp->max_sink_link_rate);
-
-	return intel_dp_find_rate(intel_dp->common_rates, common_len, link_rate);
-}
-
 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 					    int link_rate, uint8_t lane_count)
 {
-	const int *common_rates = intel_dp->common_rates;
-	int link_rate_index;
+	int index;
 
-	link_rate_index = intel_dp_link_rate_index(intel_dp, link_rate);
-	if (link_rate_index > 0) {
-		intel_dp->max_sink_link_rate = common_rates[link_rate_index - 1];
+	index = intel_dp_find_rate(intel_dp->common_rates,
+				   intel_dp->num_common_rates,
+				   link_rate);
+	if (index > 0) {
+		intel_dp->max_sink_link_rate = intel_dp->common_rates[index - 1];
 		intel_dp->max_sink_lane_count = lane_count;
 	} else if (lane_count > 1) {
 		intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp);
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author
#9 lore raw

PATCH 9/11 drm/i915/dp: don't call the link parameters sink parameters

In reply to Jani Nikula

If we modify these on the fly depending on the link conditions, don't pretend they are sink properties.

Some link vs. sink confusion still remains, but we'll take care of them in follow-up patches.

Signed-off-by Jani Nikula <[email protected]>
---
 drivers/gpu/drm/i915/intel_dp.c  | 23 +++++++++++------------
 drivers/gpu/drm/i915/intel_drv.h |  8 ++++----
 2 files changed, 15 insertions(+), 16 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +11 -12
index ad62effafaed..8c9049fa5d2c 100644
@@ -170,7 +170,7 @@ static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 	u8 source_max, sink_max;
 
 	source_max = intel_dig_port->max_lanes;
-	sink_max = intel_dp->max_sink_lane_count;
+	sink_max = intel_dp->max_link_lane_count;
 
 	return min(source_max, sink_max);
 }

@@ -323,11 +323,11 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 				   intel_dp->num_common_rates,
 				   link_rate);
 	if (index > 0) {
-		intel_dp->max_sink_link_rate = intel_dp->common_rates[index - 1];
-		intel_dp->max_sink_lane_count = lane_count;
+		intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
+		intel_dp->max_link_lane_count = lane_count;
 	} else if (lane_count > 1) {
-		intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp);
-		intel_dp->max_sink_lane_count = lane_count >> 1;
+		intel_dp->max_link_rate = intel_dp_max_sink_rate(intel_dp);
+		intel_dp->max_link_lane_count = lane_count >> 1;
 	} else {
 		DRM_ERROR("Link Training Unsuccessful\n");
 		return -1;

@@ -1562,8 +1562,7 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
 {
 	int len;
 
-	len = intel_dp_common_len_rate_limit(intel_dp,
-					     intel_dp->max_sink_link_rate);
+	len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
 	if (WARN_ON(len <= 0))
 		return 162000;
 

@@ -1633,7 +1632,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	uint8_t link_bw, rate_select;
 
 	common_len = intel_dp_common_len_rate_limit(intel_dp,
-						    intel_dp->max_sink_link_rate);
+						    intel_dp->max_link_rate);
 
 	/* No common link rates between source and sink */
 	WARN_ON(common_len <= 0);

@@ -4529,11 +4528,11 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
 		      yesno(intel_dp_source_supports_hbr2(intel_dp)),
 		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
-	/* Set the max lane count for sink */
-	intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+	/* Set the max lane count for link */
+	intel_dp->max_link_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 
-	/* Set the max link rate for sink */
-	intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp);
+	/* Set the max link rate for link */
+	intel_dp->max_link_rate = intel_dp_max_sink_rate(intel_dp);
 
 	intel_dp_print_rates(intel_dp);
drivers/gpu/drm/i915/intel_drv.h +4 -4
index a33691b3500b..240f3cebe920 100644
@@ -924,10 +924,10 @@ struct intel_dp {
 	/* intersection of source and sink rates */
 	int num_common_rates;
 	int common_rates[DP_MAX_SUPPORTED_RATES];
-	/* Max lane count for the sink as per DPCD registers */
-	uint8_t max_sink_lane_count;
-	/* Max link BW for the sink as per DPCD registers */
-	int max_sink_link_rate;
+	/* Max lane count for the current link */
+	int max_link_lane_count;
+	/* Max rate for the current link */
+	int max_link_rate;
 	/* sink or branch descriptor */
 	struct intel_dp_desc desc;
 	struct drm_dp_aux aux;
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#10 lore raw

PATCH 10/11 drm/i915/dp: add functions for max common link rate and lane count

In reply to Jani Nikula

These are the theoretical maximums common for source and sink. These are the maximums we should start with. They may be degraded in case of link training failures, and the dynamic link values are stored separately.

Signed-off-by Jani Nikula <[email protected]>
---
 drivers/gpu/drm/i915/intel_dp.c | 29 +++++++++++++++++------------
 1 file changed, 17 insertions(+), 12 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +17 -12
index 8c9049fa5d2c..96aaaf1f6b0f 100644
@@ -159,22 +159,27 @@ static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 	intel_dp->num_sink_rates = num_rates;
 }
 
-static int intel_dp_max_sink_rate(struct intel_dp *intel_dp)
+/* Theoretical max between source and sink */
+static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 {
-	return intel_dp->sink_rates[intel_dp->num_sink_rates - 1];
+	return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 }
 
-static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
+/* Theoretical max between source and sink */
+static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	u8 source_max, sink_max;
-
-	source_max = intel_dig_port->max_lanes;
-	sink_max = intel_dp->max_link_lane_count;
+	int source_max = intel_dig_port->max_lanes;
+	int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 
 	return min(source_max, sink_max);
 }
 
+static int intel_dp_max_lane_count(struct intel_dp *intel_dp)
+{
+	return intel_dp->max_link_lane_count;
+}
+
 int
 intel_dp_link_required(int pixel_clock, int bpp)
 {

@@ -326,7 +331,7 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 		intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 		intel_dp->max_link_lane_count = lane_count;
 	} else if (lane_count > 1) {
-		intel_dp->max_link_rate = intel_dp_max_sink_rate(intel_dp);
+		intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 		intel_dp->max_link_lane_count = lane_count >> 1;
 	} else {
 		DRM_ERROR("Link Training Unsuccessful\n");

@@ -4528,11 +4533,11 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
 		      yesno(intel_dp_source_supports_hbr2(intel_dp)),
 		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
-	/* Set the max lane count for link */
-	intel_dp->max_link_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+	/* Initial max link lane count */
+	intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
 
-	/* Set the max link rate for link */
-	intel_dp->max_link_rate = intel_dp_max_sink_rate(intel_dp);
+	/* Initial max link rate */
+	intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 
 	intel_dp_print_rates(intel_dp);
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#11 lore raw

PATCH 11/11 drm/i915/mst: use max link not sink lane count

In reply to Jani Nikula

The source might not support as many lanes as the sink, or the link training might have failed at higher lane counts. Take these into account.

Signed-off-by Jani Nikula <[email protected]>
---
 drivers/gpu/drm/i915/intel_dp.c     | 2 +-
 drivers/gpu/drm/i915/intel_dp_mst.c | 4 ++--
 drivers/gpu/drm/i915/intel_drv.h    | 1 +
 3 files changed, 4 insertions(+), 3 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +1 -1
index 96aaaf1f6b0f..1554da5b2dc2 100644
@@ -175,7 +175,7 @@ static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 	return min(source_max, sink_max);
 }
 
-static int intel_dp_max_lane_count(struct intel_dp *intel_dp)
+int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 {
 	return intel_dp->max_link_lane_count;
 }
drivers/gpu/drm/i915/intel_dp_mst.c +2 -2
index 205fe4748ec5..de02835ada8d 100644
@@ -51,7 +51,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
 	 * for MST we always configure max link bw - the spec doesn't
 	 * seem to suggest we should do otherwise.
 	 */
-	lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+	lane_count = intel_dp_max_lane_count(intel_dp);
 
 	pipe_config->lane_count = lane_count;
 

@@ -357,7 +357,7 @@ intel_dp_mst_mode_valid(struct drm_connector *connector,
 	int max_rate, mode_rate, max_lanes, max_link_clock;
 
 	max_link_clock = intel_dp_max_link_rate(intel_dp);
-	max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
+	max_lanes = intel_dp_max_lane_count(intel_dp);
 
 	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 	mode_rate = intel_dp_link_required(mode->clock, bpp);
drivers/gpu/drm/i915/intel_drv.h +1 -0
index 240f3cebe920..ca437a8757e8 100644
@@ -1450,6 +1450,7 @@ void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *co
 void intel_dp_mst_suspend(struct drm_device *dev);
 void intel_dp_mst_resume(struct drm_device *dev);
 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
+int intel_dp_max_lane_count(struct intel_dp *intel_dp);
 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
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#12 lore raw

✗ Fi.CI.BAT: failure for drm/i915/dp: link rate and lane count refactoring

In reply to Jani Nikula
== Series Details ==

== Series Details ==

Series: drm/i915/dp: link rate and lane count refactoring
URL : https://patchwork.freedesktop.org/series/18359/
State : failure

== Summary ==

Series 18359v1 drm/i915/dp: link rate and lane count refactoring
https://patchwork.freedesktop.org/api/1.0/series/18359/revisions/1/mbox/

Test kms_force_connector_basic:

        Subgroup force-connector-state:
                pass       -> DMESG-WARN (fi-snb-2520m)
        Subgroup prune-stale-modes:
                dmesg-warn -> PASS       (fi-snb-2520m)
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-c:
                pass       -> FAIL       (fi-skl-6700k)
fi-bdw-5557u     total:246  pass:232  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050     total:246  pass:207  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:246  pass:224  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700     total:79   pass:66   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900     total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r     total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m     total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770      total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u     total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u     total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hq    total:246  pass:226  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k     total:246  pass:221  dwarn:3   dfail:0   fail:1   skip:21 
fi-skl-6770hq    total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m     total:246  pass:214  dwarn:1   dfail:0   fail:0   skip:31 
fi-snb-2600      total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32

f62d6104306f3ec835f3776434a70ca9bb6f820e drm-tip: 2017y-01m-21d-11h-28m-52s UTC integration manifest 22d38dc drm/i915/mst: use max link not sink lane count
4256d26 drm/i915/dp: add functions for max common link rate and lane count
82d7685 drm/i915/dp: don't call the link parameters sink parameters
f3694b3 drm/i915/dp: fallback link rate seek doesn't need to use rate limit
36aa3e6 drm/i915/dp: cache common rates with sink rates
7e945d9 drm/i915/dp: use the sink rates array for max sink rates
52f5370 drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4 16f5d06 drm/i915/dp: cache source rates at init
7cd0b1a drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse f5210e2 drm/i915/dp: return errors from rate_to_index()
d21c5c4 drm/i915/dp: use known correct array size in rate_to_index

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3575/
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