target/riscv: write mstatus.GVA on every trap into M-mode
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- v1 Latest2 patches 2 repliesIn review
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/2 | target/riscv: write mstatus.GVA on every trap into M-modetarget/ | +1 | 1 reply | |
| 2/2 | tests/tcg/riscv64: test mstatus.GVA on traps into M-modetests/ tests/ | +96 | 1 reply |
Reviews trailers per patch
All 2 patches have a Reviewed-by or Acked-by.
| Patch | Daniel Henrique Barboza |
|---|---|
| 1/2 | R-b |
| 2/2 | R-b |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [PATCH 0/2] target/riscv: write mstatus.GVA on every trap into M-mode
Hi,
Based-on: <[email protected]> ("target/riscv: fix mtinst/htinst for G-stage faults on VS-stage A/D updates", whose hyp-guest.h and hyp-guest.S this test reuses)
Patch 1 fixes mstatus.GVA. On every trap into M-mode, GVA should be set to 1 if mtval holds a guest virtual address and to 0 otherwise [1]. QEMU does not clear gva or set GVA for particular faults.
Both date back to 9034e90ad9. The fix sets mstatus.GVA from write_gva, the value QEMU already computes for hstatus.GVA.
Patch 2 adds a test, all 4 pass on upstream Spike, all fail on master.
This bug was found while examining <[email protected]> and writing a generalized test. Claude was used to diagnose the issue. All commits were human written.
[1] Privileged ISA v1.12, 8.2.1, the description of GVA and the note under hstatus.GVA
https://github.com/riscv/riscv-isa-manual/releases/tag/Priv-v1.12
tewaro (2):
target/riscv: write mstatus.GVA on every trap into M-mode tests/tcg/riscv64: test mstatus.GVA on traps into M-mode
target/riscv/tcg/cpu_helper.c | 4 +- tests/tcg/riscv64/system/meson.build | 21 ++++++++ tests/tcg/riscv64/test-mstatus-gva.S | 75 ++++++++++++++++++++++++++++ 3 files changed, 97 insertions(+), 3 deletions(-) create mode 100644 tests/tcg/riscv64/test-mstatus-gva.S
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