target/i386: Fix andn instruction
PATCH 1/1 target/i386: Fix andn instruction
In commit 7073fbada733c8d10992f00772c9b9299d740e9b, the andn instruction was implemented via tcg_gen_andc but passes the operands in the wrong order:
- X86 defines andn dest,src1,src2 as: dest = ~src1 & src2
- TCG defines andc dest,src1,src2 as: dest = src1 & ~src2
I have also attached a simple test which shows the issue:
Quoted 4 lines
user@ubuntu:~/Software$ ./a.out 0000F000 user@ubuntu:~/Software$ qemu/x86_64-linux-user/qemu-x86_64 -cpu max a.out 0000000F
This patch fixes the problem by simply swapping the order of the two last arguments in tcg_gen_andc_tl.
Signed-off-by Alexandro Sanchez Bach <[email protected]>
Reported-by Alexandro Sanchez Bach <[email protected]>
target/i386/translate.c +0 -0
@@ -3802,7 +3802,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
}
ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- tcg_gen_andc_tl(cpu_T0, cpu_regs[s->vex_v], cpu_T0);
+ tcg_gen_andc_tl(cpu_T0, cpu_T0, cpu_regs[s->vex_v]);
gen_op_mov_reg_v(ot, reg, cpu_T0);
gen_op_update1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);#include <stdio.h>
#include <stdint.h>
int main(void) {
uint32_t ret = 0;
__asm (
"mov $0xFF00, %%ecx\n"
"mov $0x0F0F, %%eax\n"
"andn %%ecx, %%eax, %%ecx\n"
"mov %%ecx, %0\n"
: "=r" (ret));
printf("%08X\n", ret);
return 0;
}