FAILED: patch "[PATCH] drm/i915/bdw: Add missing delay during L3 SQC credit" failed to apply to 4.7-stable tree
Subsystems (3)
[email protected]
maintainerThe patch below does not apply to the 4.7-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
Quoted 1 line
From
48e5d68d28f00c0cadac5a830980ff3222781abbMon Sep 17 00:00:00 2001
From: Imre Deak <[email protected]>
Date: Tue, 3 May 2016 15:54:19 +0300
Subject: [PATCH] drm/i915/bdw: Add missing delay during L3 SQC credit
programming
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BSpec requires us to wait ~100 clocks before re-enabling clock gating, so make sure we do this.
CC Ville Syrjälä <[email protected]>
Signed-off-by Imre Deak <[email protected]>
Reviewed-by Ville Syrjälä <[email protected]>
drivers/gpu/drm/i915/intel_pm.c +6 -0
@@ -6738,6 +6738,12 @@ static void broadwell_init_clock_gating(struct drm_device *dev) misccpctl =I915_READ (GEN7_MISCCPCTL );I915_WRITE (GEN7_MISCCPCTL , misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE );I915_WRITE (GEN8_L3SQCREG1 ,BDW_WA_L3SQCREG1_DEFAULT ); +/* +* Wait at least 100 clocks before re-enabling clock gating. See +* the definition of L3SQCREG1 in BSpec. +*/ +POSTING_READ (GEN8_L3SQCREG1 ); +udelay (1 );I915_WRITE (GEN7_MISCCPCTL , misccpctl);/*