arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

PATCH Superseded Chin Liang See 2 participants 8 messages Sep 15, 2016 – Sep 21, 2016

lore

Share & tools

lore

Chin Liang See

author

2016-09-15 07:27 UTC #0 lore raw

PATCH 2/9 arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation

Signed-off-by Chin Liang See <[email protected]>

---
 board/altera/arria5-socdk/qts/sdram_config.h   | 3 +++
 board/altera/cyclone5-socdk/qts/sdram_config.h | 3 +++
 2 files changed, 6 insertions(+)

board/altera/arria5-socdk/qts/sdram_config.h +3 -0

index e9fe60f..8964637 100644
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0

board/altera/cyclone5-socdk/qts/sdram_config.h +3 -0

index 37c1476..1bc6f6f 100644
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0

Signature · 1 line

2.2.2

Marek Vasut

2016-09-19 14:24 UTC #1 lore raw

PATCH 2/9 arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

Quoted 2 lines · Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation

... stable ...

Isn't SoCDK using DDR3 DRAM ?

Quoted 35 lines

Signed-off-by Chin Liang See <[email protected]>

---
 board/altera/arria5-socdk/qts/sdram_config.h   | 3 +++
 board/altera/cyclone5-socdk/qts/sdram_config.h | 3 +++
 2 files changed, 6 insertions(+)

board/altera/arria5-socdk/qts/sdram_config.h +3 -0

index e9fe60f..8964637 100644
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0

board/altera/cyclone5-socdk/qts/sdram_config.h +3 -0

index 37c1476..1bc6f6f 100644
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0

Signature · 2 lines

Best regards,
Marek Vasut

Chin Liang See

author

2016-09-19 10:12 UTC #2 lore raw

PATCH 2/9 arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

Quoted 7 lines · Marek Vasut

Quoted 2 lines · Chin Liang See
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation
... stable ...
Isn't SoCDK using DDR3 DRAM ?

Yah, you are right where we won't need this patch and others except #1 one. Should I send v2 which only have first patch?

Thanks
Chin Liang

Quoted 60 lines

Quoted 58 lines
Signed-off-by Chin Liang See <[email protected]>
---
 board/altera/arria5-socdk/qts/sdram_config.h   | 3 +++
 board/altera/cyclone5-socdk/qts/sdram_config.h | 3 +++
 2 files changed, 6 insertions(+)
board/altera/arria5-socdk/qts/sdram_config.h +0 -0
index e9fe60f..8964637 100644
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			
4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT
3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT
512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_C HIP 2
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC
0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE
0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST
0
board/altera/cyclone5-socdk/qts/sdram_config.h +0 -0
index 37c1476..1bc6f6f 100644
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			
3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT
3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT
512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_C HIP 2
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC
0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE
0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST
0

Marek Vasut

2016-09-19 18:52 UTC #3 lore raw

PATCH 2/9 arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

Quoted 11 lines · Chin Liang See

Quoted 7 lines · Marek Vasut
Quoted 2 lines · Chin Liang See
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation
... stable ...
Isn't SoCDK using DDR3 DRAM ?
Yah, you are right where we won't need this patch and others except #1 one. Should I send v2 which only have first patch?

Then should this register be set to zero on SoCDK ?

Signature · 2 lines

Best regards,
Marek Vasut

Chin Liang See

author

2016-09-20 05:37 UTC #4 lore raw

PATCH 2/9 arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

Quoted 8 lines · Marek Vasut

Quoted 7 lines · Chin Liang See
Quoted 6 lines · Marek Vasut
Quoted 2 lines · Chin Liang See
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation
... stable ...

Quoted 7 lines

Quoted 5 lines
Quoted 1 line
Isn't SoCDK using DDR3 DRAM ?
Yah, you are right where we won't need this patch and others except #1
one. Should I send v2 which only have first patch?
Then should this register be set to zero on SoCDK ?

Not required as the default value is zero.

Thanks
Chin Liang

Quoted 2 lines

Marek Vasut

2016-09-20 07:52 UTC #5 lore raw

PATCH 2/9 arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

Quoted 11 lines · Chin Liang See

Quoted 10 lines · Marek Vasut
Quoted 9 lines · Chin Liang See
Quoted 7 lines · Marek Vasut
Quoted 2 lines · Chin Liang See
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation
... stable ...
Isn't SoCDK using DDR3 DRAM ?

Quoted 7 lines

Quoted 5 lines
Quoted 3 lines
Yah, you are right where we won't need this patch and others except #1
one. Should I send v2 which only have first patch?
Then should this register be set to zero on SoCDK ?
Not required as the default value is zero.

OK, if we can avoid the ifdef(s)

Signature · 2 lines

Best regards,
Marek Vasut

Chin Liang See

author

2016-09-20 09:13 UTC #6 lore raw

PATCH 2/9 arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

Quoted 17 lines · Marek Vasut

Quoted 16 lines · Chin Liang See
Quoted 15 lines · Marek Vasut
Quoted 13 lines · Chin Liang See
Quoted 7 lines · Marek Vasut
Quoted 2 lines · Chin Liang See
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation
... stable ...
Isn't SoCDK using DDR3 DRAM ?
Yah, you are right where we won't need this patch and others except
#1
one. Should I send v2 which only have first patch?

Quoted 6 lines

Quoted 3 lines
Quoted 1 line
Then should this register be set to zero on SoCDK ?
Not required as the default value is zero.
OK, if we can avoid the ifdef(s)

Removing the ifdef would requiring the patch against all socfpga boards. As commented by you earlier, all our boards are using DDR3 and this patch for LPDDR2 would not applicable then.

Thanks
Chin Liang

Marek Vasut

2016-09-21 01:19 UTC #7 lore raw

PATCH 2/9 arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

Quoted 20 lines · Chin Liang See

Quoted 19 lines · Marek Vasut
Quoted 18 lines · Chin Liang See
Quoted 16 lines · Marek Vasut
Quoted 5 lines · Chin Liang See
Quoted 4 lines · Marek Vasut
Quoted 2 lines · Chin Liang See
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation
Quoted 8 lines
Quoted 3 lines
... stable ...
Isn't SoCDK using DDR3 DRAM ?
Yah, you are right where we won't need this patch and others except
#1
one. Should I send v2 which only have first patch?
Then should this register be set to zero on SoCDK ?

Quoted 8 lines

Quoted 4 lines
Quoted 1 line
Not required as the default value is zero.
OK, if we can avoid the ifdef(s)
Removing the ifdef would requiring the patch against all socfpga boards. As commented by you earlier, all our boards are using DDR3 and this patch for LPDDR2 would not applicable then.

I'm fine if you add another patch which sets the register or it's macros to 0 for all SoCFPGA boards.

Signature · 2 lines

Best regards,
Marek Vasut