spi: cadence_spi: Adopt Linux DT bindings
Subsystems (2)
v2 cover spi: cadence_spi: Adopt Linux DT bindings
Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch.
Tested on Terasic SoCKit dev board (Altera Cyclone V)
Jason Rush (3):
spi: cadence_spi: Sync DT bindings with Linux
dts: cadence_spi: Sync DT bindings with Linux
config: cadence_spi: Remove defines read from DT
arch/arm/dts/keystone-k2g.dtsi | 5 +++-- arch/arm/dts/socfpga.dtsi | 5 +++-- arch/arm/dts/socfpga_arria10.dtsi | 4 ++-- arch/arm/dts/socfpga_arria5_socdk.dts | 9 ++++----- arch/arm/dts/socfpga_cyclone5_is1.dts | 9 ++++----- arch/arm/dts/socfpga_cyclone5_socdk.dts | 9 ++++----- arch/arm/dts/socfpga_cyclone5_sockit.dts | 9 ++++----- arch/arm/dts/socfpga_cyclone5_socrates.dts | 9 ++++----- arch/arm/dts/socfpga_cyclone5_sr1500.dts | 9 ++++----- arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 18 ++++++++---------- arch/arm/dts/stv0991.dts | 12 +++++++----- drivers/spi/cadence_qspi.c | 20 ++++++++++++-------- drivers/spi/cadence_qspi.h | 6 +++++- drivers/spi/cadence_qspi_apb.c | 15 ++++----------- include/configs/k2g_evm.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/stv0991.h | 1 - 17 files changed, 68 insertions(+), 74 deletions(-)
--
2.1.4
PATCH v2 1/3 spi: cadence_spi: Sync DT bindings with Linux
Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch.
--- drivers/spi/cadence_qspi.c | 20 ++++++++++++-------- drivers/spi/cadence_qspi.h | 6 +++++- drivers/spi/cadence_qspi_apb.c | 15 ++++----------- 3 files changed, 21 insertions(+), 20 deletions(-)
drivers/spi/cadence_qspi.c +12 -8
@@ -212,7 +212,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,/* Set Chip select */ cadence_qspi_apb_chipselect (base,spi_chip_select (dev), -CONFIG_CQSPI_DECODER ); + plat->is_decoded_cs);if ((flags &SPI_XFER_END ) || (flags ==0 )) {if (priv->cmd_len ==0 ) {
@@ -296,7 +296,11 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->regbase = (void *)data[0 ]; plat->ahbbase = (void *)data[2 ]; - plat->sram_size =fdtdec_get_int (blob, node,"sram-size" ,128 ); + plat->is_decoded_cs =fdtdec_get_bool (blob, node,"cdns,is-decoded-cs" ); + plat->fifo_depth =fdtdec_get_uint (blob, node,"cdns,fifo-depth" ,128 ); + plat->fifo_width =fdtdec_get_uint (blob, node,"cdns,fifo-width" ,4 ); + plat->trigger_address =fdtdec_get_uint (blob, node, +"cdns,trigger-address" ,0 );/* All other paramters are embedded in the child node */ subnode =fdt_first_subnode (blob, node);
@@ -310,12 +314,12 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) 500000);/* Read other parameters from DT */ - plat->page_size =fdtdec_get_int (blob, subnode,"page-size" ,256 ); - plat->block_size =fdtdec_get_int (blob, subnode,"block-size" ,16 ); - plat->tshsl_ns =fdtdec_get_int (blob, subnode,"tshsl-ns" ,200 ); - plat->tsd2d_ns =fdtdec_get_int (blob, subnode,"tsd2d-ns" ,255 ); - plat->tchsh_ns =fdtdec_get_int (blob, subnode,"tchsh-ns" ,20 ); - plat->tslch_ns =fdtdec_get_int (blob, subnode,"tslch-ns" ,20 ); + plat->page_size =fdtdec_get_uint (blob, subnode,"page-size" ,256 ); + plat->block_size =fdtdec_get_uint (blob, subnode,"block-size" ,16 ); + plat->tshsl_ns =fdtdec_get_uint (blob, subnode,"cdns,tshsl-ns" ,200 ); + plat->tsd2d_ns =fdtdec_get_uint (blob, subnode,"cdns,tsd2d-ns" ,255 ); + plat->tchsh_ns =fdtdec_get_uint (blob, subnode,"cdns,tchsh-ns" ,20 ); + plat->tslch_ns =fdtdec_get_uint (blob, subnode,"cdns,tslch-ns" ,20 ); debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", __func__, plat->regbase, plat->ahbbase, plat->max_hz,
drivers/spi/cadence_qspi.h +5 -1
@@ -18,14 +18,18 @@ struct cadence_spi_platdata {unsigned int max_hz;void *regbase;void *ahbbase; +bool is_decoded_cs; +u32 fifo_depth; +u32 fifo_width; +u32 trigger_address; +// Flash parameters u32 page_size;u32 block_size;u32 tshsl_ns;u32 tsd2d_ns;u32 tchsh_ns;u32 tslch_ns; -u32 sram_size; };struct cadence_spi_priv {
drivers/spi/cadence_qspi_apb.c +4 -11
@@ -37,10 +37,6 @@#define CQSPI_REG_RETRY 10000#define CQSPI_POLL_IDLE_RETRY 3 -#define CQSPI_FIFO_WIDTH 4 - -#define CQSPI_REG_SRAM_THRESHOLD_WORDS 50 -/* Transfer mode */ #define CQSPI_INST_TYPE_SINGLE 0#define CQSPI_INST_TYPE_DUAL 1
@@ -51,9 +47,6 @@#define CQSPI_DUMMY_CLKS_PER_BYTE 8#define CQSPI_DUMMY_BYTES_MAX 4 -#define CQSPI_REG_SRAM_FILL_THRESHOLD \ - ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH) -/**************************************************************************** * Controller's configuration and status register (offset from QSPI_BASE) ****************************************************************************/
@@ -400,7 +393,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)writel (0 , plat->regbase +CQSPI_REG_REMAP );/* Indirect mode configurations */ -writel ((plat->sram_size/2 ), plat->regbase +CQSPI_REG_SRAMPARTITION ); +writel ((plat->fifo_depth/2 ), plat->regbase +CQSPI_REG_SRAMPARTITION );/* Disable all interrupts */ writel (0 , plat->regbase +CQSPI_REG_IRQMASK );
@@ -560,7 +553,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, addr_bytes = cmdlen -1 ;/* Setup the indirect trigger address */ -writel ((u32 )plat->ahbbase, +writel (plat->trigger_address, plat->regbase +CQSPI_REG_INDIRECTTRIGGER );/* Configure the opcode */
@@ -659,7 +652,7 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, bytes_to_read = ret;while (bytes_to_read !=0 ) { - bytes_to_read *=CQSPI_FIFO_WIDTH ; + bytes_to_read *= plat->fifo_width; bytes_to_read = bytes_to_read > remaining ? remaining : bytes_to_read;readsl (plat->ahbbase, bb_rxbuf, bytes_to_read >>2 );
@@ -710,7 +703,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,return -EINVAL ; }/* Setup the indirect trigger address */ -writel ((u32 )plat->ahbbase, +writel (plat->trigger_address, plat->regbase +CQSPI_REG_INDIRECTTRIGGER );/* Configure the opcode */
Signature · 1 line
2.1.4
PATCH v2 2/3 dts: cadence_spi: Sync DT bindings with Linux
In reply to Jason RushAdopt the Linux DT bindings and clean-up duplicate and unused values.
--- arch/arm/dts/keystone-k2g.dtsi | 5 +++-- arch/arm/dts/socfpga.dtsi | 5 +++-- arch/arm/dts/socfpga_arria10.dtsi | 4 ++-- arch/arm/dts/socfpga_arria5_socdk.dts | 9 ++++----- arch/arm/dts/socfpga_cyclone5_is1.dts | 9 ++++----- arch/arm/dts/socfpga_cyclone5_socdk.dts | 9 ++++----- arch/arm/dts/socfpga_cyclone5_sockit.dts | 9 ++++----- arch/arm/dts/socfpga_cyclone5_socrates.dts | 9 ++++----- arch/arm/dts/socfpga_cyclone5_sr1500.dts | 9 ++++----- arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 18 ++++++++---------- arch/arm/dts/stv0991.dts | 12 +++++++----- 11 files changed, 47 insertions(+), 51 deletions(-)
arch/arm/dts/keystone-k2g.dtsi +3 -2
@@ -96,8 +96,9 @@ <0x24000000 0x4000000>; interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; num-cs = <4>; - fifo-depth = <256>; - sram-size = <256>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x24000000>; status = "disabled"; };
arch/arm/dts/socfpga.dtsi +3 -2
@@ -644,8 +644,9 @@ clocks = <&qspi_clk>; ext-decoder = <0>; /* external decoder */ num-cs = <4>; - fifo-depth = <128>; - sram-size = <128>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; bus-num = <2>; status = "disabled"; };
arch/arm/dts/socfpga_arria10.dtsi +2 -2
@@ -734,8 +734,8 @@ clocks = <&l4_main_clk>; ext-decoder = <0>; /* external decoder */ num-chipselect = <4>; - fifo-depth = <128>; - sram-size = <512>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; bus-num = <2>; status = "disabled"; };
arch/arm/dts/socfpga_arria5_socdk.dts +4 -5
@@ -94,10 +94,9 @@ m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ - read-delay = <4>; /* delay value in read data capture register */ - tshsl-ns = <50>; - tsd2d-ns = <50>; - tchsh-ns = <4>; - tslch-ns = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; }; };
arch/arm/dts/socfpga_cyclone5_is1.dts +4 -5
@@ -93,11 +93,10 @@ m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ - read-delay = <4>; /* delay value in read data capture register */ - tshsl-ns = <50>; - tsd2d-ns = <50>; - tchsh-ns = <4>; - tslch-ns = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; }; };
arch/arm/dts/socfpga_cyclone5_socdk.dts +4 -5
@@ -104,11 +104,10 @@ m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ - read-delay = <4>; /* delay value in read data capture register */ - tshsl-ns = <50>; - tsd2d-ns = <50>; - tchsh-ns = <4>; - tslch-ns = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; }; };
arch/arm/dts/socfpga_cyclone5_sockit.dts +4 -5
@@ -84,11 +84,10 @@ m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ - read-delay = <4>; /* delay value in read data capture register */ - tshsl-ns = <50>; - tsd2d-ns = <50>; - tchsh-ns = <4>; - tslch-ns = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; }; };
arch/arm/dts/socfpga_cyclone5_socrates.dts +4 -5
@@ -74,11 +74,10 @@ m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ - read-delay = <4>; /* delay value in read data capture register */ - tshsl-ns = <50>; - tsd2d-ns = <50>; - tchsh-ns = <4>; - tslch-ns = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; }; };
arch/arm/dts/socfpga_cyclone5_sr1500.dts +4 -5
@@ -92,10 +92,9 @@ m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ - read-delay = <4>; /* delay value in read data capture register */ - tshsl-ns = <50>; - tsd2d-ns = <50>; - tchsh-ns = <4>; - tslch-ns = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; }; };
arch/arm/dts/socfpga_cyclone5_vining_fpga.dts +8 -10
@@ -79,11 +79,10 @@ m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ - read-delay = <4>; /* delay value in read data capture register */ - tshsl-ns = <50>; - tsd2d-ns = <50>; - tchsh-ns = <4>; - tslch-ns = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; }; flash1: n25q00 at 1 {
@@ -96,11 +95,10 @@ m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ - read-delay = <4>; /* delay value in read data capture register */ - tshsl-ns = <50>; - tsd2d-ns = <50>; - tchsh-ns = <4>; - tslch-ns = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; }; };
arch/arm/dts/stv0991.dts +7 -5
@@ -32,7 +32,9 @@ reg = <0x80203000 0x100>, <0x40000000 0x1000000>; clocks = <3750000>; - sram-size = <256>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x40000000>; status = "okay"; flash0: n25q32 at 0 {
@@ -44,10 +46,10 @@ m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ - tshsl-ns = <50>; - tsd2d-ns = <50>; - tchsh-ns = <4>; - tslch-ns = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; }; }; };
Signature · 1 line
2.1.4
PATCH v2 2/3 dts: cadence_spi: Sync DT bindings with Linux
Quoted 4 lines · Jason Rush
Adopt the Linux DT bindings and clean-up duplicate and unused values.
--- arch/arm/dts/keystone-k2g.dtsi | 5 +++--
Thanks for doing this patch!
Could you change the bindings for delay values in arch/arm/dts/keystone-k2g-evm.dts as well?
Since, you are removing support for old bindings, QSPI will no longer in U-Boot on K2G.
These bindings don't exist in upstream kernel DT as K2G is not completely supported in mainline yet, but will be added shortly.
Signature · 2 lines
Regards Vignesh
PATCH v2 2/3 dts: cadence_spi: Sync DT bindings with Linux
Quoted 10 lines · Vignesh R
Quoted 4 lines · Jason Rush
Adopt the Linux DT bindings and clean-up duplicate and unused values.
--- arch/arm/dts/keystone-k2g.dtsi | 5 +++--Thanks for doing this patch!
Thanks indeed, someone finally did what needed to be done for a LONG time. Appreciated.
Quoted 7 lines
Could you change the bindings for delay values in
arch/arm/dts/keystone-k2g-evm.dtsas well?
Since, you are removing support for old bindings, QSPI will no longer in U-Boot on K2G.
These bindings don't exist in upstream kernel DT as K2G is not completely supported in mainline yet, but will be added shortly.
Signature · 2 lines
Best regards, Marek Vasut
PATCH v2 2/3 dts: cadence_spi: Sync DT bindings with Linux
In reply to Vignesh RQuoted 6 lines · Vignesh R
Quoted 4 lines · Jason Rush
Adopt the Linux DT bindings and clean-up duplicate and unused values.
--- arch/arm/dts/keystone-k2g.dtsi | 5 +++--
Quoted 8 lines
Thanks for doing this patch!
Could you change the bindings for delay values inarch/arm/dts/keystone-k2g-evm.dtsas well?
Since, you are removing support for old bindings, QSPI will no longer in U-Boot on K2G.
These bindings don't exist in upstream kernel DT as K2G is not completely supported in mainline yet, but will be added shortly.
I must have missed that dts file. I'll submit a v3 with it included.
PATCH v2 3/3 config: cadence_spi: Remove defines read from DT
In reply to Jason RushCleanup unused #define values that are read from the DT.
--- include/configs/k2g_evm.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/stv0991.h | 1 - 3 files changed, 3 deletions(-)
include/configs/k2g_evm.h +0 -1
@@ -75,7 +75,6 @@#ifndef CONFIG_SPL_BUILD #define CONFIG_CADENCE_QSPI #define CONFIG_CQSPI_REF_CLK 384000000 -#define CONFIG_CQSPI_DECODER 0x0#define CONFIG_BOUNCE_BUFFER #endif
include/configs/socfpga_common.h +0 -1
@@ -200,7 +200,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);unsigned int cm_get_qspi_controller_clk_hz (void );#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()#endif -#define CONFIG_CQSPI_DECODER 0#define CONFIG_BOUNCE_BUFFER /*
include/configs/stv0991.h +0 -1
@@ -68,7 +68,6 @@+ * QSPI support + */ #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ -#define CONFIG_CQSPI_DECODER 0#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000#define CONFIG_BOUNCE_BUFFER
Signature · 1 line
2.1.4