riscv: Add qspinlock/qrwlock
[email protected]
maintainerv3 cover riscv: Add qspinlock/qrwlock
From: Guo Ren <[email protected]>
Current riscv is still using baby spinlock implementation. It'll cause fairness and cache line bouncing problems. Many people are involved and pay the efforts to improve it:
- The first version of patch was made in 2019.1:
https://lore.kernel.org/linux-riscv/[email protected]/#r
- The second version was made in 2020.11:
https://lore.kernel.org/linux-riscv/[email protected]/
- A good discussion at Platform HSC.2021-03-08:
https://drive.google.com/drive/folders/1ooqdnIsYx7XKor5O1XTtM6D1CHp4hc0p
Hope your comments and Tested-by or Co-developed-by or Reviewed-by ...
Let's kick the qspinlock into riscv right now (Also for the architectures which doesn't have short atmoic xchg instructions.)
Change V3:
- Fixup short-xchg asm code (slli -> slliw, srli -> srliw)
- Coding convention by Peter Zijlstra's advices
Change V2:
- Coding convention in cmpxchg.h
- Re-implement short xchg
- Remove char & cmpxchg implementations
V1: (by michael)
Guo Ren (3):
riscv: cmpxchg.h: Cleanup unused code
riscv: cmpxchg.h: Merge macros
riscv: cmpxchg.h: Implement xchg for short
Michael Clark (1):
riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
arch/riscv/Kconfig | 2 + arch/riscv/include/asm/Kbuild | 3 + arch/riscv/include/asm/cmpxchg.h | 211 ++++++------------------ arch/riscv/include/asm/spinlock.h | 126 +------------- arch/riscv/include/asm/spinlock_types.h | 15 +- 5 files changed, 58 insertions(+), 299 deletions(-)
Signature · 1 line
2.17.1
[email protected]
maintainerPATCH v3 1/4 riscv: cmpxchg.h: Cleanup unused code
From: Guo Ren <[email protected]>
Remove unnecessary marco, they are no use or handled by generic files (atomic-fallback.h, asm-generic/cmpxchg*).
--- arch/riscv/include/asm/cmpxchg.h | 83 -------------------------------- 1 file changed, 83 deletions(-)
arch/riscv/include/asm/cmpxchg.h +0 -83
@@ -72,13 +72,6 @@ __ret; \ }) -#define xchg_acquire (ptr, x) \ -({ \ - __typeof__(*(ptr)) _x_ = (x); \ - (__typeof__(*(ptr))) __xchg_acquire((ptr), \ - _x_, sizeof(*(ptr))); \ -}) -#define __xchg_release (ptr, new, size) \ ({ \ __typeof__(ptr) __ptr = (ptr); \
@@ -107,13 +100,6 @@ __ret; \ }) -#define xchg_release (ptr, x) \ -({ \ - __typeof__(*(ptr)) _x_ = (x); \ - (__typeof__(*(ptr))) __xchg_release((ptr), \ - _x_, sizeof(*(ptr))); \ -}) -#define __xchg (ptr, new, size) \ ({ \ __typeof__(ptr) __ptr = (ptr); \
@@ -140,24 +126,6 @@ __ret; \ }) -#define xchg (ptr, x) \ -({ \ - __typeof__(*(ptr)) _x_ = (x); \ - (__typeof__(*(ptr))) __xchg((ptr), _x_, sizeof(*(ptr))); \ -}) - -#define xchg32 (ptr, x) \ -({ \ - BUILD_BUG_ON(sizeof(*(ptr)) != 4); \ - xchg((ptr), (x)); \ -}) - -#define xchg64 (ptr, x) \ -({ \ - BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ - xchg((ptr), (x)); \ -}) -/* * Atomic compare and exchange. Compare OLD with MEM, if identical, * store NEW in MEM. Return the initial value in MEM. Success is
@@ -245,14 +213,6 @@ __ret; \ }) -#define cmpxchg_acquire (ptr, o, n) \ -({ \ - __typeof__(*(ptr)) _o_ = (o); \ - __typeof__(*(ptr)) _n_ = (n); \ - (__typeof__(*(ptr))) __cmpxchg_acquire((ptr), \ - _o_, _n_, sizeof(*(ptr))); \ -}) -#define __cmpxchg_release (ptr, old, new, size) \ ({ \ __typeof__(ptr) __ptr = (ptr); \
@@ -291,14 +251,6 @@ __ret; \ }) -#define cmpxchg_release (ptr, o, n) \ -({ \ - __typeof__(*(ptr)) _o_ = (o); \ - __typeof__(*(ptr)) _n_ = (n); \ - (__typeof__(*(ptr))) __cmpxchg_release((ptr), \ - _o_, _n_, sizeof(*(ptr))); \ -}) -#define __cmpxchg (ptr, old, new, size) \ ({ \ __typeof__(ptr) __ptr = (ptr); \
@@ -337,39 +289,4 @@ __ret; \ }) -#define cmpxchg (ptr, o, n) \ -({ \ - __typeof__(*(ptr)) _o_ = (o); \ - __typeof__(*(ptr)) _n_ = (n); \ - (__typeof__(*(ptr))) __cmpxchg((ptr), \ - _o_, _n_, sizeof(*(ptr))); \ -}) - -#define cmpxchg_local (ptr, o, n) \ - (__cmpxchg_relaxed((ptr), (o), (n), sizeof(*(ptr)))) - -#define cmpxchg32 (ptr, o, n) \ -({ \ - BUILD_BUG_ON(sizeof(*(ptr)) != 4); \ - cmpxchg((ptr), (o), (n)); \ -}) - -#define cmpxchg32_local (ptr, o, n) \ -({ \ - BUILD_BUG_ON(sizeof(*(ptr)) != 4); \ - cmpxchg_relaxed((ptr), (o), (n)) \ -}) - -#define cmpxchg64 (ptr, o, n) \ -({ \ - BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ - cmpxchg((ptr), (o), (n)); \ -}) - -#define cmpxchg64_local (ptr, o, n) \ -({ \ - BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ - cmpxchg_relaxed((ptr), (o), (n)); \ -}) -#endif /* _ASM_RISCV_CMPXCHG_H */
Signature · 1 line
2.17.1
[email protected]
maintainerPATCH v3 2/4 riscv: cmpxchg.h: Merge macros
In reply to [email protected]From: Guo Ren <[email protected]>
To reduce assembly codes, let's merge duplicate codes into one (xchg_acquire, xchg_release, cmpxchg_release).
--- arch/riscv/include/asm/cmpxchg.h | 92 +++++--------------------------- 1 file changed, 12 insertions(+), 80 deletions(-)
arch/riscv/include/asm/cmpxchg.h +12 -80
@@ -11,6 +11,12 @@#include <asm/barrier.h> #include <asm/fence.h> +#define __local_acquire_fence () \ + __asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory") + +#define __local_release_fence () \ + __asm__ __volatile__(RISCV_RELEASE_BARRIER "" ::: "memory") +#define __xchg_relaxed (ptr, new, size) \ ({ \ __typeof__(ptr) __ptr = (ptr); \
@@ -46,58 +52,16 @@#define __xchg_acquire (ptr, new, size) \ ({ \ - __typeof__(ptr) __ptr = (ptr); \ - __typeof__(new) __new = (new); \ __typeof__(*(ptr)) __ret; \ - switch (size) { \ - case 4: \ - __asm__ __volatile__ ( \ - " amoswap.w %0, %2, %1\n" \ - RISCV_ACQUIRE_BARRIER \ - : "=r" (__ret), "+A" (*__ptr) \ - : "r" (__new) \ - : "memory"); \ - break; \ - case 8: \ - __asm__ __volatile__ ( \ - " amoswap.d %0, %2, %1\n" \ - RISCV_ACQUIRE_BARRIER \ - : "=r" (__ret), "+A" (*__ptr) \ - : "r" (__new) \ - : "memory"); \ - break; \ - default: \ - BUILD_BUG(); \ - } \ + __ret = __xchg_relaxed(ptr, new, size); \ + __local_acquire_fence(); \ __ret; \ })#define __xchg_release (ptr, new, size) \ ({ \ - __typeof__(ptr) __ptr = (ptr); \ - __typeof__(new) __new = (new); \ - __typeof__(*(ptr)) __ret; \ - switch (size) { \ - case 4: \ - __asm__ __volatile__ ( \ - RISCV_RELEASE_BARRIER \ - " amoswap.w %0, %2, %1\n" \ - : "=r" (__ret), "+A" (*__ptr) \ - : "r" (__new) \ - : "memory"); \ - break; \ - case 8: \ - __asm__ __volatile__ ( \ - RISCV_RELEASE_BARRIER \ - " amoswap.d %0, %2, %1\n" \ - : "=r" (__ret), "+A" (*__ptr) \ - : "r" (__new) \ - : "memory"); \ - break; \ - default: \ - BUILD_BUG(); \ - } \ - __ret; \ + __local_release_fence(); \ + __xchg_relaxed(ptr, new, size); \ })#define __xchg (ptr, new, size) \
@@ -215,40 +179,8 @@#define __cmpxchg_release (ptr, old, new, size) \ ({ \ - __typeof__(ptr) __ptr = (ptr); \ - __typeof__(*(ptr)) __old = (old); \ - __typeof__(*(ptr)) __new = (new); \ - __typeof__(*(ptr)) __ret; \ - register unsigned int __rc; \ - switch (size) { \ - case 4: \ - __asm__ __volatile__ ( \ - RISCV_RELEASE_BARRIER \ - "0: lr.w %0, %2\n" \ - " bne %0, %z3, 1f\n" \ - " sc.w %1, %z4, %2\n" \ - " bnez %1, 0b\n" \ - "1:\n" \ - : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ - : "rJ" ((long)__old), "rJ" (__new) \ - : "memory"); \ - break; \ - case 8: \ - __asm__ __volatile__ ( \ - RISCV_RELEASE_BARRIER \ - "0: lr.d %0, %2\n" \ - " bne %0, %z3, 1f\n" \ - " sc.d %1, %z4, %2\n" \ - " bnez %1, 0b\n" \ - "1:\n" \ - : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ - : "rJ" (__old), "rJ" (__new) \ - : "memory"); \ - break; \ - default: \ - BUILD_BUG(); \ - } \ - __ret; \ + __local_release_fence(); \ + __cmpxchg_relaxed(ptr, old, new, size); \ })#define __cmpxchg (ptr, old, new, size) \
Signature · 1 line
2.17.1
[email protected]
maintainerPATCH v3 3/4 riscv: cmpxchg.h: Implement xchg for short
In reply to [email protected]From: Guo Ren <[email protected]>
riscv only support lr.wd/s(c).w(d) with word(double word) size & align access. There are not lr.h/sc.h instructions. But qspinlock.c need xchg with short type variable:
xchg_tail -> xchg_releaxed(&lock->tail, ...
typedef struct qspinlock {
union {
atomic_t val;
/*
* By using the whole 2nd least significant byte for the
* pending bit, we can allow better optimization of the lock
* acquisition for the pending bit holder.
*/
struct {
u8 locked;
u8 pending;
};
struct {
u16 locked_pending;
u16 tail; /* half word*/
};
};
} arch_spinlock_t;So we add short emulation in xchg with word length and it only solve qspinlock's requirement.
Michael has sent another implementation, see the Link below.
--- arch/riscv/include/asm/cmpxchg.h | 36 ++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
arch/riscv/include/asm/cmpxchg.h +36 -0
@@ -22,7 +22,43 @@__typeof__ (ptr) __ptr = (ptr); \__typeof__ (new) __new = (new); \ __typeof__(*(ptr)) __ret; \ + registerunsigned long __rc, tmp, align, addr; \switch (size) { \ +case 2 : \ + align = ((unsigned long ) __ptr &0x3 ); \ + addr = ((unsigned long ) __ptr & ~0x3 ); \ +if (align) { \ + __asm__ __volatile__ ( \ +"0: lr.w %0, (%4) \n" \ +" mv %1, %0 \n" \ +" slliw %1, %1, 16 \n" \ +" srliw %1, %1, 16 \n" \ +" mv %2, %3 \n" \ +" slliw %2, %2, 16 \n" \ +" or %1, %2, %1 \n" \ +" sc.w %2, %1, (%4) \n" \ +" bnez %2, 0b \n" \ +" srliw %0, %0, 16 \n" \ + :"=&r" (__ret),"=&r" (tmp),"=&r" (__rc) \ + :"r" (__new),"r" (addr) \ + :"memory" ); \ + }else { \ + __asm__ __volatile__ ( \ +"0: lr.w %0, (%4) \n" \ +" mv %1, %0 \n" \ +" srliw %1, %1, 16 \n" \ +" slliw %1, %1, 16 \n" \ +" mv %2, %3 \n" \ +" or %1, %2, %1 \n" \ +" sc.w %2, %1, 0(%4) \n" \ +" bnez %2, 0b \n" \ +" slliw %0, %0, 16 \n" \ +" srliw %0, %0, 16 \n" \ + :"=&r" (__ret),"=&r" (tmp),"=&r" (__rc) \ + :"r" (__new),"r" (addr) \ + :"memory" ); \ + } \ +break ; \case 4 : \ __asm__ __volatile__ ( \ " amoswap.w %0, %2, %1\n" \
Signature · 1 line
2.17.1
[email protected]
maintainerPATCH v3 4/4 riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
In reply to [email protected]From: Michael Clark <[email protected]>
Update the RISC-V port to use the generic qspinlock and qrwlock.
This patch requires support for xchg for short which are added by a previous patch.
Guo fixed up compile error which made by below include sequence:
+#include <asm/qrwlock.h>
+#include <asm/qspinlock.h>
--- arch/riscv/Kconfig | 2 + arch/riscv/include/asm/Kbuild | 3 + arch/riscv/include/asm/spinlock.h | 126 +----------------------- arch/riscv/include/asm/spinlock_types.h | 15 +-- 4 files changed, 10 insertions(+), 136 deletions(-)
arch/riscv/Kconfig +2 -0
@@ -33,6 +33,8 @@ config RISCV select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU select ARCH_WANT_FRAME_POINTERS select ARCH_WANT_HUGE_PMD_SHARE if 64BIT + select ARCH_USE_QUEUED_RWLOCKS + select ARCH_USE_QUEUED_SPINLOCKS select CLONE_BACKWARDS select CLINT_TIMER if !MMU select COMMON_CLK
arch/riscv/include/asm/Kbuild +3 -0
@@ -3,5 +3,8 @@ generic-y += early_ioremap.h generic-y += extable.h generic-y += flat.h generic-y += kvm_para.h +generic-y += mcs_spinlock.h +generic-y += qrwlock.h +generic-y += qspinlock.h generic-y += user.h generic-y += vmlinux.lds.h
arch/riscv/include/asm/spinlock.h +2 -124
131 lines not on this page · raw message
arch/riscv/include/asm/spinlock_types.h +3 -12
@@ -6,20 +6,11 @@#ifndef _ASM_RISCV_SPINLOCK_TYPES_H#define _ASM_RISCV_SPINLOCK_TYPES_H -#ifndef __LINUX_SPINLOCK_TYPES_H +#if !defined(__LINUX_SPINLOCK_TYPES_H) && !defined(_ASM_RISCV_SPINLOCK_H)# error "please don't include this file directly"#endif -typedef struct { -volatile unsigned int lock; -}arch_spinlock_t ; - -#define __ARCH_SPIN_LOCK_UNLOCKED { 0 } - -typedef struct { -volatile unsigned int lock; -}arch_rwlock_t ; - -#define __ARCH_RW_LOCK_UNLOCKED { 0 } +#include <asm-generic/qspinlock_types.h> +#include <asm-generic/qrwlock_types.h> #endif /* _ASM_RISCV_SPINLOCK_TYPES_H */
Signature · 1 line
2.17.1
kernel test robot
build botRe: [PATCH v3 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
Thank you for the patch! Yet something to improve:
Hi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on tip/locking/core]
[also build test ERROR on linux/master linus/master v5.12-rc4 next-20210325] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933 base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 5965a7adbd72dd9b288c0911cb73719fed1efa08 config: riscv-rv32_defconfig (attached as .config) compiler: riscv32-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/2bf2d117ab34b007089e20e1c46eff89b5da097e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933 git checkout 2bf2d117ab34b007089e20e1c46eff89b5da097e
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
All errors (new ones prefixed by >>):
kernel/locking/qspinlock.c: Assembler messages:
kernel/locking/qspinlock.c:184: Error: unrecognized opcode srliw t1,t1,16' kernel/locking/qspinlock.c:185: Error: unrecognized opcode slliw t1,t1,16'
>> kernel/locking/qspinlock.c:190: Error: unrecognized opcode `slliw a6,a6,16' >> kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16' kernel/locking/qspinlock.c:184: Error: unrecognized opcode `slliw t1,t1,16' kernel/locking/qspinlock.c:185: Error: unrecognized opcode `srliw t1,t1,16' kernel/locking/qspinlock.c:187: Error: unrecognized opcode `slliw t3,t3,16' >> kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'
vim +190 kernel/locking/qspinlock.c
69f9cae90907e0 Peter Zijlstra (Intel 2015-04-24 187)
59fb586b4a07b4 Will Deacon 2018-04-26 188 /**
59fb586b4a07b4 Will Deacon 2018-04-26 189 * clear_pending - clear the pending bit.
59fb586b4a07b4 Will Deacon 2018-04-26 @190 * @lock: Pointer to queued spinlock structure
59fb586b4a07b4 Will Deacon 2018-04-26 @191 *
59fb586b4a07b4 Will Deacon 2018-04-26 192 * *,1,* -> *,0,*
59fb586b4a07b4 Will Deacon 2018-04-26 193 */
59fb586b4a07b4 Will Deacon 2018-04-26 194 static __always_inline void clear_pending(struct qspinlock *lock)
59fb586b4a07b4 Will Deacon 2018-04-26 195 {
59fb586b4a07b4 Will Deacon 2018-04-26 196 atomic_andnot(_Q_PENDING_VAL, &lock->val);
59fb586b4a07b4 Will Deacon 2018-04-26 197 }
59fb586b4a07b4 Will Deacon 2018-04-26 198 ---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
Guo Ren
maintainerRe: [PATCH v3 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
haha, I forgot RV32, it needs a
#ifdef RV32
srliw
#else
srli
#endif
Quoted 59 lines · kernel test robot
Hi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on tip/locking/core]
[also build test ERROR on linux/master linus/master v5.12-rc4 next-20210325] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]url: https://github.com/0day-ci/linux/commits/guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933 base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 5965a7adbd72dd9b288c0911cb73719fed1efa08 config: riscv-rv32_defconfig (attached as .config) compiler: riscv32-linux-gcc (GCC) 9.3.0reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/2bf2d117ab34b007089e20e1c46eff89b5da097e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933 git checkout2bf2d117ab34b007089e20e1c46eff89b5da097e
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscvIf you fix the issue, kindly add following tag as appropriate
Reported-by kernel test robot <[email protected]>All errors (new ones prefixed by >>):
kernel/locking/qspinlock.c: Assembler messages:
kernel/locking/qspinlock.c:184: Error: unrecognized opcodesrliw t1,t1,16' kernel/locking/qspinlock.c:185: Error: unrecognized opcodeslliw t1,t1,16'Quoted 2 lines
Quoted 2 lines
kernel/locking/qspinlock.c:190: Error: unrecognized opcodeslliw a6,a6,16' kernel/locking/qspinlock.c:191: Error: unrecognized opcodesrliw a6,a6,16'
kernel/locking/qspinlock.c:184: Error: unrecognized opcodeslliw t1,t1,16' kernel/locking/qspinlock.c:185: Error: unrecognized opcodesrliw t1,t1,16'kernel/locking/qspinlock.c:187: Error: unrecognized opcode `slliw t3,t3,16'Quoted 1 line
Quoted 1 line
kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'vim +190
kernel/locking/qspinlock.c69f9cae90907e0 Peter Zijlstra (Intel 2015-04-24 187) 59fb586b4a07b4 Will Deacon 2018-04-26 188 /** 59fb586b4a07b4 Will Deacon 2018-04-26 189 * clear_pending - clear the pending bit. 59fb586b4a07b4 Will Deacon 2018-04-26 @190 * @lock: Pointer to queued spinlock structure 59fb586b4a07b4 Will Deacon 2018-04-26 @191 * 59fb586b4a07b4 Will Deacon 2018-04-26 192 * *,1,* -> *,0,* 59fb586b4a07b4 Will Deacon 2018-04-26 193 */ 59fb586b4a07b4 Will Deacon 2018-04-26 194 static __always_inline void clear_pending(struct qspinlock *lock) 59fb586b4a07b4 Will Deacon 2018-04-26 195 { 59fb586b4a07b4 Will Deacon 2018-04-26 196 atomic_andnot(_Q_PENDING_VAL, &lock->val); 59fb586b4a07b4 Will Deacon 2018-04-26 197 } 59fb586b4a07b4 Will Deacon 2018-04-26 198---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
Signature · 4 lines
Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/
Guo Ren
maintainerRe: [PATCH v3 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
arch/riscv/include/asm/cmpxchg.h +8 -0
@@ -17,6 +17,14 @@#define __local_release_fence () \ __asm__ __volatile__(RISCV_RELEASE_BARRIER "" ::: "memory") +#ifdef CONFIG_32BIT +#define __ASM_SLLIW "slli\t" +#define __ASM_SRLIW "srli\t" +#else +#define __ASM_SLLIW "slliw\t" +#define __ASM_SRLIW "srliw\t" +#endif +#define __xchg_relaxed (ptr, new, size) \ ({ \
__typeof__(ptr) __ptr = (ptr); \
@@ -31,14 +39,14 @@
__asm__ __volatile__ ( \
"0: lr.w %0, (%4) \n" \
" mv %1, %0 \n" \
- " slliw %1, %1, 16 \n" \
- " srliw %1, %1, 16 \n" \
+ __ASM_SLLIW "%1, %1, 16 \n" \
+ __ASM_SRLIW "%1, %1, 16 \n" \
" mv %2, %3 \n" \
- " slliw %2, %2, 16 \n" \
+ __ASM_SLLIW "%2, %2, 16 \n" \
" or %1, %2, %1 \n" \
" sc.w %2, %1, (%4) \n" \
" bnez %2, 0b \n" \
- " srliw %0, %0, 16 \n" \
+ __ASM_SRLIW "%0, %0, 16 \n" \
: "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \
: "r" (__new), "r"(addr) \
: "memory"); \
@@ -46,14 +54,14 @@
__asm__ __volatile__ ( \
"0: lr.w %0, (%4) \n" \
" mv %1, %0 \n" \
- " srliw %1, %1, 16 \n" \
- " slliw %1, %1, 16 \n" \
+ __ASM_SRLIW "%1, %1, 16 \n" \
+ __ASM_SLLIW "%1, %1, 16 \n" \
" mv %2, %3 \n" \
" or %1, %2, %1 \n" \
" sc.w %2, %1, 0(%4) \n" \
" bnez %2, 0b \n" \
- " slliw %0, %0, 16 \n" \
- " srliw %0, %0, 16 \n" \
+ __ASM_SLLIW "%0, %0, 16 \n" \
+ __ASM_SRLIW "%0, %0, 16 \n" \
: "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \
: "r" (__new), "r"(addr) \
: "memory"); \Quoted 77 lines · Guo Ren
haha, I forgot RV32, it needs a
#ifdef RV32
srliw
#else
srli
#endifQuoted 56 lines · kernel test robot
Hi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on tip/locking/core]
[also build test ERROR on linux/master linus/master v5.12-rc4 next-20210325] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]url: https://github.com/0day-ci/linux/commits/guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933 base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 5965a7adbd72dd9b288c0911cb73719fed1efa08 config: riscv-rv32_defconfig (attached as .config) compiler: riscv32-linux-gcc (GCC) 9.3.0reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/2bf2d117ab34b007089e20e1c46eff89b5da097e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933 git checkout2bf2d117ab34b007089e20e1c46eff89b5da097e
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscvIf you fix the issue, kindly add following tag as appropriate
Reported-by kernel test robot <[email protected]>All errors (new ones prefixed by >>):
kernel/locking/qspinlock.c: Assembler messages:
kernel/locking/qspinlock.c:184: Error: unrecognized opcodesrliw t1,t1,16' kernel/locking/qspinlock.c:185: Error: unrecognized opcodeslliw t1,t1,16'Quoted 2 lines
Quoted 2 lines
kernel/locking/qspinlock.c:190: Error: unrecognized opcodeslliw a6,a6,16' kernel/locking/qspinlock.c:191: Error: unrecognized opcodesrliw a6,a6,16'
kernel/locking/qspinlock.c:184: Error: unrecognized opcodeslliw t1,t1,16' kernel/locking/qspinlock.c:185: Error: unrecognized opcodesrliw t1,t1,16'kernel/locking/qspinlock.c:187: Error: unrecognized opcode `slliw t3,t3,16'Quoted 1 line
Quoted 1 line
kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'vim +190
kernel/locking/qspinlock.c69f9cae90907e0 Peter Zijlstra (Intel 2015-04-24 187) 59fb586b4a07b4 Will Deacon 2018-04-26 188 /** 59fb586b4a07b4 Will Deacon 2018-04-26 189 * clear_pending - clear the pending bit. 59fb586b4a07b4 Will Deacon 2018-04-26 @190 * @lock: Pointer to queued spinlock structure 59fb586b4a07b4 Will Deacon 2018-04-26 @191 * 59fb586b4a07b4 Will Deacon 2018-04-26 192 * *,1,* -> *,0,* 59fb586b4a07b4 Will Deacon 2018-04-26 193 */ 59fb586b4a07b4 Will Deacon 2018-04-26 194 static __always_inline void clear_pending(struct qspinlock *lock) 59fb586b4a07b4 Will Deacon 2018-04-26 195 { 59fb586b4a07b4 Will Deacon 2018-04-26 196 atomic_andnot(_Q_PENDING_VAL, &lock->val); 59fb586b4a07b4 Will Deacon 2018-04-26 197 } 59fb586b4a07b4 Will Deacon 2018-04-26 198Quoted 3 lines
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0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org--
Best Regards
Guo Ren
Signature · 4 lines
Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/