Linux 4.19.266
Greg Kroah-Hartman
maintainerDocumentation/admin-guide/kernel-parameters.txt +13 -0
@@ -4132,6 +4132,18 @@ retain_initrd [RAM] Keep initrd memory after extraction + retbleed= [X86] Control mitigation of RETBleed (Arbitrary + Speculative Code Execution with Return Instructions) + vulnerability. + + off - unconditionally disable + auto - automatically select a migitation + + Selecting 'auto' will choose a mitigation method at run + time according to the CPU. + + Not specifying this option is equivalent to retbleed=auto. + rfkill.default_state= 0 "airplane mode". All wifi, bluetooth, wimax, gps, fm, etc. communication is blocked by default.
@@ -4377,6 +4389,7 @@ eibrs - enhanced IBRS eibrs,retpoline - enhanced IBRS + Retpolines eibrs,lfence - enhanced IBRS + LFENCE + ibrs - use IBRS to protect kernel Not specifying this option is equivalent to spectre_v2=auto.
Makefile +1 -1
@@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 265 +SUBLEVEL = 266 EXTRAVERSION = NAME = "People's Front"
arch/x86/entry/calling.h +59 -9
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arch/x86/entry/entry_32.S +0 -2
@@ -643,7 +643,6 @@ ENTRY(__switch_to_asm) movl %ebx, PER_CPU_VAR(stack_canary)+stack_canary_offset #endif -#ifdef CONFIG_RETPOLINE /* * When switching from a shallower to a deeper call stack * the RSB may either underflow or use entries populated
@@ -652,7 +651,6 @@ ENTRY(__switch_to_asm) * speculative execution to prevent attack. */ FILL_RETURN_BUFFER %ebx, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW -#endif /* restore callee-saved registers */ popfl
arch/x86/entry/entry_64.S +29 -5
@@ -235,6 +235,10 @@ GLOBAL(entry_SYSCALL_64_after_hwframe) /* IRQs are off. */ movq %rax, %rdi movq %rsp, %rsi + + /* clobbers %rax, make sure it is after saving the syscall nr */ + IBRS_ENTER + call do_syscall_64 /* returns with IRQs disabled */ TRACE_IRQS_IRETQ /* we're about to change IF */
@@ -311,8 +315,8 @@ GLOBAL(entry_SYSCALL_64_after_hwframe) * perf profiles. Nothing jumps here. */ syscall_return_via_sysret: - /* rcx and r11 are already restored (see code above) */ - POP_REGS pop_rdi=0 skip_r11rcx=1 + IBRS_EXIT + POP_REGS pop_rdi=0 /* * Now all regs are restored except RSP and RDI.
@@ -363,7 +367,6 @@ ENTRY(__switch_to_asm) movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset #endif -#ifdef CONFIG_RETPOLINE /* * When switching from a shallower to a deeper call stack * the RSB may either underflow or use entries populated
@@ -372,7 +375,6 @@ ENTRY(__switch_to_asm) * speculative execution to prevent attack. */ FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW -#endif /* restore callee-saved registers */ popfq
@@ -685,6 +687,7 @@ GLOBAL(retint_user) TRACE_IRQS_IRETQ GLOBAL(swapgs_restore_regs_and_return_to_usermode) + IBRS_EXIT #ifdef CONFIG_DEBUG_ENTRY /* Assert that pt_regs indicates user mode. */ testb $3, CS(%rsp)
@@ -1250,7 +1253,13 @@ ENTRY(paranoid_entry) */ FENCE_SWAPGS_KERNEL_ENTRY - ret + /* + * Once we have CR3 and %GS setup save and set SPEC_CTRL. Just like + * CR3 above, keep the old value in a callee saved register. + */ + IBRS_ENTER save_reg=%r15 + + RET END(paranoid_entry) /*
@@ -1278,12 +1287,20 @@ ENTRY(paranoid_exit) jmp .Lparanoid_exit_restore .Lparanoid_exit_no_swapgs: TRACE_IRQS_IRETQ_DEBUG + + /* + * Must restore IBRS state before both CR3 and %GS since we need access + * to the per-CPU x86_spec_ctrl_shadow variable. + */ + IBRS_EXIT save_reg=%r15 + /* Always restore stashed CR3 value (see paranoid_entry) */ RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 .Lparanoid_exit_restore: jmp restore_regs_and_return_to_kernel END(paranoid_exit) + /* * Save all registers in pt_regs, and switch GS if needed. */
@@ -1303,6 +1320,7 @@ ENTRY(error_entry) FENCE_SWAPGS_USER_ENTRY /* We have user CR3. Change to kernel CR3. */ SWITCH_TO_KERNEL_CR3 scratch_reg=%rax + IBRS_ENTER .Lerror_entry_from_usermode_after_swapgs: /* Put us onto the real thread stack. */
@@ -1367,6 +1385,7 @@ ENTRY(error_entry) SWAPGS FENCE_SWAPGS_USER_ENTRY SWITCH_TO_KERNEL_CR3 scratch_reg=%rax + IBRS_ENTER /* * Pretend that the exception came from user mode: set up pt_regs
@@ -1472,6 +1491,8 @@ ENTRY(nmi) PUSH_AND_CLEAR_REGS rdx=(%rdx) ENCODE_FRAME_POINTER + IBRS_ENTER + /* * At this point we no longer need to worry about stack damage * due to nesting -- we're on the normal thread stack and we're
@@ -1695,6 +1716,9 @@ end_repeat_nmi: movq $-1, %rsi call do_nmi + /* Always restore stashed SPEC_CTRL value (see paranoid_entry) */ + IBRS_EXIT save_reg=%r15 + /* Always restore stashed CR3 value (see paranoid_entry) */ RESTORE_CR3 scratch_reg=%r15 save_reg=%r14
arch/x86/entry/entry_64_compat.S +10 -1
@@ -4,7 +4,6 @@ * * Copyright 2000-2002 Andi Kleen, SuSE Labs. */ -#include "calling.h" #include <asm/asm-offsets.h> #include <asm/current.h> #include <asm/errno.h>
@@ -17,6 +16,8 @@ #include <linux/linkage.h> #include <linux/err.h> +#include "calling.h" + .section .entry.text, "ax" /*
@@ -106,6 +107,8 @@ ENTRY(entry_SYSENTER_compat) xorl %r15d, %r15d /* nospec r15 */ cld + IBRS_ENTER + /* * SYSENTER doesn't filter flags, so we need to clear NT and AC * ourselves. To save a few cycles, we can check whether
@@ -253,6 +256,8 @@ GLOBAL(entry_SYSCALL_compat_after_hwframe) */ TRACE_IRQS_OFF + IBRS_ENTER + movq %rsp, %rdi call do_fast_syscall_32 /* XEN PV guests always use IRET path */
@@ -262,6 +267,9 @@ GLOBAL(entry_SYSCALL_compat_after_hwframe) /* Opportunistic SYSRET */ sysret32_from_system_call: TRACE_IRQS_ON /* User mode traces as IRQs on. */ + + IBRS_EXIT + movq RBX(%rsp), %rbx /* pt_regs->rbx */ movq RBP(%rsp), %rbp /* pt_regs->rbp */ movq EFLAGS(%rsp), %r11 /* pt_regs->flags (in r11) */
@@ -403,6 +411,7 @@ ENTRY(entry_INT80_compat) * gate turned them off. */ TRACE_IRQS_OFF + IBRS_ENTER movq %rsp, %rdi call do_int80_syscall_32
arch/x86/include/asm/cpu_device_id.h +161 -7
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arch/x86/include/asm/cpufeatures.h +14 -4
@@ -202,8 +202,8 @@#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9)/* AMD ProcFeedbackInterface */ #define X86_FEATURE_SME ( 7*32+10)/* AMD Secure Memory Encryption */ #define X86_FEATURE_PTI ( 7*32+11)/* Kernel Page Table Isolation enabled */ -#define X86_FEATURE_RETPOLINE ( 7*32+12)/* "" Generic Retpoline mitigation for Spectre variant 2 */ -#define X86_FEATURE_RETPOLINE_LFENCE ( 7*32+13)/* "" Use LFENCE for Spectre variant 2 */ +#define X86_FEATURE_KERNEL_IBRS ( 7*32+12)/* "" Set/clear IBRS on kernel entry/exit */ +#define X86_FEATURE_RSB_VMEXIT ( 7*32+13)/* "" Fill RSB on VM-Exit */ #define X86_FEATURE_INTEL_PPIN ( 7*32+14)/* Intel Processor Inventory Number */ #define X86_FEATURE_CDP_L2 ( 7*32+15)/* Code and Data Prioritization L2 */ #define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16)/* "" MSR SPEC_CTRL is implemented */
@@ -283,7 +283,15 @@#define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3)/* LLC Local MBM monitoring */ #define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4)/* "" LFENCE in user entry SWAPGS path */ #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5)/* "" LFENCE in kernel entry SWAPGS path */ -#define X86_FEATURE_RSB_VMEXIT_LITE (11*32+ 6)/* "" Fill RSB on VM exit when EIBRS is enabled */ +/* FREE! (11*32+ 6) */ +/* FREE! (11*32+ 7) */ +/* FREE! (11*32+ 8) */ +/* FREE! (11*32+ 9) */ +/* FREE! (11*32+10) */ +#define X86_FEATURE_RRSBA_CTRL (11*32+11)/* "" RET prediction control */ +#define X86_FEATURE_RETPOLINE (11*32+12)/* "" Generic Retpoline mitigation for Spectre variant 2 */ +#define X86_FEATURE_RETPOLINE_LFENCE (11*32+13)/* "" Use LFENCE for Spectre variant 2 */ +#define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17)/* "" Fill RSB on VM exit when EIBRS is enabled */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0)/* CLZERO instruction */
@@ -296,6 +304,7 @@#define X86_FEATURE_AMD_SSBD (13*32+24)/* "" Speculative Store Bypass Disable */ #define X86_FEATURE_VIRT_SSBD (13*32+25)/* Virtualized Speculative Store Bypass Disable */ #define X86_FEATURE_AMD_SSB_NO (13*32+26)/* "" Speculative Store Bypass is fixed in hardware. */ +#define X86_FEATURE_BTC_NO (13*32+29)/* "" Not vulnerable to Branch Type Confusion */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0)/* Digital Thermal Sensor */
@@ -397,6 +406,7 @@#define X86_BUG_SRBDS X86_BUG(24)/* CPU may leak RNG bits if not mitigated */ #define X86_BUG_MMIO_STALE_DATA X86_BUG(25)/* CPU is affected by Processor MMIO Stale Data vulnerabilities */ #define X86_BUG_MMIO_UNKNOWN X86_BUG(26)/* CPU is too old and its MMIO Stale Data status is unknown */ -#define X86_BUG_EIBRS_PBRSB X86_BUG(27)/* EIBRS is vulnerable to Post Barrier RSB Predictions */ +#define X86_BUG_RETBLEED X86_BUG(27)/* CPU is affected by RETBleed */ +#define X86_BUG_EIBRS_PBRSB X86_BUG(28)/* EIBRS is vulnerable to Post Barrier RSB Predictions */ #endif /* _ASM_X86_CPUFEATURES_H */
arch/x86/include/asm/intel-family.h +6 -0
@@ -13,6 +13,9 @@* that group keep the CPUID for the variants sorted by model number. */ +/* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */ +#define INTEL_FAM6_ANY X86_MODEL_ANY +#define INTEL_FAM6_CORE_YONAH 0x0E#define INTEL_FAM6_CORE2_MEROM 0x0F
@@ -101,6 +104,9 @@#define INTEL_FAM6_XEON_PHI_KNL 0x57/* Knights Landing */ #define INTEL_FAM6_XEON_PHI_KNM 0x85/* Knights Mill */ +/* Family 5 */ +#define INTEL_FAM5_QUARK_X1000 0x09/* Quark X1000 SoC */ +/* Useful macros */ #define INTEL_CPU_FAM_ANY (_family, _model, _driver_data) \ { \
arch/x86/include/asm/msr-index.h +10 -0
@@ -47,6 +47,8 @@#define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT)/* STIBP mask */ #define SPEC_CTRL_SSBD_SHIFT 2/* Speculative Store Bypass Disable bit */ #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT)/* Speculative Store Bypass Disable */ +#define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6/* Disable RRSBA behavior */ +#define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)#define MSR_IA32_PRED_CMD 0x00000049/* Prediction Command */ #define PRED_CMD_IBPB BIT(0)/* Indirect Branch Prediction Barrier */
@@ -73,6 +75,7 @@#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a#define ARCH_CAP_RDCL_NO BIT(0)/* Not susceptible to Meltdown */ #define ARCH_CAP_IBRS_ALL BIT(1)/* Enhanced IBRS support */ +#define ARCH_CAP_RSBA BIT(2)/* RET may use alternative branch predictors */ #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3)/* Skip L1D flush on vmentry */ #define ARCH_CAP_SSB_NO BIT(4)/* * Not susceptible to Speculative Store Bypass
@@ -120,6 +123,13 @@* bit available to control VERW * behavior. */ +#define ARCH_CAP_RRSBA BIT(19)/* +* Indicates RET may use predictors +* other than the RSB. With eIBRS +* enabled predictions in kernel mode +* are restricted to targets in +* kernel. +*/ #define ARCH_CAP_PBRSB_NO BIT(24)/* * Not susceptible to Post-Barrier * Return Stack Buffer Predictions.
arch/x86/include/asm/nospec-branch.h +24 -29
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arch/x86/kernel/cpu/amd.c +15 -6
@@ -885,12 +885,21 @@ static void init_amd_zn(struct cpuinfo_x86 *c) {set_cpu_cap (c,X86_FEATURE_ZEN ); -/* -* Fix erratum 1076: CPB feature bit not being set in CPUID. -* Always set it, except when running under a hypervisor. -*/ -if (!cpu_has (c,X86_FEATURE_HYPERVISOR ) && !cpu_has (c,X86_FEATURE_CPB )) -set_cpu_cap (c,X86_FEATURE_CPB ); +/* Fix up CPUID bits, but only if not virtualised. */ +if (!cpu_has (c,X86_FEATURE_HYPERVISOR )) { + +/* Erratum 1076: CPB feature bit not being set in CPUID. */ +if (!cpu_has (c,X86_FEATURE_CPB )) +set_cpu_cap (c,X86_FEATURE_CPB ); + +/* +* Zen3 (Fam19 model < 0x10) parts are not susceptible to +* Branch Type Confusion, but predate the allocation of the +* BTC_NO bit. +*/ +if (c->x86 ==0x19 && !cpu_has (c,X86_FEATURE_BTC_NO )) +set_cpu_cap (c,X86_FEATURE_BTC_NO ); + } }static void init_amd (struct cpuinfo_x86 *c)
arch/x86/kernel/cpu/bugs.c +293 -75
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arch/x86/kernel/cpu/common.c +36 -24
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arch/x86/kernel/cpu/match.c +40 -4
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arch/x86/kernel/cpu/scattered.c +1 -0
@@ -21,6 +21,7 @@ struct cpuid_bit {static const struct cpuid_bit cpuid_bits[] = { {X86_FEATURE_APERFMPERF ,CPUID_ECX ,0 ,0x00000006 ,0 }, {X86_FEATURE_EPB ,CPUID_ECX ,3 ,0x00000006 ,0 }, + {X86_FEATURE_RRSBA_CTRL ,CPUID_EDX ,2 ,0x00000007 ,2 }, {X86_FEATURE_CQM_LLC ,CPUID_EDX ,1 ,0x0000000f ,0 }, {X86_FEATURE_CQM_OCCUP_LLC ,CPUID_EDX ,0 ,0x0000000f ,1 }, {X86_FEATURE_CQM_MBM_TOTAL ,CPUID_EDX ,1 ,0x0000000f ,1 },
arch/x86/kernel/process.c +1 -1
@@ -434,7 +434,7 @@ static __always_inline void __speculation_ctrl_update(unsigned long tifp, }if (updmsr) -wrmsrl (MSR_IA32_SPEC_CTRL , msr); +write_spec_ctrl_current (msr, false); }static unsigned long speculation_ctrl_update_tif (struct task_struct *tsk)
arch/x86/kvm/svm.c +1 -0
@@ -50,6 +50,7 @@#include <asm/kvm_para.h> #include <asm/irq_remapping.h> #include <asm/spec-ctrl.h> +#include <asm/cpu_device_id.h> #include <asm/virtext.h> #include "trace.h"
arch/x86/kvm/vmx.c +46 -7
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arch/x86/kvm/x86.c +2 -2
@@ -9736,9 +9736,9 @@ void kvm_arch_end_assignment(struct kvm *kvm) }EXPORT_SYMBOL_GPL (kvm_arch_end_assignment); -bool kvm_arch_has_assigned_device (struct kvm *kvm) +bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm) { -return atomic_read (&kvm->arch.assigned_device_count); +return arch_atomic_read (&kvm->arch.assigned_device_count); }EXPORT_SYMBOL_GPL (kvm_arch_has_assigned_device);
drivers/base/cpu.c +8 -0
@@ -577,6 +577,12 @@ ssize_t __weak cpu_show_mmio_stale_data(struct device *dev,return sysfs_emit (buf,"Not affected\n" ); } +ssize_t __weak cpu_show_retbleed (struct device *dev, +struct device_attribute *attr,char *buf) +{ +return sysfs_emit (buf,"Not affected\n" ); +} + static DEVICE_ATTR(meltdown, 0444, cpu_show_meltdown, NULL); static DEVICE_ATTR(spectre_v1, 0444, cpu_show_spectre_v1, NULL); static DEVICE_ATTR(spectre_v2, 0444, cpu_show_spectre_v2, NULL);
@@ -587,6 +593,7 @@ static DEVICE_ATTR(tsx_async_abort, 0444, cpu_show_tsx_async_abort, NULL); static DEVICE_ATTR(itlb_multihit, 0444, cpu_show_itlb_multihit, NULL); static DEVICE_ATTR(srbds, 0444, cpu_show_srbds, NULL); static DEVICE_ATTR(mmio_stale_data, 0444, cpu_show_mmio_stale_data, NULL); +static DEVICE_ATTR(retbleed, 0444, cpu_show_retbleed, NULL);static struct attribute *cpu_root_vulnerabilities_attrs[] = { &dev_attr_meltdown.attr,
@@ -599,6 +606,7 @@ static struct attribute *cpu_root_vulnerabilities_attrs[] = { &dev_attr_itlb_multihit.attr, &dev_attr_srbds.attr, &dev_attr_mmio_stale_data.attr, + &dev_attr_retbleed.attr, NULL };
drivers/cpufreq/acpi-cpufreq.c +1 -0
@@ -47,6 +47,7 @@#include <asm/msr.h> #include <asm/processor.h> #include <asm/cpufeature.h> +#include <asm/cpu_device_id.h> MODULE_AUTHOR ("Paul Diefenbaugh, Dominik Brodowski" );MODULE_DESCRIPTION ("ACPI Processor P-States Driver" );
drivers/cpufreq/amd_freq_sensitivity.c +1 -0
@@ -21,6 +21,7 @@#include <asm/msr.h> #include <asm/cpufeature.h> +#include <asm/cpu_device_id.h> #include "cpufreq_ondemand.h"
drivers/idle/intel_idle.c +37 -6
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include/linux/cpu.h +2 -0
@@ -68,6 +68,8 @@ extern ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr,extern ssize_t cpu_show_mmio_stale_data (struct device *dev,struct device_attribute *attr,char *buf); +extern ssize_t cpu_show_retbleed (struct device *dev, +struct device_attribute *attr,char *buf); extern __printf(4, 5) struct device *cpu_device_create(struct device *parent, void *drvdata,
include/linux/kvm_host.h +1 -1
@@ -928,7 +928,7 @@ static inline void kvm_arch_end_assignment(struct kvm *kvm) { } -static inline bool kvm_arch_has_assigned_device (struct kvm *kvm) +static __always_inline bool kvm_arch_has_assigned_device(struct kvm *kvm) {return false; }
include/linux/mod_devicetable.h +1 -3
@@ -636,9 +636,7 @@ struct x86_cpu_id {__u16 steppings; }; -#define X86_FEATURE_MATCH (x) \ - { X86_VENDOR_ANY, X86_FAMILY_ANY, X86_MODEL_ANY, x } - +/* Wild cards for x86_cpu_id::vendor, family, model and feature */ #define X86_VENDOR_ANY 0xffff#define X86_FAMILY_ANY 0#define X86_MODEL_ANY 0
tools/arch/x86/include/asm/cpufeatures.h +1 -0
@@ -271,6 +271,7 @@/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (EDX), word 11 */ #define X86_FEATURE_CQM_LLC (11*32+ 1)/* LLC QoS if 1 */ +#define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17)/* "" Fill RSB on VM-Exit when EIBRS is enabled */ /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (EDX), word 12 */ #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0)/* LLC occupancy monitoring */
Greg Kroah-Hartman
maintainerI'm announcing the release of the 4.19.266 kernel.
All users of the 4.19 kernel series must upgrade.
The updated 4.19.y git tree can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git linux-4.19.y
and can be browsed at the normal kernel.org git web browser:
https://git.kernel.org/?p=linux/kernel/git/stable/linux-stable.git;a=summary
thanks,
greg k-h
------------
Documentation/admin-guide/kernel-parameters.txt | 13 Makefile | 2 arch/x86/entry/calling.h | 68 +++- arch/x86/entry/entry_32.S | 2 arch/x86/entry/entry_64.S | 34 +- arch/x86/entry/entry_64_compat.S | 11 arch/x86/include/asm/cpu_device_id.h | 168 ++++++++++ arch/x86/include/asm/cpufeatures.h | 18 - arch/x86/include/asm/intel-family.h | 6 arch/x86/include/asm/msr-index.h | 10 arch/x86/include/asm/nospec-branch.h | 53 +-- arch/x86/kernel/cpu/amd.c | 21 - arch/x86/kernel/cpu/bugs.c | 368 +++++++++++++++++++----- arch/x86/kernel/cpu/common.c | 60 ++- arch/x86/kernel/cpu/match.c | 44 ++ arch/x86/kernel/cpu/scattered.c | 1 arch/x86/kernel/process.c | 2 arch/x86/kvm/svm.c | 1 arch/x86/kvm/vmx.c | 53 +++ arch/x86/kvm/x86.c | 4 drivers/base/cpu.c | 8 drivers/cpufreq/acpi-cpufreq.c | 1 drivers/cpufreq/amd_freq_sensitivity.c | 1 drivers/idle/intel_idle.c | 43 ++ include/linux/cpu.h | 2 include/linux/kvm_host.h | 2 include/linux/mod_devicetable.h | 4 tools/arch/x86/include/asm/cpufeatures.h | 1 28 files changed, 814 insertions(+), 187 deletions(-)
Alexandre Chartre (2):
x86/bugs: Report AMD retbleed vulnerability
x86/bugs: Add AMD retbleed= boot parameter
Andrew Cooper (1):
x86/cpu/amd: Enumerate BTC_NO
Daniel Sneddon (1):
x86/speculation: Add RSB VM Exit protections
Greg Kroah-Hartman (1):
Linux 4.19.266
Ingo Molnar (1):
x86/cpufeature: Fix various quality problems in the <asm/cpu_device_hd.h> header
Josh Poimboeuf (8):
x86/speculation: Fix RSB filling with CONFIG_RETPOLINE=n x86/speculation: Fix firmware entry SPEC_CTRL handling x86/speculation: Fix SPEC_CTRL write on SMT state change x86/speculation: Use cached host SPEC_CTRL value for guest entry/exit x86/speculation: Remove x86_spec_ctrl_mask
KVM: VMX: Prevent guest RSB poisoning attacks with eIBRS
KVM: VMX: Fix IBRS handling after vmexit
x86/speculation: Fill RSB on vmexit for IBRS
Kan Liang (1):
x86/cpufeature: Add facility to check for min microcode revisions
Mark Gross (1):
x86/cpu: Add a steppings field to struct x86_cpu_id
Nathan Chancellor (1):
x86/speculation: Use DECLARE_PER_CPU for x86_spec_ctrl_current
Pawan Gupta (4):
x86/speculation: Add spectre_v2=ibrs option to support Kernel IBRS x86/bugs: Add Cannon lake to RETBleed affected CPU list x86/speculation: Disable RRSBA behavior
x86/bugs: Warn when "ibrs" mitigation is selected on Enhanced IBRS parts
Peter Zijlstra (10):
x86/cpufeatures: Move RETPOLINE flags to word 11
x86/bugs: Keep a per-CPU IA32_SPEC_CTRL value
x86/entry: Remove skip_r11rcx
x86/entry: Add kernel IBRS implementation
x86/bugs: Optimize SPEC_CTRL MSR writes
x86/bugs: Split spectre_v2_select_mitigation() and spectre_v2_user_select_mitigation() x86/bugs: Report Intel retbleed vulnerability
intel_idle: Disable IBRS during long idle
x86/speculation: Change FILL_RETURN_BUFFER to work with objtool x86/common: Stamp out the stepping madness
Suleiman Souhlal (2):
Revert "x86/speculation: Add RSB VM Exit protections" Revert "x86/cpu: Add a steppings field to struct x86_cpu_id"
Thomas Gleixner (2):
x86/devicetable: Move x86 specific macro out of generic code x86/cpu: Add consistent CPU match macros