Skip to contentSkip to conversation

Add the Harris QUAD100HD AMCC 405EP-based board.

PATCH New Gary Jennejohn 4 participants 5 messages Apr 23, 2008 – Apr 25, 2008

lore
Share & tools
lore

Gary Jennejohn

author
#0 lore raw

PATCH 2/2 Add the Harris QUAD100HD AMCC 405EP-based board.

Add the Harris QUAD100HD AMCC 405EP-based board.

Signed-off-by Gary Jennejohn <[email protected]>

---

board/quad100hd/nand.c new file +156 -0
new file mode 100644
index 0000000..964dd4b
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj at denx.de
+ *
+ * Based on board/icecube/ice_nand.c from PPCBoot (no copyright
+ * notice).
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#if defined(CONFIG_CMD_NAND)
+#include <ppc405.h>
+#include <asm/io.h>
+#include <nand.h>
+
+#define _BITMASK(i) (((unsigned)0x80000000) >> (i))
+
+#define GPIO_OUT	1
+#define GPIO_IN		2
+#define GPIO_GPIO	4
+#define GPIO_ALT	8
+
+typedef struct quad100hd_gpio_regs {
+	volatile u32 gpio_or;
+	volatile u32 gpio_tcr;
+	volatile u32 gpio_osrh;
+	volatile u32 gpio_osrl;
+	volatile u32 gpio_tsrh;
+	volatile u32 gpio_tsrl;
+	volatile u32 gpio_odr;
+	volatile u32 gpio_ir;
+	volatile u32 gpio_rr;
+	volatile u32 gpio_isrh;
+	volatile u32 gpio_isrl;
+} quad100hd_gpio_t;
+
+static struct quad100hd_gpio_regs *quad100hd_gpio = NULL;
+
+static void inline set_gpio_dr(volatile u32 *reg_adr, int gpio, int set)
+{
+	
+	if (gpio > 15) {
+		++reg_adr;   /* point to osrl */
+		gpio -= 16;
+	}
+	gpio <<= 1;
+	if (set) {
+		*reg_adr &= ~_BITMASK(gpio);
+		*reg_adr |=  _BITMASK(gpio + 1);
+	} else {
+		*reg_adr &= ~(_BITMASK(gpio) | _BITMASK(gpio + 1));
+	}
+}
+
+static void inline set_gpio(quad100hd_gpio_t * gpio, int gpio_pin, int func)
+{
+
+	gpio->gpio_odr &= ~_BITMASK(gpio_pin);
+	if (func & GPIO_OUT)
+		gpio->gpio_tcr |= _BITMASK(gpio_pin);
+	else
+		gpio->gpio_tcr &= ~_BITMASK(gpio_pin);
+	set_gpio_dr(&gpio->gpio_osrh, gpio_pin, func & GPIO_ALT);
+	set_gpio_dr(&gpio->gpio_tsrh, gpio_pin, 0);
+}
+
+static int quad100hd_init_nand_gpio(void)
+{
+	quad100hd_gpio = (struct quad100hd_gpio_regs *) GPIO_BASE;
+			
+	set_gpio(quad100hd_gpio, CFG_NAND_CS, GPIO_ALT | GPIO_OUT);
+	set_gpio(quad100hd_gpio, CFG_NAND_ALE, GPIO_GPIO | GPIO_OUT);
+	set_gpio(quad100hd_gpio, CFG_NAND_CLE, GPIO_GPIO | GPIO_OUT);
+	set_gpio(quad100hd_gpio, CFG_NAND_CE, GPIO_GPIO | GPIO_OUT);
+	set_gpio(quad100hd_gpio, CFG_NAND_RDY, GPIO_GPIO | GPIO_IN);
+	
+	return 0;
+}
+
+/* 
+ *	hardware specific access to control-lines
+ */
+static void quad100hd_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+	switch(cmd) {
+	case NAND_CTL_SETCLE:
+		quad100hd_gpio->gpio_or |= _BITMASK(CFG_NAND_CLE);
+		eieio();
+		break;
+	case NAND_CTL_CLRCLE:
+		quad100hd_gpio->gpio_or &= ~_BITMASK(CFG_NAND_CLE);
+		eieio();
+		break;
+
+	case NAND_CTL_SETALE:
+		quad100hd_gpio->gpio_or |= _BITMASK(CFG_NAND_ALE);
+		eieio();
+		break;
+	case NAND_CTL_CLRALE:
+		quad100hd_gpio->gpio_or &= ~_BITMASK(CFG_NAND_ALE);
+		eieio();
+		break;
+
+	case NAND_CTL_SETNCE:
+		quad100hd_gpio->gpio_or &= ~_BITMASK(CFG_NAND_CE);
+		eieio();
+		break;
+	case NAND_CTL_CLRNCE:
+		quad100hd_gpio->gpio_or |= _BITMASK(CFG_NAND_CE);
+		eieio();
+		break;
+	}
+}
+
+static int quad100hd_nand_ready(struct mtd_info *mtd)
+{
+	return (quad100hd_gpio->gpio_ir & _BITMASK(CFG_NAND_RDY) ? 1 : 0);
+}
+
+
+/*
+ * Main initialization routine
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+	quad100hd_init_nand_gpio();
+
+	/* Set address of hardware control function */
+	nand->hwcontrol = quad100hd_hwcontrol;
+	nand->dev_ready = quad100hd_nand_ready;
+	nand->eccmode = NAND_ECC_SOFT;
+	/* 15 us command delay time */
+	nand->chip_delay =  20;
+
+	/* Return happy */
+	return 0;
+}
+#endif /* CONFIG_CMD_NAND */
board/quad100hd/quad100hd.c new file +113 -0

113 lines not on this page · raw message

board/quad100hd/u-boot.lds new file +133 -0

133 lines not on this page · raw message

include/configs/quad100hd.h new file +306 -0

306 lines not on this page · raw message

Signature · 10 lines
1.5.5


---
Gary Jennejohn
*********************************************************************
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: [email protected]
*********************************************************************
#1 lore raw

PATCH 2/2 Add the Harris QUAD100HD AMCC 405EP-based board.

Quoted 1 line · Gary Jennejohn

Add the Harris QUAD100HD AMCC 405EP-based board.

Please find some comments below.

<snip>

Quoted 56 lines
Signed-off-by Gary Jennejohn <[email protected]>

---

board/quad100hd/nand.c new file +48 -0
new file mode 100644
index 0000000..964dd4b
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj at denx.de
+ *
+ * Based on board/icecube/ice_nand.c from PPCBoot (no copyright
+ * notice).
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#if defined(CONFIG_CMD_NAND)
+#include <ppc405.h>
+#include <asm/io.h>
+#include <nand.h>
+
+#define _BITMASK(i) (((unsigned)0x80000000) >> (i))
+
+#define GPIO_OUT	1
+#define GPIO_IN		2
+#define GPIO_GPIO	4
+#define GPIO_ALT	8
+
+typedef struct quad100hd_gpio_regs {
+	volatile u32 gpio_or;
+	volatile u32 gpio_tcr;
+	volatile u32 gpio_osrh;
+	volatile u32 gpio_osrl;
+	volatile u32 gpio_tsrh;
+	volatile u32 gpio_tsrl;
+	volatile u32 gpio_odr;

board/quad100hd/nand.c line 58

Quoted 10 lines
board/quad100hd/nand.c new file +10 -0
+	volatile u32 gpio_ir;
+	volatile u32 gpio_rr;
+	volatile u32 gpio_isrh;
+	volatile u32 gpio_isrl;
+} quad100hd_gpio_t;
+
+static struct quad100hd_gpio_regs *quad100hd_gpio = NULL;
+
+static void inline set_gpio_dr(volatile u32 *reg_adr, int gpio, int set)
+{

There is a function for this already available. Please take a look at gpio_write_bit() in cpu/ppc4xx/gpio.c.

board/quad100hd/nand.c line 66

Quoted 8 lines
board/quad100hd/nand.c new file +8 -0
+
+	if (gpio > 15) {
+		++reg_adr;   /* point to osrl */
+		gpio -= 16;
+	}
+	gpio <<= 1;
+	if (set) {
+		*reg_adr &= ~_BITMASK(gpio);

And don't access the GPIO registers via volatile pointers. Use the in/out_be32 () functions instead.

Quoted 8 lines
board/quad100hd/nand.c new file +7 -0
+		*reg_adr |=  _BITMASK(gpio + 1);
+	} else {
+		*reg_adr &= ~(_BITMASK(gpio) | _BITMASK(gpio + 1));
+	}
+}
+
+static void inline set_gpio(quad100hd_gpio_t * gpio, int gpio_pin, int

func) +{

This function is also already available: gpio_config(). Could be that this function needs some changes for 405EP since it has never been tested on this platform before.

Quoted 21 lines
board/quad100hd/nand.c new file +21 -0
+	gpio->gpio_odr &= ~_BITMASK(gpio_pin);
+	if (func & GPIO_OUT)
+		gpio->gpio_tcr |= _BITMASK(gpio_pin);
+	else
+		gpio->gpio_tcr &= ~_BITMASK(gpio_pin);
+	set_gpio_dr(&gpio->gpio_osrh, gpio_pin, func & GPIO_ALT);
+	set_gpio_dr(&gpio->gpio_tsrh, gpio_pin, 0);
+}
+
+static int quad100hd_init_nand_gpio(void)
+{
+	quad100hd_gpio = (struct quad100hd_gpio_regs *) GPIO_BASE;
+
+	set_gpio(quad100hd_gpio, CFG_NAND_CS, GPIO_ALT | GPIO_OUT);
+	set_gpio(quad100hd_gpio, CFG_NAND_ALE, GPIO_GPIO | GPIO_OUT);
+	set_gpio(quad100hd_gpio, CFG_NAND_CLE, GPIO_GPIO | GPIO_OUT);
+	set_gpio(quad100hd_gpio, CFG_NAND_CE, GPIO_GPIO | GPIO_OUT);
+	set_gpio(quad100hd_gpio, CFG_NAND_RDY, GPIO_GPIO | GPIO_IN);
+
+	return 0;
+}

board/quad100hd/nand.c line 106

Quoted 10 lines
board/quad100hd/nand.c new file +10 -0
+
+/*
+ *	hardware specific access to control-lines
+ */
+static void quad100hd_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+	switch(cmd) {
+	case NAND_CTL_SETCLE:
+		quad100hd_gpio->gpio_or |= _BITMASK(CFG_NAND_CLE);
+		eieio();

Please use this instead:

		gpio_write_bit(CFG_NAND_CLE, 1);

No need for the eieio() then.

board/quad100hd/nand.c line 110

Quoted 4 lines
board/quad100hd/nand.c new file +4 -0
+		break;
+	case NAND_CTL_CLRCLE:
+		quad100hd_gpio->gpio_or &= ~_BITMASK(CFG_NAND_CLE);
+		eieio();

		gpio_write_bit(CFG_NAND_CLE, 0);

board/quad100hd/nand.c line 115

Quoted 5 lines
board/quad100hd/nand.c new file +5 -0
+		break;
+
+	case NAND_CTL_SETALE:
+		quad100hd_gpio->gpio_or |= _BITMASK(CFG_NAND_ALE);
+		eieio();

here too...

Quoted 10 lines
board/quad100hd/nand.c new file +10 -0
+		break;
+	case NAND_CTL_CLRALE:
+		quad100hd_gpio->gpio_or &= ~_BITMASK(CFG_NAND_ALE);
+		eieio();
+		break;
+
+	case NAND_CTL_SETNCE:
+		quad100hd_gpio->gpio_or &= ~_BITMASK(CFG_NAND_CE);
+		eieio();
+		break;

board/quad100hd/nand.c line 135

Quoted 10 lines
board/quad100hd/nand.c new file +10 -0
+	case NAND_CTL_CLRNCE:
+		quad100hd_gpio->gpio_or |= _BITMASK(CFG_NAND_CE);
+		eieio();
+		break;
+	}
+}
+
+static int quad100hd_nand_ready(struct mtd_info *mtd)
+{
+	return (quad100hd_gpio->gpio_ir & _BITMASK(CFG_NAND_RDY) ? 1 : 0);

gpio_read_in_bit()

Quoted 68 lines
board/quad100hd/nand.c new file +21 -0
+}
+
+
+/*
+ * Main initialization routine
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+	quad100hd_init_nand_gpio();
+
+	/* Set address of hardware control function */
+	nand->hwcontrol = quad100hd_hwcontrol;
+	nand->dev_ready = quad100hd_nand_ready;
+	nand->eccmode = NAND_ECC_SOFT;
+	/* 15 us command delay time */
+	nand->chip_delay =  20;
+
+	/* Return happy */
+	return 0;
+}
+#endif /* CONFIG_CMD_NAND */
board/quad100hd/quad100hd.c new file +41 -0
new file mode 100644
index 0000000..fbe9274
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj at denx.de.
+ *
+ * Based in part on board/icecube/icecube.c from PPCBoot
+ * (C) Copyright 2003 Intrinsyc Software
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <environment.h>
+#include <logbuff.h>
+#include <post.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{

board/quad100hd/quad100hd.c line 51

Quoted 10 lines
board/quad100hd/quad100hd.c new file +10 -0
+	/* taken from ppcboot */
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(uicer, 0x00000000);	/* disable all ints */
+	mtdcr(uiccr, 0x00000000);
+	mtdcr(uicpr, 0xFFFF7FFE);	/* set int polarities */
+	mtdcr(uictr, 0x00000000);	/* set int trigger levels */
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+
+#define cpc0_srr (CNTRL_DCR_BASE+0x6)

Please don't put #defines in functions. And this is already defined:

CPC0_SRR.

Quoted 47 lines
board/quad100hd/quad100hd.c new file +47 -0
+    	mtdcr (cpc0_srr, 0x00040000);   /* Hold PCI bridge in reset */
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+#ifdef DISPLAY_BOARD_INFO
+	sys_info_t sysinfo;
+#endif
+
+	puts("Board: Quad100hd");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+#ifdef DISPLAY_BOARD_INFO
+	/* taken from ppcboot */
+	get_sys_info (&sysinfo);
+
+	printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz);
+	printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+	printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+	printf("\tEPB: %lu MHz\n", sysinfo.freqPLB / (sysinfo.pllExtBusDiv *
+		1000000));
+	printf ("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
+#endif
+
+	return (0);
+}
+
+/* taken from ppcboot */
+long int init_sdram_static_settings(void)
+{
+#define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
+	/* disable memcontroller so updates work */
+	mtsdram0( mem_mcopt1, 0x00A00000);
+	mtsdram0( mem_rtr   , 0x05f00000);
+	mtsdram0( mem_pmit  , 0x07C00000);

board/quad100hd/quad100hd.c line 108

Quoted 10 lines
board/quad100hd/quad100hd.c new file +10 -0
+	mtsdram0( mem_mb0cf , 0x00062001);
+	mtsdram0( mem_mb1cf , 0x00000000);
+	mtsdram0( mem_sdtr1 , 0x010b401a);
+	/* SDRAM have a power on delay,  500 micro should do */
+	udelay(500);
+	mtsdram0( mem_mcopt1, 0x00A00000|0x80000000);
+	udelay(500);
+
+	return (CFG_SDRAM_SIZE);
+}

Is this fixed SDRAM init really needed? Did you take a look at cpu/ppc4xx/sdram.c. This should handle your setup probably too. You need to define:

#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

in you board config file for it.

<snip>

Quoted 81 lines
include/configs/quad100hd.h new file +44 -0
new file mode 100644
index 0000000..6f84878
@@ -0,0 +1,306 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * quad100hd.h - configuration for Quad100hd board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_QUAD100HD	1		/* Board is Quad100hd	*/
+#define CONFIG_4xx		1		/* ... PPC4xx family	*/
+#define CONFIG_405EP		1		/* Specifc 405EP support*/
+
+#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
+
+#define PLLMR0_DEFAULT		PLLMR0_266_133_66 /* no PCI */
+#define PLLMR1_DEFAULT		PLLMR1_266_133_66 /* no PCI */
+
+#define CFG_ENV_IS_IN_EEPROM    1   /* use the EEPROM for environment vars

*/ +

include/configs/quad100hd.h new file +7 -0
+#define CONFIG_OVERWRITE_ETHADDR_ONCE	1
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_HAS_ETH1		1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0x01	/* PHY address			*/
+#define CFG_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers &

descriptors */ +#define CONFIG_PHY_RESET 1

include/configs/quad100hd.h new file +22 -0
+#define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_ASKENV
+#undef CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_LOG
+#undef CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#undef CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+

include/configs/quad100hd.h line 85

Quoted 10 lines
include/configs/quad100hd.h new file +10 -0
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*-----------------------------------------------------------------------
+ * SDRAM
+ *----------------------------------------------------------------------*/
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0  1
+#define CFG_SDRAM_SIZE      0x02000000      /* 32 MB */

So you are using the common SDRAM init code already. And some board specific code too. I'm not sure but it could be that you SDRAM is now initialized twice. Please double-check this.

Quoted 87 lines
include/configs/quad100hd.h new file +4 -0
+/* FIX! SDRAM timings used in datasheet */
+#define CFG_SDRAM_CL            3       /* CAS latency */
+#define CFG_SDRAM_tRP           20      /* PRECHARGE command period */
+#define CFG_SDRAM_tRC           66      /* ACTIVE-to-ACTIVE command period

*/ +#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */

include/configs/quad100hd.h new file +9 -0
+#define CFG_SDRAM_tRFC          66      /* Auto refresh period */ +
+/*
+ * JFFS2
+ */
+#define CFG_JFFS2_FIRST_BANK    0
+#ifdef  CFG_KERNEL_IN_JFFS2
+#define CFG_JFFS2_FIRST_SECTOR  0   /* JFFS starts at block 0 */
+#else /* kernel not in JFFS */
+#define CFG_JFFS2_FIRST_SECTOR  8   /* block 0-7 is kernel (1MB = 8

sectors) */ +#endif

include/configs/quad100hd.h new file +25 -0
+#define CFG_JFFS2_NUM_BANKS     1
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef	CFG_EXT_SERIAL_CLOCK			/* external serial clock */
+#define CFG_BASE_BAUD		691200
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /*

Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of
command args */

include/configs/quad100hd.h new file +17 -0
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
+#define CFG_EXTBDINFO		1	/* To use extended board_info (bd_t) */
+
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0

*/ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +

include/configs/quad100hd.h new file +27 -0
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50		/* base address */
+#define CFG_I2C_EEPROM_ADDR_LEN	2		/* bytes of address */
+
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 8 byte write page size */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CFG_EEPROM_SIZE			0x2000
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFC00000
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CFG_MONITOR_BASE	0xFFF80000
+
+/*

include/configs/quad100hd.h line 184

Quoted 10 lines
include/configs/quad100hd.h new file +10 -0
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI			/* The flash is CFI compatible	*/

You are using the CFI driver *and* a board specific driver too. Why is this ?

Quoted 39 lines
include/configs/quad100hd.h new file +13 -0
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+#define CFG_FLASH_WORD_SIZE	unsigned short
+#define CFG_FLASH_ADDR0		0x0555
+#define CFG_FLASH_ADDR1		0x02aa
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)

*/ +#define CFG_FLASH_INCREMENT 0 /* there is only one bank
*/ +

include/configs/quad100hd.h new file +24 -0
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
+#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET		0x00050000 /* Offset of Environment Sector  */
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#endif
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE		0x400		/* Size of Environment vars */
+#define CFG_ENV_OFFSET		0x00000000
+#define CFG_ENABLE_CRC_16	1       /* Intrinsyc formatting used crc16 */
+#endif
+
+/* from PPCBoot */
+/* NAND */
+#define CONFIG_NAND
+#ifdef CONFIG_NAND
+#define CFG_NAND_BASE   0x60000000
+#define SECTORSIZE	512
+#define ADDR_COLUMN	1
+#define ADDR_PAGE	2

include/configs/quad100hd.h line 234

Quoted 10 lines
include/configs/quad100hd.h new file +10 -0
+#define NAND_MAX_FLOORS	1
+#define NAND_MAX_CHIPS	1
+#define CFG_NAND_CS	10   /* our CS is GPIO10 */
+#define CFG_NAND_RDY	23   /* our RDY is GPIO23 */
+#define CFG_NAND_CE	24   /* our CE is GPIO24  */
+#define CFG_NAND_CLE	31   /* our CLE is GPIO31 */
+#define CFG_NAND_ALE	30   /* our ALE is GPIO30 */
+#define CFG_MAX_NAND_DEVICE	1
+#define ADDR_COLUMN_PAGE	3
+#define NAND_ChipID_UNKNOWN	0x00

Some of those defines are not needed anymore. I suspect that the following defines can be removed:

include/configs/quad100hd.h line 234

Quoted 7 lines
include/configs/quad100hd.h new file +7 -0
+#define SECTORSIZE	512
+#define ADDR_COLUMN	1
+#define ADDR_PAGE	2
+#define NAND_MAX_FLOORS	1
+#define NAND_MAX_CHIPS	1
+#define ADDR_COLUMN_PAGE	3
+#define NAND_ChipID_UNKNOWN	0x00

Please check if they are needed and remove them if not needed.

Quoted 55 lines
include/configs/quad100hd.h new file +16 -0
+#endif
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+/* see ./cpu/ppc4xx/start.S */
+#define CFG_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of OCM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data

*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)

include/configs/quad100hd.h new file +38 -0
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ * Taken from PPCBoot board/icecube/icecube.h
+ */
+
+/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
+#define CFG_EBC_PB0AP		0x04002480
+/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
+#define CFG_EBC_PB0CR		0xFFC5A000
+#define CFG_EBC_PB1AP           0x04005480
+#define CFG_EBC_PB1CR           0x60018000
+#define CFG_EBC_PB2AP           0x00000000
+#define CFG_EBC_PB2CR           0x00000000
+#define CFG_EBC_PB3AP           0x00000000
+#define CFG_EBC_PB3CR           0x00000000
+#define CFG_EBC_PB4AP           0x00000000
+#define CFG_EBC_PB4CR           0x00000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * Taken from PPCBoot board/icecube/icecube.h
+ */
+/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
+#define CFG_GPIO0_OSRH		0x55555550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+#define CFG_GPIO0_ISR1L		0x15555445
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xFFFF8014
+#define CFG_GPIO0_ODR		0x00000000
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */

include/configs/quad100hd.h line 299

Quoted 10 lines
include/configs/quad100hd.h new file +10 -0
+#endif
+
+/* ENVIRONMENT VARS */
+
+#define CONFIG_IPADDR		192.168.1.67
+#define CONFIG_SERVERIP		192.168.1.50
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_ETHADDR 		00:01:02:03:04:05
+#define CONFIG_ETH1ADDR		00:01:02:03:04:06

Are you really sure that you want to provide default MAC-addresses? We usually don't do this.

include/configs/quad100hd.h line 306

Quoted 7 lines
include/configs/quad100hd.h new file +7 -0
+#define CONFIG_LOADADDR		300000
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+
+#endif	/* __CONFIG_H */

Please fix the issues and resumbit.

Thanks.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================

author
#2 lore raw

PATCH 2/2 Add the Harris QUAD100HD AMCC 405EP-based board.

Quoted 10 lines · On Thu, 24 Apr 2008 08:27:20 +0200 Stefan Roese <[email protected]> wrote:

include/configs/quad100hd.h line 299

Quoted 6 lines
include/configs/quad100hd.h new file +6 -0
+#define CONFIG_IPADDR		192.168.1.67
+#define CONFIG_SERVERIP		192.168.1.50
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_ETHADDR 		00:01:02:03:04:05
+#define CONFIG_ETH1ADDR		00:01:02:03:04:06

Are you really sure that you want to provide default MAC-addresses? We usually don't do this.

The customer had CONFIG_ETHADDR set in PPCBoot. I added CONFIG_ETH1ADDR analog to that, since I have CONFIG_NET_MULTI defined in quad100hd.h.

I personally don't care either way and have no problem with removing them. Don't know what the customer would have to say about that.

---
Gary Jennejohn
*********************************************************************
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
*********************************************************************

#3 lore raw

PATCH 2/2 Add the Harris QUAD100HD AMCC 405EP-based board.

Hi Gary,

Quoted 14 lines
Quoted 10 lines · On Thu, 24 Apr 2008 08:27:20 +0200 Stefan Roese <[email protected]> wrote:

include/configs/quad100hd.h line 299

Quoted 6 lines
include/configs/quad100hd.h new file +6 -0
+#define CONFIG_IPADDR		192.168.1.67
+#define CONFIG_SERVERIP		192.168.1.50
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_ETHADDR 		00:01:02:03:04:05
+#define CONFIG_ETH1ADDR		00:01:02:03:04:06

Are you really sure that you want to provide default MAC-addresses? We usually don't do this.

Quoted 5 lines

The customer had CONFIG_ETHADDR set in PPCBoot. I added CONFIG_ETH1ADDR analog to that, since I have CONFIG_NET_MULTI defined in quad100hd.h.

I personally don't care either way and have no problem with removing them. Don't know what the customer would have to say about that.

Mac addresses (not that those are worth of that title) should not go into stock U-Boot source. This only calls for lots of trouble as discussed n+1 times. The customer will have to assign correct addresses anyway, so there is no reason to set a bad example in source others will copy from.

Cheers
Detlev

Signature · 7 lines
A GNU manual  should give a  good introduction to a beginner reading
through from the start, and should also provide all the details that
hackers want.                       --- GNU Coding Standards
--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu at denx.de
#4 lore raw

PATCH 2/2 Add the Harris QUAD100HD AMCC 405EP-based board.

In reply to Gary Jennejohn

Hello Gary,

Quoted 11 lines · in message <[email protected]> you wrote:
Quoted 10 lines

include/configs/quad100hd.h line 299

Quoted 7 lines
include/configs/quad100hd.h new file +6 -0
+#define CONFIG_IPADDR		192.168.1.67
+#define CONFIG_SERVERIP		192.168.1.50
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_ETHADDR 		00:01:02:03:04:05
+#define CONFIG_ETH1ADDR		00:01:02:03:04:06

Are you really sure that you want to provide default MAC-addresses? We usually don't do this.

Quoted 5 lines

The customer had CONFIG_ETHADDR set in PPCBoot. I added CONFIG_ETH1ADDR analog to that, since I have CONFIG_NET_MULTI defined in quad100hd.h.

I personally don't care either way and have no problem with removing them. Don't know what the customer would have to say about that.

Please remove this stuff from the board conig file. It has no place there. Not to mention that the used MAC addresses are owned by the 3Com corporation, and we have no permission to use these.

Best regards,

Wolfgang Denk

Signature · 5 lines
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"There are some good people in it, but the orchestra as  a  whole  is
equivalent to a gang bent on destruction."      - John Cage, composer