aic7xxx: debloat

@@ -147,6 +147,8 @@
 
 %token T_ACCESS_MODE
 
+%token T_DONT_GENERATE_DEBUG_CODE
+
 %token T_MODES
 
 %token T_DEFINE

@@ -357,6 +359,7 @@
 |	size
 |	count
 |	access_mode
+|	dont_generate_debug_code
 |	modes
 |	field_defn
 |	enum_defn

@@ -407,6 +410,13 @@
 	T_ACCESS_MODE T_MODE
 	{
 		cur_symbol->info.rinfo->mode = $2;
+	}
+;
+
+dont_generate_debug_code:
+	T_DONT_GENERATE_DEBUG_CODE
+	{
+		cur_symbol->dont_generate_debug_code = 1;
 	}
 ;
 

@@ -164,6 +164,7 @@
 address			{ return T_ADDRESS; }
 count			{ return T_COUNT; }
 access_mode		{ return T_ACCESS_MODE; }
+dont_generate_debug_code { return T_DONT_GENERATE_DEBUG_CODE; }
 modes			{ return T_MODES; }
 RW|RO|WO		{
 				 if (strcmp(yytext, "RW") == 0)

@@ -80,6 +80,17 @@
 	}
 
 /*
+ * Registers marked "dont_generate_debug_code" are not (yet) referenced
+ * from the driver code, and this keyword inhibit generation
+ * of debug code for them.
+ *
+ * REG_PRETTY_PRINT config will complain if dont_generate_debug_code
+ * is added to the register which is referenced in the driver.
+ * Unreferenced register with no dont_generate_debug_code will result
+ * in dead code. No warning is issued.
+ */
+
+/*
  * Mode Pointer
  * Controls which of the 5, 512byte, address spaces should be used
  * as the source and destination of any register accesses in our

@@ -91,6 +102,7 @@
 	field	DST_MODE	0x70
 	field	SRC_MODE	0x07
 	mode_pointer
+	dont_generate_debug_code
 }
 
 const SRC_MODE_SHIFT	0

@@ -190,6 +202,7 @@
 		SAW_HWERR,
 		BAD_SCB_STATUS
 	}
+	dont_generate_debug_code
 }
 
 /*

@@ -207,6 +220,7 @@
 	field	CLRSEQINT	0x04
 	field	CLRCMDINT	0x02
 	field	CLRSPLTINT	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -222,6 +236,7 @@
 	field	SQPARERR	0x08
 	field	ILLOPCODE	0x04
 	field	DSCTMOUT	0x02
+	dont_generate_debug_code
 }
 
 /*

@@ -255,6 +270,7 @@
 	field	INTEN		0x02
 	field	CHIPRST		0x01
 	field	CHIPRSTACK	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -265,6 +281,7 @@
 	access_mode	RW
 	size		2
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -274,6 +291,7 @@
 	address			0x008
 	access_mode	RW
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -311,6 +329,7 @@
 	field	CLRSEQ_SCSIINT	0x04
 	field	CLRSEQ_PCIINT	0x02
 	field	CLRSEQ_SPLTINT	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -320,6 +339,7 @@
 	address			0x00E
 	access_mode	RW
 	size		2
+	dont_generate_debug_code
 }
 
 /*

@@ -330,6 +350,7 @@
 	access_mode	RW
 	size		2
 	modes		M_CCHAN
+	dont_generate_debug_code
 }
 
 /*

@@ -340,6 +361,7 @@
 	count		2
 	access_mode	RW
 	modes		M_CCHAN
+	dont_generate_debug_code
 }
 
 /*

@@ -350,6 +372,7 @@
 	access_mode	RW
 	modes		M_CCHAN
 	size		2
+	dont_generate_debug_code
 }
 
 /*

@@ -378,6 +401,7 @@
 		SCB_QSIZE_8192,
 		SCB_QSIZE_16384
 	}
+	dont_generate_debug_code
 }
 
 /*

@@ -431,6 +455,7 @@
 	field	EXTREQLCK	0x10	/* External Request Lock */
 	field	DISABLE_TWATE	0x02	/* Rev B or greater */
 	field	CIOPARCKEN	0x01	/* Internal bus parity error enable */
+	dont_generate_debug_code
 }
 
 /*

@@ -459,6 +484,7 @@
 	field	SG_ADDR_MASK	0xf8
 	field	ODD_SEG		0x04
 	field	LAST_SEG	0x02
+	dont_generate_debug_code
 }
 
 register SG_CACHE_SHADOW {

@@ -469,6 +495,7 @@
 	field	ODD_SEG		0x04
 	field	LAST_SEG	0x02
 	field	LAST_SEG_DONE	0x01
+/*YAY*/
 }
 
 /*

@@ -491,6 +518,7 @@
 	access_mode	RW
 	size		8
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -522,6 +550,7 @@
 	access_mode	RW
 	size		3
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -551,6 +580,7 @@
 	access_mode	RW
 	size		8
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -561,6 +591,7 @@
 	access_mode	RW
 	size		8
 	modes		M_CCHAN
+	dont_generate_debug_code
 }
 
 /*

@@ -570,6 +601,7 @@
 	address			0x084
 	access_mode	RW
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -579,6 +611,7 @@
 	address			0x084
 	access_mode	RW
 	modes		M_CCHAN
+	dont_generate_debug_code
 }
 
 /*

@@ -609,6 +642,7 @@
 		RD_DFTHRSH_90,
 		RD_DFTHRSH_MAX
 	}
+	dont_generate_debug_code
 }
 
 /*

@@ -817,6 +851,7 @@
 	field	SRSPDPEEN	0x04
 	field	TSCSERREN	0x02
 	field	CMPABCDIS	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -863,6 +898,7 @@
 	field	RXOVRUN		0x04
 	field	RXSCEMSG	0x02
 	field	RXSPLTRSP	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -908,6 +944,7 @@
 	modes		M_DFF0, M_DFF1
 	count		2
 	field	RXDATABUCKET	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1069,6 +1106,7 @@
 	field	RXOVRUN		0x04
 	field	RXSCEMSG	0x02
 	field	RXSPLTRSP	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1080,6 +1118,7 @@
 	modes		M_DFF0, M_DFF1
 	count		2
 	field	RXDATABUCKET	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1091,6 +1130,7 @@
 	modes		M_CFG
 	field	TEST_GROUP	0xF0
 	field	TEST_NUM	0x0F
+	dont_generate_debug_code
 }
 
 /*

@@ -1109,6 +1149,7 @@
 	field	RDPERR		0x04
 	field	TWATERR		0x02
 	field	DPR		0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1204,6 +1245,7 @@
 	field	SSE		0x40
 	field	STA		0x08
 	field	TWATERR		0x02
+	dont_generate_debug_code
 }
 
 /*

@@ -1216,6 +1258,7 @@
 	size		20
 	count		2
 	modes		M_DFF0, M_DFF1, M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -1247,6 +1290,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -1278,6 +1322,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -1290,6 +1335,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -1302,6 +1348,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -1313,6 +1360,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -1324,6 +1372,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -1347,6 +1396,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -1358,6 +1408,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -1398,6 +1449,7 @@
 	count		2
 	mask		ILUNLEN	0x0F
 	mask		TLUNLEN	0xF0
+	dont_generate_debug_code
 }
 const LUNLEN_SINGLE_LEVEL_LUN 0xF
 

@@ -1410,6 +1462,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -1422,6 +1475,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		9
+	dont_generate_debug_code
 }
 
 /*

@@ -1432,6 +1486,7 @@
 	address			0x033
 	access_mode	RW
 	modes		M_CFG
+	dont_generate_debug_code
 }
 
 /*

@@ -1490,6 +1545,7 @@
 	field	PCI2PCI		0x04
 	field	SINGLECMD	0x02
 	field	ABORTPENDING	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1508,6 +1564,7 @@
 	field	LQOCONTINUE	0x04
 	field	LQOTOIDLE	0x02
 	field	LQOPAUSE	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1578,6 +1635,7 @@
 	field	DFPEXP		0x40
 	field	BIOSCANCELEN	0x10
 	field	SPIOEN		0x08
+	dont_generate_debug_code
 }
 
 /*

@@ -1594,6 +1652,7 @@
 	field	ENSTIMER	0x04
 	field	ACTNEGEN	0x02
 	field	STPWEN		0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1696,6 +1755,7 @@
 		P_STATUS	CDO|IOO,
 		P_MESGIN	CDO|IOO|MSGO
 	}
+	dont_generate_debug_code
 }
 
 /*

@@ -1738,6 +1798,7 @@
 	modes		M_CFG
 	size		2
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -1774,6 +1835,7 @@
 	access_mode	RW
 	modes		M_DFF0, M_DFF1, M_SCSI
 	size		2
+	dont_generate_debug_code
 }
 
 /*

@@ -1796,6 +1858,7 @@
 	count		2
 	field	CLKOUT		0x80
 	field	TARGID		0x0F
+	dont_generate_debug_code
 }
 
 /*

@@ -1825,6 +1888,7 @@
 	field	ENAB40		0x08	/* LVD transceiver active */
 	field	ENAB20		0x04	/* SE/HVD transceiver active */
 	field	SELWIDE		0x02
+	dont_generate_debug_code
 }
 
 /*

@@ -1842,6 +1906,7 @@
 	field	ENDGFORMCHK		0x04
 	field	AUTO_MSGOUT_DE		0x02
 	mask	OPTIONMODE_DEFAULTS	AUTO_MSGOUT_DE
+	dont_generate_debug_code
 }
 
 /*

@@ -1876,6 +1941,7 @@
 	field	CLROVERRUN	0x04
 	field	CLRSPIORDY	0x02
 	field	CLRARBDO	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1929,6 +1995,7 @@
 	field	CLRSCSIPERR	0x04
 	field	CLRSTRB2FAST	0x02
 	field	CLRREQINIT	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1962,6 +2029,7 @@
 	field	CLRWIDE_RES	0x04	/* Modes 0 and 1 only */
 	field	CLRSDONE	0x02	/* Modes 0 and 1 only */
 	field	CLRDMADONE	0x01	/* Modes 0 and 1 only */
+	dont_generate_debug_code
 }
 
 /*

@@ -2002,6 +2070,7 @@
 	access_mode	RO
 	modes		M_CFG
 	count		6
+	dont_generate_debug_code
 }
 
 /*

@@ -2022,6 +2091,7 @@
 	access_mode	RO
 	modes		M_CFG
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -2054,6 +2124,7 @@
 	field	CLRLQIBADLQT	0x04
 	field	CLRLQIATNLQ	0x02
 	field	CLRLQIATNCMD	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2070,6 +2141,7 @@
 	field	ENLQIBADLQT	0x04
 	field	ENLQIATNLQ	0x02
 	field	ENLQIATNCMD	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2106,6 +2178,7 @@
 	field	CLRLQIBADLQI	0x04
 	field	CLRLQIOVERI_LQ	0x02
 	field	CLRLQIOVERI_NLQ	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2124,6 +2197,7 @@
 	field	ENLQIBADLQI	0x04
 	field	ENLQIOVERI_LQ	0x02	/* LQIOVERI1 */
 	field	ENLQIOVERI_NLQ	0x01	/* LQIOVERI2 */
+	dont_generate_debug_code
 }
 
 /*

@@ -2165,6 +2239,7 @@
 	count		3
 	field	CLRNTRAMPERR	0x02
 	field	CLROSRAMPERR	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2177,6 +2252,7 @@
 	count		4
 	field	ENNTRAMPERR	0x02
 	field	ENOSRAMPERR	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2207,6 +2283,7 @@
 	field	CLRLQOATNLQ		0x04
 	field	CLRLQOATNPKT		0x02
 	field	CLRLQOTCRC		0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2222,6 +2299,7 @@
 	field	ENLQOATNLQ		0x04
 	field	ENLQOATNPKT		0x02
 	field	ENLQOTCRC		0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2251,6 +2329,7 @@
 	field	CLRLQOBADQAS		0x04
 	field	CLRLQOBUSFREE		0x02
 	field	CLRLQOPHACHGINPKT	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2266,6 +2345,7 @@
 	field	ENLQOBADQAS		0x04
 	field	ENLQOBUSFREE		0x02
 	field	ENLQOPHACHGINPKT	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2289,6 +2369,7 @@
 	access_mode	RO
 	modes		M_CFG
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -2318,6 +2399,7 @@
 	access_mode	RO
 	size		2
 	modes		M_DFF0, M_DFF1, M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -2341,6 +2423,7 @@
 	access_mode	RW
 	size		2
 	modes		M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -2357,6 +2440,7 @@
 	field		LQOBUSETDLY	0x40
 	field		LQONOHOLDLACK	0x02
 	field		LQONOCHKOVER	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2389,6 +2473,7 @@
 	field	CLRCFG4TSTAT	0x04
 	field	CLRCFG4ICMD	0x02
 	field	CLRCFG4TCMD	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2415,6 +2500,7 @@
 	access_mode	RW
 	size		2
 	modes		M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -2472,6 +2558,7 @@
 	access_mode	RW
 	size		2
 	modes		M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -2494,6 +2581,7 @@
 	access_mode	RO
 	size		8
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -2513,6 +2601,7 @@
 	address			0x060
 	access_mode	RW
 	modes		M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -2523,6 +2612,7 @@
 	access_mode	RW
 	modes		M_SCSI
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -2543,6 +2633,7 @@
 	access_mode	RW
 	modes		M_SCSI
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -2557,6 +2648,7 @@
 	field	PPROPT_QAS	0x04
 	field	PPROPT_DT	0x02
 	field	PPROPT_IUT	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2573,6 +2665,7 @@
 	field	ENAUTOATNI	0x04
 	field	ENAUTOATNO	0x02
 	field	WIDEXFER	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2583,6 +2676,7 @@
 	access_mode	RW
 	modes		M_SCSI
 	count		7
+	dont_generate_debug_code
 }
 
 /*

@@ -2602,6 +2696,7 @@
 	field	DFFACTCLR	0x04
 	field	SHVALIDSTDIS	0x02
 	field	LSTSGCLRDIS	0x01
+	dont_generate_debug_code
 }
 
 const AHD_ANNEXCOL_PER_DEV0	4

@@ -2635,6 +2730,7 @@
 	access_mode	RW
 	modes		M_SCSI
 	count		3
+	dont_generate_debug_code
 }
 
 /*

@@ -2645,6 +2741,7 @@
 	address			0x067
 	access_mode	RW
 	modes		M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -2671,6 +2768,7 @@
 	access_mode	RW
 	modes		M_SCSI
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -2702,6 +2800,7 @@
 	access_mode	RW
 	size		3
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -2789,6 +2888,7 @@
 	access_mode	RW
 	size		2
 	modes		M_DFF0, M_DFF1, M_CCHAN, M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -2816,6 +2916,7 @@
 	field	AUSCBPTR_EN	0x80
 	field	SCBPTR_ADDR	0x38
 	field	SCBPTR_OFF	0x07
+	dont_generate_debug_code
 }
 
 /*

@@ -2825,6 +2926,7 @@
 	address			0x0AC
 	access_mode	RW
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -2834,6 +2936,7 @@
 	address			0x0AC
 	access_mode	RW
 	modes		M_CCHAN
+	dont_generate_debug_code
 }
 
 /*

@@ -2875,6 +2978,7 @@
 	field	CCSCBEN		0x08
 	field	CCSCBDIR	0x04
 	field	CCSCBRESET	0x01
+/*YAY*/
 }
 
 /*

@@ -2899,6 +3003,7 @@
 	address			0x0B0
 	access_mode	RW
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -2908,6 +3013,7 @@
 	address			0x0B0
 	access_mode	RW
 	modes		M_CCHAN
+	dont_generate_debug_code
 }
 
 /*

@@ -2958,6 +3064,7 @@
 	access_mode	RW
 	modes		M_SCSI
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -2974,6 +3081,7 @@
 	field	BRDEN		0x04
 	field	BRDRW		0x02
 	field	BRDSTB		0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2984,6 +3092,7 @@
 	access_mode	RW
 	modes		M_SCSI
 	count		4
+	dont_generate_debug_code
 }
 
 /*

@@ -2995,6 +3104,7 @@
 	size		2
 	modes		M_SCSI
 	count		4
+	dont_generate_debug_code
 }
 
 /*

@@ -3011,6 +3121,7 @@
 	field	SEEARBACK	0x04
 	field	SEEBUSY		0x02
 	field	SEESTART	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -3036,6 +3147,7 @@
 	mask	SEEOP_EWDS	0x40
 	field	SEERST		0x02
 	field	SEESTART	0x01
+	dont_generate_debug_code
 }
 
 const SEEOP_ERAL_ADDR	0x80

@@ -3050,6 +3162,7 @@
 	address			0x0BF
 	access_mode	RW
 	modes		M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -3061,6 +3174,7 @@
 	access_mode	RW
 	size		2
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -3087,6 +3201,7 @@
 	field	DESQDIS		0x10
 	field	RCVROFFSTDIS	0x04
 	field	XMITOFFSTDIS	0x02
+	dont_generate_debug_code
 }
 
 /*

@@ -3132,6 +3247,7 @@
 	address			0x0C4
 	access_mode	RW
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -3144,6 +3260,7 @@
 	count		1
 	field	AUTOINCEN	0x80
 	field	DSPSEL		0x1F
+	dont_generate_debug_code
 }
 
 const NUMDSPS 0x14

@@ -3158,6 +3275,7 @@
 	count		3
 	field	AUTOXBCDIS	0x80
 	field	XMITMANVAL	0x3F
+	dont_generate_debug_code
 }
 
 /*

@@ -3316,6 +3434,7 @@
 	count		23
 	field	ZERO		0x02
 	field	CARRY		0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -3344,6 +3463,7 @@
 	address			0x0DA
 	access_mode 	RW
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -3355,6 +3475,7 @@
 	access_mode	RW
 	size		2
 	count		5
+	dont_generate_debug_code
 }
 
 /*

@@ -3364,6 +3485,7 @@
 	address			0x0E0
 	access_mode 	RW
 	accumulator
+	dont_generate_debug_code
 }
 
 /*

@@ -3380,6 +3502,7 @@
 	access_mode	RW
 	size		2
 	sindex
+	dont_generate_debug_code
 }
 
 /*

@@ -3390,6 +3513,7 @@
 	address			0x0E4
 	access_mode	RW
 	size		2
+	dont_generate_debug_code
 }
 
 /*

@@ -3415,6 +3539,7 @@
 	address			0x0E8
 	access_mode RO
 	allones
+	dont_generate_debug_code
 }
 
 /*

@@ -3425,6 +3550,7 @@
 	address			0x0EA
 	access_mode RO
 	allzeros
+	dont_generate_debug_code
 }
 
 /*

@@ -3435,6 +3561,7 @@
 	address			0x0EA
 	access_mode WO
 	none
+	dont_generate_debug_code
 }
 
 /*

@@ -3445,6 +3572,7 @@
 register SINDIR	{
 	address			0x0EC
 	access_mode RO
+	dont_generate_debug_code
 }
 
 /*

@@ -3455,6 +3583,7 @@
 register DINDIR	 {
 	address			0x0ED
 	access_mode WO
+	dont_generate_debug_code
 }
 
 /*

@@ -3479,6 +3608,7 @@
 register STACK {
 	address			0x0F2
 	access_mode RW
+	dont_generate_debug_code
 }
 
 /*

@@ -3491,6 +3621,7 @@
 	size		2
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -3503,6 +3634,7 @@
 	size		2
 	modes		M_SCSI
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -3515,6 +3647,7 @@
 	size		2
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -3543,12 +3676,14 @@
 	modes	0, 1, 2, 3
 	REG0 {
 		size		2
+		dont_generate_debug_code
 	}
 	REG1 {
 		size		2
 	}
 	REG_ISR {
 		size		2
+		dont_generate_debug_code
 	}
 	SG_STATE {
 		size		1

@@ -3572,9 +3707,11 @@
 	modes	0, 1, 2, 3
 	LONGJMP_ADDR {
 		size		2
+		dont_generate_debug_code
 	}
 	ACCUM_SAVE {
 		size		1
+		dont_generate_debug_code
 	}
 }
 

@@ -3591,18 +3728,22 @@
 	 */
 	WAITING_SCB_TAILS {
 		size		32
+		dont_generate_debug_code
 	}
 	WAITING_TID_HEAD {
 		size		2
+		dont_generate_debug_code
 	}
 	WAITING_TID_TAIL {
 		size		2
+		dont_generate_debug_code
 	}
 	/*
 	 * SCBID of the next SCB in the new SCB queue.
 	 */
 	NEXT_QUEUED_SCB_ADDR {
 		size		4
+		dont_generate_debug_code
 	}
 	/*
 	 * head of list of SCBs that have

@@ -3611,6 +3752,7 @@
 	 */
 	COMPLETE_SCB_HEAD {
 		size		2
+		dont_generate_debug_code
 	}
 	/*
 	 * The list of completed SCBs in

@@ -3618,6 +3760,7 @@
 	 */
 	COMPLETE_SCB_DMAINPROG_HEAD {
 		size		2
+		dont_generate_debug_code
 	}
 	/*
 	 * head of list of SCBs that have

@@ -3626,6 +3769,7 @@
 	 */
 	COMPLETE_DMA_SCB_HEAD {
 		size		2
+		dont_generate_debug_code
 	}
 	/*
 	 * tail of list of SCBs that have

@@ -3634,6 +3778,7 @@
 	 */
 	COMPLETE_DMA_SCB_TAIL {
 		size		2
+		dont_generate_debug_code
 	}
 	/*
 	 * head of list of SCBs that have

@@ -3643,6 +3788,7 @@
 	 */
 	COMPLETE_ON_QFREEZE_HEAD {
 		size		2
+		dont_generate_debug_code
 	}
 	/*
 	 * Counting semaphore to prevent new select-outs

@@ -3667,6 +3813,7 @@
 	 */
 	MSG_OUT {
 		size		1
+		dont_generate_debug_code
 	}
 	/* Parameters for DMA Logic */
 	DMAPARAMS {

@@ -3682,6 +3829,7 @@
 		field	DIRECTION	0x04	/* Set indicates PCI->SCSI */
 		field	FIFOFLUSH	0x02
 		field	FIFORESET	0x01
+		dont_generate_debug_code
 	}
 	SEQ_FLAGS {
 		size		1

@@ -3703,9 +3851,11 @@
 	 */
 	SAVED_SCSIID {
 		size		1
+		dont_generate_debug_code
 	}
 	SAVED_LUN {
 		size		1
+		dont_generate_debug_code
 	}
 	/*
 	 * The last bus phase as seen by the sequencer. 

@@ -3733,6 +3883,7 @@
 	 */
 	QOUTFIFO_ENTRY_VALID_TAG {
 		size		1
+		dont_generate_debug_code
 	}
 	/*
 	 * Kernel and sequencer offsets into the queue of

@@ -3742,10 +3893,12 @@
 	KERNEL_TQINPOS {
 		size		1
 		count		1
+		dont_generate_debug_code
 	}
 	TQINPOS {
 		size		1
 		count		8
+		dont_generate_debug_code
 	}
 	/*
 	 * Base address of our shared data with the kernel driver in host

@@ -3754,6 +3907,7 @@
 	 */
 	SHARED_DATA_ADDR {
 		size		4
+		dont_generate_debug_code
 	}
 	/*
 	 * Pointer to location in host memory for next

@@ -3761,6 +3915,7 @@
 	 */
 	QOUTFIFO_NEXT_ADDR {
 		size		4
+		dont_generate_debug_code
 	}
 	ARG_1 {
 		size		1

@@ -3773,11 +3928,13 @@
 		mask	CONT_MSG_LOOP_READ	0x03
 		mask	CONT_MSG_LOOP_TARG	0x02
 		alias	RETURN_1
+		dont_generate_debug_code
 	}
 	ARG_2 {
 		size		1
 		count		1
 		alias	RETURN_2
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3785,6 +3942,7 @@
 	 */
 	LAST_MSG {
 		size		1
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3801,6 +3959,7 @@
 		field	MANUALP		0x0C
 		field	ENAUTOATNP	0x02
 		field	ALTSTIM		0x01
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3809,6 +3968,7 @@
 	INITIATOR_TAG {
 		size		1
 		count		1
+		dont_generate_debug_code
 	}
 
 	SEQ_FLAGS2 {

@@ -3820,6 +3980,7 @@
 
 	ALLOCFIFO_SCBPTR {
 		size		2
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3829,6 +3990,7 @@
 	 */
 	INT_COALESCING_TIMER {
 		size		2
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3838,6 +4000,7 @@
 	 */
 	INT_COALESCING_MAXCMDS {
 		size		1
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3846,6 +4009,7 @@
 	 */
 	INT_COALESCING_MINCMDS {
 		size		1
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3853,6 +4017,7 @@
 	 */
 	CMDS_PENDING {
 		size		2
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3860,6 +4025,7 @@
 	 */
 	INT_COALESCING_CMDCOUNT {
 		size		1
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3868,6 +4034,7 @@
 	 */
 	LOCAL_HS_MAILBOX {
 		size		1
+		dont_generate_debug_code
 	}
 	/*
 	 * Target-mode CDB type to CDB length table used

@@ -3876,6 +4043,7 @@
 	CMDSIZE_TABLE {
 		size		8
 		count		8
+		dont_generate_debug_code
 	}
 	/*
 	 * When an SCB with the MK_MESSAGE flag is

@@ -3908,25 +4076,31 @@
 		size	4
 		alias	SCB_CDB_STORE
 		alias	SCB_HOST_CDB_PTR
+		dont_generate_debug_code
 	}
 	SCB_RESIDUAL_SGPTR {
 		size	4
 		field	SG_ADDR_MASK		0xf8	/* In the last byte */
 		field	SG_OVERRUN_RESID	0x02	/* In the first byte */
 		field	SG_LIST_NULL		0x01	/* In the first byte */
+		dont_generate_debug_code
 	}
 	SCB_SCSI_STATUS {
 		size	1
 		alias	SCB_HOST_CDB_LEN
+		dont_generate_debug_code
 	}
 	SCB_TARGET_PHASES {
 		size	1
+		dont_generate_debug_code
 	}
 	SCB_TARGET_DATA_DIR {
 		size	1
+		dont_generate_debug_code
 	}
 	SCB_TARGET_ITAG {
 		size	1
+		dont_generate_debug_code
 	}
 	SCB_SENSE_BUSADDR {
 		/*

@@ -3936,10 +4110,12 @@
 		 */
 		size	4
 		alias	SCB_NEXT_COMPLETE
+		dont_generate_debug_code
 	}
 	SCB_TAG {
 		alias	SCB_FIFO_USE_COUNT
 		size	2
+		dont_generate_debug_code
 	}
 	SCB_CONTROL {
 		size	1

@@ -3959,6 +4135,7 @@
 	SCB_LUN {
 		size	1
 		field	LID	0xff
+		dont_generate_debug_code
 	}
 	SCB_TASK_ATTRIBUTE {
 		size	1

@@ -3967,16 +4144,20 @@
 		 * ignore wide residue message handling.
 		 */
 		field	SCB_XFERLEN_ODD	0x01
+		dont_generate_debug_code
 	}
 	SCB_CDB_LEN {
 		size	1
 		field	SCB_CDB_LEN_PTR	0x80	/* CDB in host memory */
+		dont_generate_debug_code
 	}
 	SCB_TASK_MANAGEMENT {
 		size	1
+		dont_generate_debug_code
 	}
 	SCB_DATAPTR {
 		size	8
+		dont_generate_debug_code
 	}
 	SCB_DATACNT {
 		/*

@@ -3986,22 +4167,27 @@
 		size	4
 		field	SG_LAST_SEG		0x80	/* In the fourth byte */
 		field	SG_HIGH_ADDR_BITS	0x7F	/* In the fourth byte */
+		dont_generate_debug_code
 	}
 	SCB_SGPTR {
 		size	4
 		field	SG_STATUS_VALID	0x04	/* In the first byte */
 		field	SG_FULL_RESID	0x02	/* In the first byte */
 		field	SG_LIST_NULL	0x01	/* In the first byte */
+		dont_generate_debug_code
 	}
 	SCB_BUSADDR {
 		size	4
+		dont_generate_debug_code
 	}
 	SCB_NEXT {
 		alias	SCB_NEXT_SCB_BUSADDR
 		size	2
+		dont_generate_debug_code
 	}
 	SCB_NEXT2 {
 		size	2
+		dont_generate_debug_code
 	}
 	SCB_SPARE {
 		size	8

@@ -4009,6 +4195,7 @@
 	}
 	SCB_DISCONNECTED_LISTS {
 		size	8
+		dont_generate_debug_code
 	}
 }
 

743 lines not on this page · raw message

@@ -34,13 +34,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_clrint_print;
-#else
-#define ahd_clrint_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "CLRINT", 0x03, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_error_print;
 #else
 #define ahd_error_print(regvalue, cur_col, wrap) \

@@ -48,20 +41,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_hcntrl_print;
-#else
-#define ahd_hcntrl_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "HCNTRL", 0x05, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_hnscb_qoff_print;
-#else
-#define ahd_hnscb_qoff_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "HNSCB_QOFF", 0x06, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_hescb_qoff_print;
 #else
 #define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \

@@ -97,13 +76,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_snscb_qoff_print;
-#else
-#define ahd_snscb_qoff_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SNSCB_QOFF", 0x10, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_sescb_qoff_print;
 #else
 #define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \

@@ -111,20 +83,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_sdscb_qoff_print;
-#else
-#define ahd_sdscb_qoff_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SDSCB_QOFF", 0x14, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_qoff_ctlsta_print;
-#else
-#define ahd_qoff_ctlsta_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "QOFF_CTLSTA", 0x16, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_intctl_print;
 #else
 #define ahd_intctl_print(regvalue, cur_col, wrap) \

@@ -139,13 +97,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_dscommand0_print;
-#else
-#define ahd_dscommand0_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "DSCOMMAND0", 0x19, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_dfstatus_print;
 #else
 #define ahd_dfstatus_print(regvalue, cur_col, wrap) \

@@ -160,13 +111,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_sg_cache_pre_print;
-#else
-#define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SG_CACHE_PRE", 0x1b, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_lqin_print;
 #else
 #define ahd_lqin_print(regvalue, cur_col, wrap) \

@@ -293,13 +237,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_sxfrctl1_print;
-#else
-#define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SXFRCTL1", 0x3d, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_dffstat_print;
 #else
 #define ahd_dffstat_print(regvalue, cur_col, wrap) \

@@ -314,13 +251,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_scsisigo_print;
-#else
-#define ahd_scsisigo_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_scsisigi_print;
 #else
 #define ahd_scsisigi_print(regvalue, cur_col, wrap) \

@@ -363,13 +293,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_optionmode_print;
-#else
-#define ahd_optionmode_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "OPTIONMODE", 0x4a, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_sblkctl_print;
 #else
 #define ahd_sblkctl_print(regvalue, cur_col, wrap) \

@@ -391,13 +314,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_clrsint0_print;
-#else
-#define ahd_clrsint0_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_sstat1_print;
 #else
 #define ahd_sstat1_print(regvalue, cur_col, wrap) \

@@ -405,13 +321,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_clrsint1_print;
-#else
-#define ahd_clrsint1_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_sstat2_print;
 #else
 #define ahd_sstat2_print(regvalue, cur_col, wrap) \

@@ -461,17 +370,17 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_lqimode0_print;
+ahd_reg_print_t ahd_clrlqiint0_print;
 #else
-#define ahd_lqimode0_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap)
+#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \
+    ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap)
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_clrlqiint0_print;
+ahd_reg_print_t ahd_lqimode0_print;
 #else
-#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap)
+#define ahd_lqimode0_print(regvalue, cur_col, wrap) \
+    ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap)
 #endif
 
 #if AIC_DEBUG_REGISTERS

@@ -629,17 +538,17 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_seqimode_print;
+ahd_reg_print_t ahd_currscb_print;
 #else
-#define ahd_seqimode_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap)
+#define ahd_currscb_print(regvalue, cur_col, wrap) \
+    ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap)
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_currscb_print;
+ahd_reg_print_t ahd_seqimode_print;
 #else
-#define ahd_currscb_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap)
+#define ahd_seqimode_print(regvalue, cur_col, wrap) \
+    ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap)
 #endif
 
 #if AIC_DEBUG_REGISTERS

@@ -657,13 +566,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_shaddr_print;
-#else
-#define ahd_shaddr_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SHADDR", 0x60, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_negoaddr_print;
 #else
 #define ahd_negoaddr_print(regvalue, cur_col, wrap) \

@@ -748,20 +650,13 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_haddr_print;
+ahd_reg_print_t ahd_scbhaddr_print;
 #else
-#define ahd_haddr_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "HADDR", 0x70, regvalue, cur_col, wrap)
+#define ahd_scbhaddr_print(regvalue, cur_col, wrap) \
+    ahd_print_register(NULL, 0, "SCBHADDR", 0x7c, regvalue, cur_col, wrap)
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_hcnt_print;
-#else
-#define ahd_hcnt_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "HCNT", 0x78, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_sghaddr_print;
 #else
 #define ahd_sghaddr_print(regvalue, cur_col, wrap) \

@@ -769,10 +664,10 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_scbhaddr_print;
+ahd_reg_print_t ahd_scbhcnt_print;
 #else
-#define ahd_scbhaddr_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SCBHADDR", 0x7c, regvalue, cur_col, wrap)
+#define ahd_scbhcnt_print(regvalue, cur_col, wrap) \
+    ahd_print_register(NULL, 0, "SCBHCNT", 0x84, regvalue, cur_col, wrap)
 #endif
 
 #if AIC_DEBUG_REGISTERS

@@ -783,20 +678,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_scbhcnt_print;
-#else
-#define ahd_scbhcnt_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SCBHCNT", 0x84, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_dff_thrsh_print;
-#else
-#define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "DFF_THRSH", 0x88, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_pcixctl_print;
 #else
 #define ahd_pcixctl_print(regvalue, cur_col, wrap) \

@@ -867,13 +748,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_scbptr_print;
-#else
-#define ahd_scbptr_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SCBPTR", 0xa8, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_scbautoptr_print;
 #else
 #define ahd_scbautoptr_print(regvalue, cur_col, wrap) \

@@ -881,13 +755,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_ccsgaddr_print;
-#else
-#define ahd_ccsgaddr_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "CCSGADDR", 0xac, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_ccscbaddr_print;
 #else
 #define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \

@@ -909,13 +776,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_ccsgram_print;
-#else
-#define ahd_ccsgram_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "CCSGRAM", 0xb0, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_ccscbram_print;
 #else
 #define ahd_ccscbram_print(regvalue, cur_col, wrap) \

@@ -930,13 +790,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_brdctl_print;
-#else
-#define ahd_brdctl_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "BRDCTL", 0xb9, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_seeadr_print;
 #else
 #define ahd_seeadr_print(regvalue, cur_col, wrap) \

@@ -972,13 +825,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_dfdat_print;
-#else
-#define ahd_dfdat_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "DFDAT", 0xc4, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_dspselect_print;
 #else
 #define ahd_dspselect_print(regvalue, cur_col, wrap) \

@@ -1000,13 +846,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_flags_print;
-#else
-#define ahd_flags_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "FLAGS", 0xd8, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_seqintctl_print;
 #else
 #define ahd_seqintctl_print(regvalue, cur_col, wrap) \

@@ -1014,13 +853,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_seqram_print;
-#else
-#define ahd_seqram_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SEQRAM", 0xda, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_prgmcnt_print;
 #else
 #define ahd_prgmcnt_print(regvalue, cur_col, wrap) \

@@ -1028,41 +860,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_accum_print;
-#else
-#define ahd_accum_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "ACCUM", 0xe0, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_sindex_print;
-#else
-#define ahd_sindex_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SINDEX", 0xe2, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_dindex_print;
-#else
-#define ahd_dindex_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "DINDEX", 0xe4, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_allones_print;
-#else
-#define ahd_allones_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "ALLONES", 0xe8, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_allzeros_print;
-#else
-#define ahd_allzeros_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "ALLZEROS", 0xea, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_none_print;
 #else
 #define ahd_none_print(regvalue, cur_col, wrap) \

@@ -1070,27 +867,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_sindir_print;
-#else
-#define ahd_sindir_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SINDIR", 0xec, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_dindir_print;
-#else
-#define ahd_dindir_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "DINDIR", 0xed, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_stack_print;
-#else
-#define ahd_stack_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "STACK", 0xf2, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_intvec1_addr_print;
 #else
 #define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \

@@ -1126,17 +902,17 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_sram_base_print;
+ahd_reg_print_t ahd_waiting_scb_tails_print;
 #else
-#define ahd_sram_base_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap)
+#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \
+    ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap)
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_waiting_scb_tails_print;
+ahd_reg_print_t ahd_sram_base_print;
 #else
-#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap)
+#define ahd_sram_base_print(regvalue, cur_col, wrap) \
+    ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap)
 #endif
 
 #if AIC_DEBUG_REGISTERS

@@ -1224,13 +1000,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_dmaparams_print;
-#else
-#define ahd_dmaparams_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "DMAPARAMS", 0x138, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_seq_flags_print;
 #else
 #define ahd_seq_flags_print(regvalue, cur_col, wrap) \

@@ -1238,20 +1007,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_saved_scsiid_print;
-#else
-#define ahd_saved_scsiid_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SAVED_SCSIID", 0x13a, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_saved_lun_print;
-#else
-#define ahd_saved_lun_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SAVED_LUN", 0x13b, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_lastphase_print;
 #else
 #define ahd_lastphase_print(regvalue, cur_col, wrap) \

@@ -1273,20 +1028,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_tqinpos_print;
-#else
-#define ahd_tqinpos_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "TQINPOS", 0x13f, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_shared_data_addr_print;
-#else
-#define ahd_shared_data_addr_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x140, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_qoutfifo_next_addr_print;
 #else
 #define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \

@@ -1294,20 +1035,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_arg_1_print;
-#else
-#define ahd_arg_1_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "ARG_1", 0x148, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_arg_2_print;
-#else
-#define ahd_arg_2_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "ARG_2", 0x149, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_last_msg_print;
 #else
 #define ahd_last_msg_print(regvalue, cur_col, wrap) \

@@ -1406,13 +1133,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_scb_residual_datacnt_print;
-#else
-#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_scb_base_print;
 #else
 #define ahd_scb_base_print(regvalue, cur_col, wrap) \

@@ -1420,20 +1140,13 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_scb_residual_sgptr_print;
+ahd_reg_print_t ahd_scb_residual_datacnt_print;
 #else
-#define ahd_scb_residual_sgptr_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0x184, regvalue, cur_col, wrap)
+#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \
+    ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap)
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_scb_scsi_status_print;
-#else
-#define ahd_scb_scsi_status_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SCB_SCSI_STATUS", 0x188, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_scb_sense_busaddr_print;
 #else
 #define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \

@@ -1476,13 +1189,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_scb_cdb_len_print;
-#else
-#define ahd_scb_cdb_len_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SCB_CDB_LEN", 0x196, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_scb_task_management_print;
 #else
 #define ahd_scb_task_management_print(regvalue, cur_col, wrap) \

@@ -1518,13 +1224,6 @@
 #endif
 
 #if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_scb_next_print;
-#else
-#define ahd_scb_next_print(regvalue, cur_col, wrap) \
-    ahd_print_register(NULL, 0, "SCB_NEXT", 0x1ac, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
 ahd_reg_print_t ahd_scb_next2_print;
 #else
 #define ahd_scb_next2_print(regvalue, cur_col, wrap) \

@@ -1717,10 +1416,10 @@
 
 #define	SG_CACHE_PRE    		0x1b
 
-#define	TYPEPTR         		0x20
-
 #define	LQIN            		0x20
 
+#define	TYPEPTR         		0x20
+
 #define	TAGPTR          		0x21
 
 #define	LUNPTR          		0x22

@@ -1780,6 +1479,14 @@
 #define		SINGLECMD       	0x02
 #define		ABORTPENDING    	0x01
 
+#define	SCSBIST0        		0x39
+#define		GSBISTERR       	0x40
+#define		GSBISTDONE      	0x20
+#define		GSBISTRUN       	0x10
+#define		OSBISTERR       	0x04
+#define		OSBISTDONE      	0x02
+#define		OSBISTRUN       	0x01
+
 #define	LQCTL2          		0x39
 #define		LQIRETRY        	0x80
 #define		LQICONTINUE     	0x40

@@ -1790,13 +1497,10 @@
 #define		LQOTOIDLE       	0x02
 #define		LQOPAUSE        	0x01
 
-#define	SCSBIST0        		0x39
-#define		GSBISTERR       	0x40
-#define		GSBISTDONE      	0x20
-#define		GSBISTRUN       	0x10
-#define		OSBISTERR       	0x04
-#define		OSBISTDONE      	0x02
-#define		OSBISTRUN       	0x01
+#define	SCSBIST1        		0x3a
+#define		NTBISTERR       	0x04
+#define		NTBISTDONE      	0x02
+#define		NTBISTRUN       	0x01
 
 #define	SCSISEQ0        		0x3a
 #define		TEMODEO         	0x80

@@ -1805,15 +1509,8 @@
 #define		FORCEBUSFREE    	0x10
 #define		SCSIRSTO        	0x01
 
-#define	SCSBIST1        		0x3a
-#define		NTBISTERR       	0x04
-#define		NTBISTDONE      	0x02
-#define		NTBISTRUN       	0x01
-
 #define	SCSISEQ1        		0x3b
 
-#define	BUSINITID       		0x3c
-
 #define	SXFRCTL0        		0x3c
 #define		DFON            	0x80
 #define		DFPEXP          	0x40

@@ -1822,6 +1519,8 @@
 
 #define	DLCOUNT         		0x3c
 
+#define	BUSINITID       		0x3c
+
 #define	SXFRCTL1        		0x3d
 #define		BITBUCKET       	0x80
 #define		ENSACHK         	0x40

@@ -1846,8 +1545,6 @@
 #define		CURRFIFO_1      	0x01
 #define		CURRFIFO_0      	0x00
 
-#define	MULTARGID       		0x40
-
 #define	SCSISIGO        		0x40
 #define		CDO             	0x80
 #define		IOO             	0x40

@@ -1858,6 +1555,8 @@
 #define		REQO            	0x02
 #define		ACKO            	0x01
 
+#define	MULTARGID       		0x40
+
 #define	SCSISIGI        		0x41
 #define		ATNI            	0x10
 #define		SELI            	0x08

@@ -1904,6 +1603,15 @@
 #define		ENAB20          	0x04
 #define		SELWIDE         	0x02
 
+#define	CLRSINT0        		0x4b
+#define		CLRSELDO        	0x40
+#define		CLRSELDI        	0x20
+#define		CLRSELINGO      	0x10
+#define		CLRIOERR        	0x08
+#define		CLROVERRUN      	0x04
+#define		CLRSPIORDY      	0x02
+#define		CLRARBDO        	0x01
+
 #define	SSTAT0          		0x4b
 #define		TARGET          	0x80
 #define		SELDO           	0x40

@@ -1923,14 +1631,14 @@
 #define		ENSPIORDY       	0x02
 #define		ENARBDO         	0x01
 
-#define	CLRSINT0        		0x4b
-#define		CLRSELDO        	0x40
-#define		CLRSELDI        	0x20
-#define		CLRSELINGO      	0x10
-#define		CLRIOERR        	0x08
-#define		CLROVERRUN      	0x04
-#define		CLRSPIORDY      	0x02
-#define		CLRARBDO        	0x01
+#define	CLRSINT1        		0x4c
+#define		CLRSELTIMEO     	0x80
+#define		CLRATNO         	0x40
+#define		CLRSCSIRSTI     	0x20
+#define		CLRBUSFREE      	0x08
+#define		CLRSCSIPERR     	0x04
+#define		CLRSTRB2FAST    	0x02
+#define		CLRREQINIT      	0x01
 
 #define	SSTAT1          		0x4c
 #define		SELTO           	0x80

@@ -1942,15 +1650,6 @@
 #define		STRB2FAST       	0x02
 #define		REQINIT         	0x01
 
-#define	CLRSINT1        		0x4c
-#define		CLRSELTIMEO     	0x80
-#define		CLRATNO         	0x40
-#define		CLRSCSIRSTI     	0x20
-#define		CLRBUSFREE      	0x08
-#define		CLRSCSIPERR     	0x04
-#define		CLRSTRB2FAST    	0x02
-#define		CLRREQINIT      	0x01
-
 #define	SSTAT2          		0x4d
 #define		BUSFREETIME     	0xc0
 #define		NONPACKREQ      	0x20

@@ -1998,14 +1697,6 @@
 #define		LQIATNLQ        	0x02
 #define		LQIATNCMD       	0x01
 
-#define	LQIMODE0        		0x50
-#define		ENLQIATNQASK    	0x20
-#define		ENLQICRCT1      	0x10
-#define		ENLQICRCT2      	0x08
-#define		ENLQIBADLQT     	0x04
-#define		ENLQIATNLQ      	0x02
-#define		ENLQIATNCMD     	0x01
-
 #define	CLRLQIINT0      		0x50
 #define		CLRLQIATNQAS    	0x20
 #define		CLRLQICRCT1     	0x10

@@ -2014,6 +1705,14 @@
 #define		CLRLQIATNLQ     	0x02
 #define		CLRLQIATNCMD    	0x01
 
+#define	LQIMODE0        		0x50
+#define		ENLQIATNQASK    	0x20
+#define		ENLQICRCT1      	0x10
+#define		ENLQICRCT2      	0x08
+#define		ENLQIBADLQT     	0x04
+#define		ENLQIATNLQ      	0x02
+#define		ENLQIATNCMD     	0x01
+
 #define	LQIMODE1        		0x51
 #define		ENLQIPHASE_LQ   	0x80
 #define		ENLQIPHASE_NLQ  	0x40

@@ -2160,6 +1859,8 @@
 #define		CFG4ICMD        	0x02
 #define		CFG4TCMD        	0x01
 
+#define	CURRSCB         		0x5c
+
 #define	SEQIMODE        		0x5c
 #define		ENCTXTDONE      	0x40
 #define		ENSAVEPTRS      	0x20

@@ -2169,8 +1870,6 @@
 #define		ENCFG4ICMD      	0x02
 #define		ENCFG4TCMD      	0x01
 
-#define	CURRSCB         		0x5c
-
 #define	MDFFSTAT        		0x5d
 #define		SHCNTNEGATIVE   	0x40
 #define		SHCNTMINUS1     	0x20

@@ -2185,29 +1884,29 @@
 
 #define	DFFTAG          		0x5e
 
+#define	LASTSCB         		0x5e
+
 #define	SCSITEST        		0x5e
 #define		CNTRTEST        	0x08
 #define		SEL_TXPLL_DEBUG 	0x04
 
-#define	LASTSCB         		0x5e
-
 #define	IOPDNCTL        		0x5f
 #define		DISABLE_OE      	0x80
 #define		PDN_IDIST       	0x04
 #define		PDN_DIFFSENSE   	0x01
 
-#define	DGRPCRCI        		0x60
-
 #define	SHADDR          		0x60
 
 #define	NEGOADDR        		0x60
 
+#define	DGRPCRCI        		0x60
+
 #define	NEGPERIOD       		0x61
 
-#define	NEGOFFSET       		0x62
-
 #define	PACKCRCI        		0x62
 
+#define	NEGOFFSET       		0x62
+
 #define	NEGPPROPTS      		0x63
 #define		PPROPT_PACE     	0x08
 #define		PPROPT_QAS      	0x04

@@ -2253,8 +1952,6 @@
 
 #define	SELOID          		0x6b
 
-#define	FAIRNESS        		0x6c
-
 #define	PLL400CTL0      		0x6c
 #define		PLL_VCOSEL      	0x80
 #define		PLL_PWDN        	0x40

@@ -2264,6 +1961,8 @@
 #define		PLL_DLPF        	0x02
 #define		PLL_ENFBM       	0x01
 
+#define	FAIRNESS        		0x6c
+
 #define	PLL400CTL1      		0x6d
 #define		PLL_CNTEN       	0x80
 #define		PLL_CNTCLR      	0x40

@@ -2275,25 +1974,25 @@
 
 #define	HADDR           		0x70
 
-#define	HODMAADR        		0x70
-
 #define	PLLDELAY        		0x70
 #define		SPLIT_DROP_REQ  	0x80
 
-#define	HCNT            		0x78
+#define	HODMAADR        		0x70
 
 #define	HODMACNT        		0x78
 
+#define	HCNT            		0x78
+
 #define	HODMAEN         		0x7a
 
-#define	SGHADDR         		0x7c
-
 #define	SCBHADDR        		0x7c
 
-#define	SGHCNT          		0x84
+#define	SGHADDR         		0x7c
 
 #define	SCBHCNT         		0x84
 
+#define	SGHCNT          		0x84
+
 #define	DFF_THRSH       		0x88
 #define		WR_DFTHRSH      	0x70
 #define		RD_DFTHRSH      	0x07

@@ -2326,10 +2025,6 @@
 
 #define	CMCRXMSG0       		0x90
 
-#define	OVLYRXMSG0      		0x90
-
-#define	DCHRXMSG0       		0x90
-
 #define	ROENABLE        		0x90
 #define		MSIROEN         	0x20
 #define		OVLYROEN        	0x10

@@ -2338,11 +2033,11 @@
 #define		DCH1ROEN        	0x02
 #define		DCH0ROEN        	0x01
 
-#define	OVLYRXMSG1      		0x91
+#define	OVLYRXMSG0      		0x90
 
-#define	CMCRXMSG1       		0x91
+#define	DCHRXMSG0       		0x90
 
-#define	DCHRXMSG1       		0x91
+#define	OVLYRXMSG1      		0x91
 
 #define	NSENABLE        		0x91
 #define		MSINSEN         	0x20

@@ -2352,6 +2047,10 @@
 #define		DCH1NSEN        	0x02
 #define		DCH0NSEN        	0x01
 
+#define	CMCRXMSG1       		0x91
+
+#define	DCHRXMSG1       		0x91
+
 #define	DCHRXMSG2       		0x92
 
 #define	CMCRXMSG2       		0x92

@@ -2375,24 +2074,24 @@
 #define		TSCSERREN       	0x02
 #define		CMPABCDIS       	0x01
 
-#define	CMCSEQBCNT      		0x94
-
 #define	OVLYSEQBCNT     		0x94
 
 #define	DCHSEQBCNT      		0x94
 
+#define	CMCSEQBCNT      		0x94
+
+#define	CMCSPLTSTAT0    		0x96
+
 #define	DCHSPLTSTAT0    		0x96
 
 #define	OVLYSPLTSTAT0   		0x96
 
-#define	CMCSPLTSTAT0    		0x96
+#define	CMCSPLTSTAT1    		0x97
 
 #define	OVLYSPLTSTAT1   		0x97
 
 #define	DCHSPLTSTAT1    		0x97
 
-#define	CMCSPLTSTAT1    		0x97
-
 #define	SGRXMSG0        		0x98
 #define		CDNUM           	0xf8
 #define		CFNUM           	0x07

@@ -2420,15 +2119,18 @@
 #define		TAG_NUM         	0x1f
 #define		RLXORD          	0x10
 
+#define	SGSEQBCNT       		0x9c
+
 #define	SLVSPLTOUTATTR0 		0x9c
 #define		LOWER_BCNT      	0xff
 
-#define	SGSEQBCNT       		0x9c
-
 #define	SLVSPLTOUTATTR1 		0x9d
 #define		CMPLT_DNUM      	0xf8
 #define		CMPLT_FNUM      	0x07
 
+#define	SLVSPLTOUTATTR2 		0x9e
+#define		CMPLT_BNUM      	0xff
+
 #define	SGSPLTSTAT0     		0x9e
 #define		STAETERM        	0x80
 #define		SCBCERR         	0x40

@@ -2439,9 +2141,6 @@
 #define		RXSCEMSG        	0x02
 #define		RXSPLTRSP       	0x01
 
-#define	SLVSPLTOUTATTR2 		0x9e
-#define		CMPLT_BNUM      	0xff
-
 #define	SGSPLTSTAT1     		0x9f
 #define		RXDATABUCKET    	0x01
 

@@ -2497,10 +2196,10 @@
 
 #define	CCSGADDR        		0xac
 
-#define	CCSCBADDR       		0xac
-
 #define	CCSCBADR_BK     		0xac
 
+#define	CCSCBADDR       		0xac
+
 #define	CMC_RAMBIST     		0xad
 #define		SG_ELEMENT_SIZE 	0x80
 #define		SCBRAMBIST_FAIL 	0x40

@@ -2554,9 +2253,9 @@
 #define	SEEDAT          		0xbc
 
 #define	SEECTL          		0xbe
-#define		SEEOP_EWDS      	0x40
 #define		SEEOP_WALL      	0x40
 #define		SEEOP_EWEN      	0x40
+#define		SEEOP_EWDS      	0x40
 #define		SEEOPCODE       	0x70
 #define		SEERST          	0x02
 #define		SEESTART        	0x01

@@ -2573,25 +2272,25 @@
 
 #define	SCBCNT          		0xbf
 
+#define	DFWADDR         		0xc0
+
 #define	DSPFLTRCTL      		0xc0
 #define		FLTRDISABLE     	0x20
 #define		EDGESENSE       	0x10
 #define		DSPFCNTSEL      	0x0f
 
-#define	DFWADDR         		0xc0
-
 #define	DSPDATACTL      		0xc1
 #define		BYPASSENAB      	0x80
 #define		DESQDIS         	0x10
 #define		RCVROFFSTDIS    	0x04
 #define		XMITOFFSTDIS    	0x02
 
+#define	DFRADDR         		0xc2
+
 #define	DSPREQCTL       		0xc2
 #define		MANREQCTL       	0xc0
 #define		MANREQDLY       	0x3f
 
-#define	DFRADDR         		0xc2
-
 #define	DSPACKCTL       		0xc3
 #define		MANACKCTL       	0xc0
 #define		MANACKDLY       	0x3f

@@ -2612,14 +2311,14 @@
 
 #define	WRTBIASCALC     		0xc7
 
-#define	DFPTRS          		0xc8
-
 #define	RCVRBIASCALC    		0xc8
 
-#define	DFBKPTR         		0xc9
+#define	DFPTRS          		0xc8
 
 #define	SKEWCALC        		0xc9
 
+#define	DFBKPTR         		0xc9
+
 #define	DFDBCTL         		0xcb
 #define		DFF_CIO_WR_RDY  	0x20
 #define		DFF_CIO_RD_RDY  	0x10

@@ -2704,12 +2403,12 @@
 
 #define	ACCUM_SAVE      		0xfa
 
+#define	WAITING_SCB_TAILS		0x100
+
 #define	AHD_PCI_CONFIG_BASE		0x100
 
 #define	SRAM_BASE       		0x100
 
-#define	WAITING_SCB_TAILS		0x100
-
 #define	WAITING_TID_HEAD		0x120
 
 #define	WAITING_TID_TAIL		0x122

@@ -2738,8 +2437,8 @@
 #define		PRELOADEN       	0x80
 #define		WIDEODD         	0x40
 #define		SCSIEN          	0x20
-#define		SDMAENACK       	0x10
 #define		SDMAEN          	0x10
+#define		SDMAENACK       	0x10
 #define		HDMAEN          	0x08
 #define		HDMAENACK       	0x08
 #define		DIRECTION       	0x04

@@ -2837,12 +2536,12 @@
 
 #define	MK_MESSAGE_SCSIID		0x162
 
+#define	SCB_BASE        		0x180
+
 #define	SCB_RESIDUAL_DATACNT		0x180
 #define	SCB_CDB_STORE   		0x180
 #define	SCB_HOST_CDB_PTR		0x180
 
-#define	SCB_BASE        		0x180
-
 #define	SCB_RESIDUAL_SGPTR		0x184
 #define		SG_ADDR_MASK    	0xf8
 #define		SG_OVERRUN_RESID	0x02

@@ -2910,17 +2609,6 @@
 #define	SCB_DISCONNECTED_LISTS		0x1b8
 
 
-#define	CMD_GROUP_CODE_SHIFT	0x05
-#define	STIMESEL_MIN	0x18
-#define	STIMESEL_SHIFT	0x03
-#define	INVALID_ADDR	0x80
-#define	AHD_PRECOMP_MASK	0x07
-#define	TARGET_DATA_IN	0x01
-#define	CCSCBADDR_MAX	0x80
-#define	NUMDSPS 	0x14
-#define	SEEOP_EWEN_ADDR	0xc0
-#define	AHD_ANNEXCOL_PER_DEV0	0x04
-#define	DST_MODE_SHIFT	0x04
 #define	AHD_TIMER_MAX_US	0x18ffe7
 #define	AHD_TIMER_MAX_TICKS	0xffff
 #define	AHD_SENSE_BUFSIZE	0x100

@@ -2955,32 +2643,43 @@
 #define	LUNLEN_SINGLE_LEVEL_LUN	0x0f
 #define	NVRAM_SCB_OFFSET	0x2c
 #define	STATUS_PKT_SENSE	0xff
+#define	CMD_GROUP_CODE_SHIFT	0x05
 #define	MAX_OFFSET_PACED_BUG	0x7f
 #define	STIMESEL_BUG_ADJ	0x08
+#define	STIMESEL_MIN	0x18
+#define	STIMESEL_SHIFT	0x03
 #define	CCSGRAM_MAXSEGS	0x10
+#define	INVALID_ADDR	0x80
 #define	SEEOP_ERAL_ADDR	0x80
 #define	AHD_SLEWRATE_DEF_REVB	0x08
 #define	AHD_PRECOMP_CUTBACK_17	0x04
+#define	AHD_PRECOMP_MASK	0x07
 #define	SRC_MODE_SHIFT	0x00
 #define	PKT_OVERRUN_BUFSIZE	0x200
 #define	SCB_TRANSFER_SIZE_1BYTE_LUN	0x30
+#define	TARGET_DATA_IN	0x01
 #define	HOST_MSG	0xff
 #define	MAX_OFFSET	0xfe
 #define	BUS_16_BIT	0x01
+#define	CCSCBADDR_MAX	0x80
+#define	NUMDSPS 	0x14
+#define	SEEOP_EWEN_ADDR	0xc0
+#define	AHD_ANNEXCOL_PER_DEV0	0x04
+#define	DST_MODE_SHIFT	0x04
 
 
 /* Downloaded Constant Definitions */
-#define	SG_SIZEOF	0x04
-#define	SG_PREFETCH_ALIGN_MASK	0x02
-#define	SG_PREFETCH_CNT_LIMIT	0x01
 #define	CACHELINE_MASK	0x07
 #define	SCB_TRANSFER_SIZE	0x06
 #define	PKT_OVERRUN_BUFOFFSET	0x05
+#define	SG_SIZEOF	0x04
 #define	SG_PREFETCH_ADDR_MASK	0x03
+#define	SG_PREFETCH_ALIGN_MASK	0x02
+#define	SG_PREFETCH_CNT_LIMIT	0x01
 #define	SG_PREFETCH_CNT	0x00
 #define	DOWNLOAD_CONST_COUNT	0x08
 
 
 /* Exported Labels */
-#define	LABEL_timer_isr	0x28b
 #define	LABEL_seq_isr 	0x28f
+#define	LABEL_timer_isr	0x28b

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@@ -80,6 +80,17 @@
 	}
 
 /*
+ * Registers marked "dont_generate_debug_code" are not (yet) referenced
+ * from the driver code, and this keyword inhibit generation
+ * of debug code for them.
+ *
+ * REG_PRETTY_PRINT config will complain if dont_generate_debug_code
+ * is added to the register which is referenced in the driver.
+ * Unreferenced register with no dont_generate_debug_code will result
+ * in dead code. No warning is issued.
+ */
+
+/*
  * Mode Pointer
  * Controls which of the 5, 512byte, address spaces should be used
  * as the source and destination of any register accesses in our

@@ -91,6 +102,7 @@
 	field	DST_MODE	0x70
 	field	SRC_MODE	0x07
 	mode_pointer
+	dont_generate_debug_code
 }
 
 const SRC_MODE_SHIFT	0

@@ -190,6 +202,7 @@
 		SAW_HWERR,
 		BAD_SCB_STATUS
 	}
+	dont_generate_debug_code
 }
 
 /*

@@ -207,6 +220,7 @@
 	field	CLRSEQINT	0x04
 	field	CLRCMDINT	0x02
 	field	CLRSPLTINT	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -222,6 +236,7 @@
 	field	SQPARERR	0x08
 	field	ILLOPCODE	0x04
 	field	DSCTMOUT	0x02
+	dont_generate_debug_code
 }
 
 /*

@@ -255,6 +270,7 @@
 	field	INTEN		0x02
 	field	CHIPRST		0x01
 	field	CHIPRSTACK	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -265,6 +281,7 @@
 	access_mode	RW
 	size		2
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -274,6 +291,7 @@
 	address			0x008
 	access_mode	RW
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -311,6 +329,7 @@
 	field	CLRSEQ_SCSIINT	0x04
 	field	CLRSEQ_PCIINT	0x02
 	field	CLRSEQ_SPLTINT	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -320,6 +339,7 @@
 	address			0x00E
 	access_mode	RW
 	size		2
+	dont_generate_debug_code
 }
 
 /*

@@ -330,6 +350,7 @@
 	access_mode	RW
 	size		2
 	modes		M_CCHAN
+	dont_generate_debug_code
 }
 
 /*

@@ -340,6 +361,7 @@
 	count		2
 	access_mode	RW
 	modes		M_CCHAN
+	dont_generate_debug_code
 }
 
 /*

@@ -350,6 +372,7 @@
 	access_mode	RW
 	modes		M_CCHAN
 	size		2
+	dont_generate_debug_code
 }
 
 /*

@@ -378,6 +401,7 @@
 		SCB_QSIZE_8192,
 		SCB_QSIZE_16384
 	}
+	dont_generate_debug_code
 }
 
 /*

@@ -431,6 +455,7 @@
 	field	EXTREQLCK	0x10	/* External Request Lock */
 	field	DISABLE_TWATE	0x02	/* Rev B or greater */
 	field	CIOPARCKEN	0x01	/* Internal bus parity error enable */
+	dont_generate_debug_code
 }
 
 /*

@@ -459,6 +484,7 @@
 	field	SG_ADDR_MASK	0xf8
 	field	ODD_SEG		0x04
 	field	LAST_SEG	0x02
+	dont_generate_debug_code
 }
 
 register SG_CACHE_SHADOW {

@@ -491,6 +517,7 @@
 	access_mode	RW
 	size		8
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -522,6 +549,7 @@
 	access_mode	RW
 	size		3
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -551,6 +579,7 @@
 	access_mode	RW
 	size		8
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -561,6 +590,7 @@
 	access_mode	RW
 	size		8
 	modes		M_CCHAN
+	dont_generate_debug_code
 }
 
 /*

@@ -570,6 +600,7 @@
 	address			0x084
 	access_mode	RW
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -579,6 +610,7 @@
 	address			0x084
 	access_mode	RW
 	modes		M_CCHAN
+	dont_generate_debug_code
 }
 
 /*

@@ -609,6 +641,7 @@
 		RD_DFTHRSH_90,
 		RD_DFTHRSH_MAX
 	}
+	dont_generate_debug_code
 }
 
 /*

@@ -817,6 +850,7 @@
 	field	SRSPDPEEN	0x04
 	field	TSCSERREN	0x02
 	field	CMPABCDIS	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -863,6 +897,7 @@
 	field	RXOVRUN		0x04
 	field	RXSCEMSG	0x02
 	field	RXSPLTRSP	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -908,6 +943,7 @@
 	modes		M_DFF0, M_DFF1
 	count		2
 	field	RXDATABUCKET	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1069,6 +1105,7 @@
 	field	RXOVRUN		0x04
 	field	RXSCEMSG	0x02
 	field	RXSPLTRSP	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1080,6 +1117,7 @@
 	modes		M_DFF0, M_DFF1
 	count		2
 	field	RXDATABUCKET	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1091,6 +1129,7 @@
 	modes		M_CFG
 	field	TEST_GROUP	0xF0
 	field	TEST_NUM	0x0F
+	dont_generate_debug_code
 }
 
 /*

@@ -1109,6 +1148,7 @@
 	field	RDPERR		0x04
 	field	TWATERR		0x02
 	field	DPR		0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1204,6 +1244,7 @@
 	field	SSE		0x40
 	field	STA		0x08
 	field	TWATERR		0x02
+	dont_generate_debug_code
 }
 
 /*

@@ -1216,6 +1257,7 @@
 	size		20
 	count		2
 	modes		M_DFF0, M_DFF1, M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -1247,6 +1289,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -1278,6 +1321,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -1290,6 +1334,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -1302,6 +1347,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -1313,6 +1359,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -1324,6 +1371,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -1347,6 +1395,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -1358,6 +1407,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -1398,6 +1448,7 @@
 	count		2
 	mask		ILUNLEN	0x0F
 	mask		TLUNLEN	0xF0
+	dont_generate_debug_code
 }
 const LUNLEN_SINGLE_LEVEL_LUN 0xF
 

@@ -1410,6 +1461,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -1422,6 +1474,7 @@
 	access_mode	RW
 	modes		M_CFG
 	count		9
+	dont_generate_debug_code
 }
 
 /*

@@ -1432,6 +1485,7 @@
 	address			0x033
 	access_mode	RW
 	modes		M_CFG
+	dont_generate_debug_code
 }
 
 /*

@@ -1490,6 +1544,7 @@
 	field	PCI2PCI		0x04
 	field	SINGLECMD	0x02
 	field	ABORTPENDING	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1508,6 +1563,7 @@
 	field	LQOCONTINUE	0x04
 	field	LQOTOIDLE	0x02
 	field	LQOPAUSE	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1578,6 +1634,7 @@
 	field	DFPEXP		0x40
 	field	BIOSCANCELEN	0x10
 	field	SPIOEN		0x08
+	dont_generate_debug_code
 }
 
 /*

@@ -1594,6 +1651,7 @@
 	field	ENSTIMER	0x04
 	field	ACTNEGEN	0x02
 	field	STPWEN		0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1696,6 +1754,7 @@
 		P_STATUS	CDO|IOO,
 		P_MESGIN	CDO|IOO|MSGO
 	}
+	dont_generate_debug_code
 }
 
 /*

@@ -1738,6 +1797,7 @@
 	modes		M_CFG
 	size		2
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -1774,6 +1834,7 @@
 	access_mode	RW
 	modes		M_DFF0, M_DFF1, M_SCSI
 	size		2
+	dont_generate_debug_code
 }
 
 /*

@@ -1796,6 +1857,7 @@
 	count		2
 	field	CLKOUT		0x80
 	field	TARGID		0x0F
+	dont_generate_debug_code
 }
 
 /*

@@ -1825,6 +1887,7 @@
 	field	ENAB40		0x08	/* LVD transceiver active */
 	field	ENAB20		0x04	/* SE/HVD transceiver active */
 	field	SELWIDE		0x02
+	dont_generate_debug_code
 }
 
 /*

@@ -1842,6 +1905,7 @@
 	field	ENDGFORMCHK		0x04
 	field	AUTO_MSGOUT_DE		0x02
 	mask	OPTIONMODE_DEFAULTS	AUTO_MSGOUT_DE
+	dont_generate_debug_code
 }
 
 /*

@@ -1876,6 +1940,7 @@
 	field	CLROVERRUN	0x04
 	field	CLRSPIORDY	0x02
 	field	CLRARBDO	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1929,6 +1994,7 @@
 	field	CLRSCSIPERR	0x04
 	field	CLRSTRB2FAST	0x02
 	field	CLRREQINIT	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -1962,6 +2028,7 @@
 	field	CLRWIDE_RES	0x04	/* Modes 0 and 1 only */
 	field	CLRSDONE	0x02	/* Modes 0 and 1 only */
 	field	CLRDMADONE	0x01	/* Modes 0 and 1 only */
+	dont_generate_debug_code
 }
 
 /*

@@ -2002,6 +2069,7 @@
 	access_mode	RO
 	modes		M_CFG
 	count		6
+	dont_generate_debug_code
 }
 
 /*

@@ -2022,6 +2090,7 @@
 	access_mode	RO
 	modes		M_CFG
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -2054,6 +2123,7 @@
 	field	CLRLQIBADLQT	0x04
 	field	CLRLQIATNLQ	0x02
 	field	CLRLQIATNCMD	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2070,6 +2140,7 @@
 	field	ENLQIBADLQT	0x04
 	field	ENLQIATNLQ	0x02
 	field	ENLQIATNCMD	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2106,6 +2177,7 @@
 	field	CLRLQIBADLQI	0x04
 	field	CLRLQIOVERI_LQ	0x02
 	field	CLRLQIOVERI_NLQ	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2124,6 +2196,7 @@
 	field	ENLQIBADLQI	0x04
 	field	ENLQIOVERI_LQ	0x02	/* LQIOVERI1 */
 	field	ENLQIOVERI_NLQ	0x01	/* LQIOVERI2 */
+	dont_generate_debug_code
 }
 
 /*

@@ -2165,6 +2238,7 @@
 	count		3
 	field	CLRNTRAMPERR	0x02
 	field	CLROSRAMPERR	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2177,6 +2251,7 @@
 	count		4
 	field	ENNTRAMPERR	0x02
 	field	ENOSRAMPERR	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2207,6 +2282,7 @@
 	field	CLRLQOATNLQ		0x04
 	field	CLRLQOATNPKT		0x02
 	field	CLRLQOTCRC		0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2222,6 +2298,7 @@
 	field	ENLQOATNLQ		0x04
 	field	ENLQOATNPKT		0x02
 	field	ENLQOTCRC		0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2251,6 +2328,7 @@
 	field	CLRLQOBADQAS		0x04
 	field	CLRLQOBUSFREE		0x02
 	field	CLRLQOPHACHGINPKT	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2266,6 +2344,7 @@
 	field	ENLQOBADQAS		0x04
 	field	ENLQOBUSFREE		0x02
 	field	ENLQOPHACHGINPKT	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2289,6 +2368,7 @@
 	access_mode	RO
 	modes		M_CFG
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -2318,6 +2398,7 @@
 	access_mode	RO
 	size		2
 	modes		M_DFF0, M_DFF1, M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -2341,6 +2422,7 @@
 	access_mode	RW
 	size		2
 	modes		M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -2357,6 +2439,7 @@
 	field		LQOBUSETDLY	0x40
 	field		LQONOHOLDLACK	0x02
 	field		LQONOCHKOVER	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2389,6 +2472,7 @@
 	field	CLRCFG4TSTAT	0x04
 	field	CLRCFG4ICMD	0x02
 	field	CLRCFG4TCMD	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2415,6 +2499,7 @@
 	access_mode	RW
 	size		2
 	modes		M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -2472,6 +2557,7 @@
 	access_mode	RW
 	size		2
 	modes		M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -2494,6 +2580,7 @@
 	access_mode	RO
 	size		8
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -2513,6 +2600,7 @@
 	address			0x060
 	access_mode	RW
 	modes		M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -2523,6 +2611,7 @@
 	access_mode	RW
 	modes		M_SCSI
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -2543,6 +2632,7 @@
 	access_mode	RW
 	modes		M_SCSI
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -2557,6 +2647,7 @@
 	field	PPROPT_QAS	0x04
 	field	PPROPT_DT	0x02
 	field	PPROPT_IUT	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2573,6 +2664,7 @@
 	field	ENAUTOATNI	0x04
 	field	ENAUTOATNO	0x02
 	field	WIDEXFER	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2583,6 +2675,7 @@
 	access_mode	RW
 	modes		M_SCSI
 	count		7
+	dont_generate_debug_code
 }
 
 /*

@@ -2602,6 +2695,7 @@
 	field	DFFACTCLR	0x04
 	field	SHVALIDSTDIS	0x02
 	field	LSTSGCLRDIS	0x01
+	dont_generate_debug_code
 }
 
 const AHD_ANNEXCOL_PER_DEV0	4

@@ -2635,6 +2729,7 @@
 	access_mode	RW
 	modes		M_SCSI
 	count		3
+	dont_generate_debug_code
 }
 
 /*

@@ -2645,6 +2740,7 @@
 	address			0x067
 	access_mode	RW
 	modes		M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -2671,6 +2767,7 @@
 	access_mode	RW
 	modes		M_SCSI
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -2702,6 +2799,7 @@
 	access_mode	RW
 	size		3
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -2789,6 +2887,7 @@
 	access_mode	RW
 	size		2
 	modes		M_DFF0, M_DFF1, M_CCHAN, M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -2816,6 +2915,7 @@
 	field	AUSCBPTR_EN	0x80
 	field	SCBPTR_ADDR	0x38
 	field	SCBPTR_OFF	0x07
+	dont_generate_debug_code
 }
 
 /*

@@ -2825,6 +2925,7 @@
 	address			0x0AC
 	access_mode	RW
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -2834,6 +2935,7 @@
 	address			0x0AC
 	access_mode	RW
 	modes		M_CCHAN
+	dont_generate_debug_code
 }
 
 /*

@@ -2899,6 +3001,7 @@
 	address			0x0B0
 	access_mode	RW
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -2908,6 +3011,7 @@
 	address			0x0B0
 	access_mode	RW
 	modes		M_CCHAN
+	dont_generate_debug_code
 }
 
 /*

@@ -2958,6 +3062,7 @@
 	access_mode	RW
 	modes		M_SCSI
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -2974,6 +3079,7 @@
 	field	BRDEN		0x04
 	field	BRDRW		0x02
 	field	BRDSTB		0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -2984,6 +3090,7 @@
 	access_mode	RW
 	modes		M_SCSI
 	count		4
+	dont_generate_debug_code
 }
 
 /*

@@ -2995,6 +3102,7 @@
 	size		2
 	modes		M_SCSI
 	count		4
+	dont_generate_debug_code
 }
 
 /*

@@ -3011,6 +3119,7 @@
 	field	SEEARBACK	0x04
 	field	SEEBUSY		0x02
 	field	SEESTART	0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -3036,6 +3145,7 @@
 	mask	SEEOP_EWDS	0x40
 	field	SEERST		0x02
 	field	SEESTART	0x01
+	dont_generate_debug_code
 }
 
 const SEEOP_ERAL_ADDR	0x80

@@ -3050,6 +3160,7 @@
 	address			0x0BF
 	access_mode	RW
 	modes		M_SCSI
+	dont_generate_debug_code
 }
 
 /*

@@ -3061,6 +3172,7 @@
 	access_mode	RW
 	size		2
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -3087,6 +3199,7 @@
 	field	DESQDIS		0x10
 	field	RCVROFFSTDIS	0x04
 	field	XMITOFFSTDIS	0x02
+	dont_generate_debug_code
 }
 
 /*

@@ -3132,6 +3245,7 @@
 	address			0x0C4
 	access_mode	RW
 	modes		M_DFF0, M_DFF1
+	dont_generate_debug_code
 }
 
 /*

@@ -3144,6 +3258,7 @@
 	count		1
 	field	AUTOINCEN	0x80
 	field	DSPSEL		0x1F
+	dont_generate_debug_code
 }
 
 const NUMDSPS 0x14

@@ -3158,6 +3273,7 @@
 	count		3
 	field	AUTOXBCDIS	0x80
 	field	XMITMANVAL	0x3F
+	dont_generate_debug_code
 }
 
 /*

@@ -3316,6 +3432,7 @@
 	count		23
 	field	ZERO		0x02
 	field	CARRY		0x01
+	dont_generate_debug_code
 }
 
 /*

@@ -3344,6 +3461,7 @@
 	address			0x0DA
 	access_mode 	RW
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -3355,6 +3473,7 @@
 	access_mode	RW
 	size		2
 	count		5
+	dont_generate_debug_code
 }
 
 /*

@@ -3364,6 +3483,7 @@
 	address			0x0E0
 	access_mode 	RW
 	accumulator
+	dont_generate_debug_code
 }
 
 /*

@@ -3380,6 +3500,7 @@
 	access_mode	RW
 	size		2
 	sindex
+	dont_generate_debug_code
 }
 
 /*

@@ -3390,6 +3511,7 @@
 	address			0x0E4
 	access_mode	RW
 	size		2
+	dont_generate_debug_code
 }
 
 /*

@@ -3415,6 +3537,7 @@
 	address			0x0E8
 	access_mode RO
 	allones
+	dont_generate_debug_code
 }
 
 /*

@@ -3425,6 +3548,7 @@
 	address			0x0EA
 	access_mode RO
 	allzeros
+	dont_generate_debug_code
 }
 
 /*

@@ -3435,6 +3559,7 @@
 	address			0x0EA
 	access_mode WO
 	none
+	dont_generate_debug_code
 }
 
 /*

@@ -3445,6 +3570,7 @@
 register SINDIR	{
 	address			0x0EC
 	access_mode RO
+	dont_generate_debug_code
 }
 
 /*

@@ -3455,6 +3581,7 @@
 register DINDIR	 {
 	address			0x0ED
 	access_mode WO
+	dont_generate_debug_code
 }
 
 /*

@@ -3479,6 +3606,7 @@
 register STACK {
 	address			0x0F2
 	access_mode RW
+	dont_generate_debug_code
 }
 
 /*

@@ -3491,6 +3619,7 @@
 	size		2
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -3503,6 +3632,7 @@
 	size		2
 	modes		M_SCSI
 	count		2
+	dont_generate_debug_code
 }
 
 /*

@@ -3515,6 +3645,7 @@
 	size		2
 	modes		M_CFG
 	count		1
+	dont_generate_debug_code
 }
 
 /*

@@ -3543,12 +3674,14 @@
 	modes	0, 1, 2, 3
 	REG0 {
 		size		2
+		dont_generate_debug_code
 	}
 	REG1 {
 		size		2
 	}
 	REG_ISR {
 		size		2
+		dont_generate_debug_code
 	}
 	SG_STATE {
 		size		1

@@ -3572,9 +3705,11 @@
 	modes	0, 1, 2, 3
 	LONGJMP_ADDR {
 		size		2
+		dont_generate_debug_code
 	}
 	ACCUM_SAVE {
 		size		1
+		dont_generate_debug_code
 	}
 }
 

@@ -3591,18 +3726,22 @@
 	 */
 	WAITING_SCB_TAILS {
 		size		32
+		dont_generate_debug_code
 	}
 	WAITING_TID_HEAD {
 		size		2
+		dont_generate_debug_code
 	}
 	WAITING_TID_TAIL {
 		size		2
+		dont_generate_debug_code
 	}
 	/*
 	 * SCBID of the next SCB in the new SCB queue.
 	 */
 	NEXT_QUEUED_SCB_ADDR {
 		size		4
+		dont_generate_debug_code
 	}
 	/*
 	 * head of list of SCBs that have

@@ -3611,6 +3750,7 @@
 	 */
 	COMPLETE_SCB_HEAD {
 		size		2
+		dont_generate_debug_code
 	}
 	/*
 	 * The list of completed SCBs in

@@ -3618,6 +3758,7 @@
 	 */
 	COMPLETE_SCB_DMAINPROG_HEAD {
 		size		2
+		dont_generate_debug_code
 	}
 	/*
 	 * head of list of SCBs that have

@@ -3626,6 +3767,7 @@
 	 */
 	COMPLETE_DMA_SCB_HEAD {
 		size		2
+		dont_generate_debug_code
 	}
 	/*
 	 * tail of list of SCBs that have

@@ -3634,6 +3776,7 @@
 	 */
 	COMPLETE_DMA_SCB_TAIL {
 		size		2
+		dont_generate_debug_code
 	}
 	/*
 	 * head of list of SCBs that have

@@ -3643,6 +3786,7 @@
 	 */
 	COMPLETE_ON_QFREEZE_HEAD {
 		size		2
+		dont_generate_debug_code
 	}
 	/*
 	 * Counting semaphore to prevent new select-outs

@@ -3667,6 +3811,7 @@
 	 */
 	MSG_OUT {
 		size		1
+		dont_generate_debug_code
 	}
 	/* Parameters for DMA Logic */
 	DMAPARAMS {

@@ -3682,6 +3827,7 @@
 		field	DIRECTION	0x04	/* Set indicates PCI->SCSI */
 		field	FIFOFLUSH	0x02
 		field	FIFORESET	0x01
+		dont_generate_debug_code
 	}
 	SEQ_FLAGS {
 		size		1

@@ -3703,9 +3849,11 @@
 	 */
 	SAVED_SCSIID {
 		size		1
+		dont_generate_debug_code
 	}
 	SAVED_LUN {
 		size		1
+		dont_generate_debug_code
 	}
 	/*
 	 * The last bus phase as seen by the sequencer. 

@@ -3733,6 +3881,7 @@
 	 */
 	QOUTFIFO_ENTRY_VALID_TAG {
 		size		1
+		dont_generate_debug_code
 	}
 	/*
 	 * Kernel and sequencer offsets into the queue of

@@ -3742,10 +3891,12 @@
 	KERNEL_TQINPOS {
 		size		1
 		count		1
+		dont_generate_debug_code
 	}
 	TQINPOS {
 		size		1
 		count		8
+		dont_generate_debug_code
 	}
 	/*
 	 * Base address of our shared data with the kernel driver in host

@@ -3754,6 +3905,7 @@
 	 */
 	SHARED_DATA_ADDR {
 		size		4
+		dont_generate_debug_code
 	}
 	/*
 	 * Pointer to location in host memory for next

@@ -3761,6 +3913,7 @@
 	 */
 	QOUTFIFO_NEXT_ADDR {
 		size		4
+		dont_generate_debug_code
 	}
 	ARG_1 {
 		size		1

@@ -3773,11 +3926,13 @@
 		mask	CONT_MSG_LOOP_READ	0x03
 		mask	CONT_MSG_LOOP_TARG	0x02
 		alias	RETURN_1
+		dont_generate_debug_code
 	}
 	ARG_2 {
 		size		1
 		count		1
 		alias	RETURN_2
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3785,6 +3940,7 @@
 	 */
 	LAST_MSG {
 		size		1
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3801,6 +3957,7 @@
 		field	MANUALP		0x0C
 		field	ENAUTOATNP	0x02
 		field	ALTSTIM		0x01
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3809,6 +3966,7 @@
 	INITIATOR_TAG {
 		size		1
 		count		1
+		dont_generate_debug_code
 	}
 
 	SEQ_FLAGS2 {

@@ -3820,6 +3978,7 @@
 
 	ALLOCFIFO_SCBPTR {
 		size		2
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3829,6 +3988,7 @@
 	 */
 	INT_COALESCING_TIMER {
 		size		2
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3838,6 +3998,7 @@
 	 */
 	INT_COALESCING_MAXCMDS {
 		size		1
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3846,6 +4007,7 @@
 	 */
 	INT_COALESCING_MINCMDS {
 		size		1
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3853,6 +4015,7 @@
 	 */
 	CMDS_PENDING {
 		size		2
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3860,6 +4023,7 @@
 	 */
 	INT_COALESCING_CMDCOUNT {
 		size		1
+		dont_generate_debug_code
 	}
 
 	/*

@@ -3868,6 +4032,7 @@
 	 */
 	LOCAL_HS_MAILBOX {
 		size		1
+		dont_generate_debug_code
 	}
 	/*
 	 * Target-mode CDB type to CDB length table used

@@ -3876,6 +4041,7 @@
 	CMDSIZE_TABLE {
 		size		8
 		count		8
+		dont_generate_debug_code
 	}
 	/*
 	 * When an SCB with the MK_MESSAGE flag is

@@ -3908,25 +4074,31 @@
 		size	4
 		alias	SCB_CDB_STORE
 		alias	SCB_HOST_CDB_PTR
+		dont_generate_debug_code
 	}
 	SCB_RESIDUAL_SGPTR {
 		size	4
 		field	SG_ADDR_MASK		0xf8	/* In the last byte */
 		field	SG_OVERRUN_RESID	0x02	/* In the first byte */
 		field	SG_LIST_NULL		0x01	/* In the first byte */
+		dont_generate_debug_code
 	}
 	SCB_SCSI_STATUS {
 		size	1
 		alias	SCB_HOST_CDB_LEN
+		dont_generate_debug_code
 	}
 	SCB_TARGET_PHASES {
 		size	1
+		dont_generate_debug_code
 	}
 	SCB_TARGET_DATA_DIR {
 		size	1
+		dont_generate_debug_code
 	}
 	SCB_TARGET_ITAG {
 		size	1
+		dont_generate_debug_code
 	}
 	SCB_SENSE_BUSADDR {
 		/*

@@ -3936,10 +4108,12 @@
 		 */
 		size	4
 		alias	SCB_NEXT_COMPLETE
+		dont_generate_debug_code
 	}
 	SCB_TAG {
 		alias	SCB_FIFO_USE_COUNT
 		size	2
+		dont_generate_debug_code
 	}
 	SCB_CONTROL {
 		size	1

@@ -3959,6 +4133,7 @@
 	SCB_LUN {
 		size	1
 		field	LID	0xff
+		dont_generate_debug_code
 	}
 	SCB_TASK_ATTRIBUTE {
 		size	1

@@ -3967,16 +4142,20 @@
 		 * ignore wide residue message handling.
 		 */
 		field	SCB_XFERLEN_ODD	0x01
+		dont_generate_debug_code
 	}
 	SCB_CDB_LEN {
 		size	1
 		field	SCB_CDB_LEN_PTR	0x80	/* CDB in host memory */
+		dont_generate_debug_code
 	}
 	SCB_TASK_MANAGEMENT {
 		size	1
+		dont_generate_debug_code
 	}
 	SCB_DATAPTR {
 		size	8
+		dont_generate_debug_code
 	}
 	SCB_DATACNT {
 		/*

@@ -3986,22 +4165,27 @@
 		size	4
 		field	SG_LAST_SEG		0x80	/* In the fourth byte */
 		field	SG_HIGH_ADDR_BITS	0x7F	/* In the fourth byte */
+		dont_generate_debug_code
 	}
 	SCB_SGPTR {
 		size	4
 		field	SG_STATUS_VALID	0x04	/* In the first byte */
 		field	SG_FULL_RESID	0x02	/* In the first byte */
 		field	SG_LIST_NULL	0x01	/* In the first byte */
+		dont_generate_debug_code
 	}
 	SCB_BUSADDR {
 		size	4
+		dont_generate_debug_code
 	}
 	SCB_NEXT {
 		alias	SCB_NEXT_SCB_BUSADDR
 		size	2
+		dont_generate_debug_code
 	}
 	SCB_NEXT2 {
 		size	2
+		dont_generate_debug_code
 	}
 	SCB_SPARE {
 		size	8

@@ -4009,6 +4193,7 @@
 	}
 	SCB_DISCONNECTED_LISTS {
 		size	8
+		dont_generate_debug_code
 	}
 }
 

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