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A workaround for AMD erratum 411

PATCH In review Wei Wang2 2 participants 2 messages Jun 4, 2010

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Wei Wang2

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#0 lore raw

PATCH 1/1 A workaround for AMD erratum 411

Hi,
This patch is a workaround of AMD erratum 411 for family 10h CPUs. This does not cause functional issues but may reduce the power saving effectiveness of message-triggered C1e mode. This would normally occur only if OS which has used the local APIC timer masks the interrupt without clearing Timer Initial Count Register.

Thanks,
Wei

Signed-off-by Wei Wang <[email protected]>
Signature · 11 lines
AMD GmbH, Germany
Operating System Research Center

Legal Information:
Advanced Micro Devices GmbH
Karl-Hammerschmidt-Str. 34
85609 Dornach b. München

Geschäftsführer: Andrew Bowd, Thomas M. McCoy, Giuliano Meroni
Sitz: Dornach, Gemeinde Aschheim, Landkreis München
Registergericht München, HRB Nr. 43632
xen/arch/x86/apic.c +9 -0
diff -r e6f751ed8e38 xen/arch/x86/apic.c
@@ -209,6 +209,11 @@ void clear_local_APIC(void)
      */
     v = apic_read(APIC_LVTT);
     apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
+
+    /* Workaround AMD Erratum 411. Please refer to AMD
+    revision guide for more details. */
+    apic_write_around(APIC_TMICT, 0x0);
+
     v = apic_read(APIC_LVT0);
     apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
     v = apic_read(APIC_LVT1);

@@ -1187,6 +1192,10 @@ void disable_APIC_timer(void)
         
         v = apic_read(APIC_LVTT);
         apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
+
+        /* Workaround AMD Erratum 411. Please refer to AMD
+        revision guide for more details. */
+        apic_write_around(APIC_TMICT, 0x0);
     }
 }

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#1 lore raw

I don't think we are susceptible to this bug, but it's probably a nice thing to do anyway. I will apply some variant of it to xen-unstable at least.

-- Keir

Quoted 11 lines · On 04/06/2010 12:33, "Wei Wang2" <[email protected]> wrote:

Hi,
This patch is a workaround of AMD erratum 411 for family 10h CPUs. This does not cause functional issues but may reduce the power saving effectiveness of message-triggered C1e mode. This would normally occur only if OS which has used the local APIC timer masks the interrupt without clearing Timer Initial Count Register.

Thanks,
Wei

Signed-off-by Wei Wang <[email protected]>