arm: aspeed: zaius: Disable LPC reset for UART1
Subsystems (3)
PATCH 1/1 arm: aspeed: zaius: Disable LPC reset for UART1
Currently, UART1 on Zaius BMC is unusable until brought out of reset by powering the host on. In this reset state, ttyS0 can still be opened and UART1 silently drops bytes, which is not obviously expected behavior.
--- arch/arm/mach-aspeed/aspeed.c | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/mach-aspeed/aspeed.c +4 -0
@@ -185,6 +185,10 @@ static void __init do_zaius_setup(void)/* Set SPI1 CE0 decoding window to 0x30000000 */ writel (0x68600000 ,AST_IO (AST_BASE_SPI |0x30 )); + +/* Disable LPC reset for UART1 */ + reg =readl (AST_IO (AST_BASE_LPC |0x98 )); +writel (reg & ~BIT (4 ),AST_IO (AST_BASE_LPC |0x98 )); }static void __init do_witherspoon_setup (void )
Signature · 1 line
2.11.0.483.g087da7b7c-goog
From the patch, I can't tell what your change is doing. You've described the problem but not the solution.
Quoted 33 lines · Xo Wang
Currently, UART1 on Zaius BMC is unusable until brought out of reset by powering the host on. In this reset state, ttyS0 can still be opened and UART1 silently drops bytes, which is not obviously expected behavior.
Signed-off-by Xo Wang <[email protected]--- arch/arm/mach-aspeed/aspeed.c | 4 ++++ 1 file changed, 4 insertions(+)arch/arm/mach-aspeed/aspeed.c +4
-1@@ -185,6 +185,10 @@ static void __init do_zaius_setup(void)/* Set SPI1 CE0 decoding window to 0x30000000 */ writel (0x68600000 ,AST_IO (AST_BASE_SPI |0x30 )); + +/* Disable LPC reset for UART1 */ + reg =readl (AST_IO (AST_BASE_LPC |0x98 )); +writel (reg & ~BIT (4 ),AST_IO (AST_BASE_LPC |0x98 )); }static void __init do_witherspoon_setup (void ) --2.11.0.483.g087da7b7c-goog
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Heh, that's fair. I guess the code is an opaque block of bit twiddling.
Please take a look at v2.
Quoted 39 lines · Rick Altherr
From the patch, I can't tell what your change is doing. You've described the problem but not the solution.
Quoted 33 lines · Xo Wang
Currently, UART1 on Zaius BMC is unusable until brought out of reset by powering the host on. In this reset state, ttyS0 can still be opened and UART1 silently drops bytes, which is not obviously expected behavior.
Signed-off-by Xo Wang <[email protected]--- arch/arm/mach-aspeed/aspeed.c | 4 ++++ 1 file changed, 4 insertions(+)arch/arm/mach-aspeed/aspeed.c +4
-1@@ -185,6 +185,10 @@ static void __init do_zaius_setup(void)/* Set SPI1 CE0 decoding window to 0x30000000 */ writel (0x68600000 ,AST_IO (AST_BASE_SPI |0x30 )); + +/* Disable LPC reset for UART1 */ + reg =readl (AST_IO (AST_BASE_LPC |0x98 )); +writel (reg & ~BIT (4 ),AST_IO (AST_BASE_LPC |0x98 )); }static void __init do_witherspoon_setup (void ) --2.11.0.483.g087da7b7c-goog
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