arm: aspeed: zaius: Disable LPC reset for UART1
Subsystems (3)
PATCH v2 1/1 arm: aspeed: zaius: Disable LPC reset for UART1
Currently, UART1 on Zaius BMC is unusable until brought out of reset by powering the host on. In this reset state, ttyS0 can still be opened and UART1 silently drops bytes, which is not obviously expected behavior.
Clear the LPC block control bit that enables LPCRST# as a reset source for UART1.
--- arch/arm/mach-aspeed/aspeed.c | 7 +++++++ 1 file changed, 7 insertions(+)
arch/arm/mach-aspeed/aspeed.c +7 -0
@@ -185,6 +185,13 @@ static void __init do_zaius_setup(void)/* Set SPI1 CE0 decoding window to 0x30000000 */ writel (0x68600000 ,AST_IO (AST_BASE_SPI |0x30 )); + +/* Disable LPC reset for UART1, otherwise held in reset by LPCRST#, +* silently dropping bytes until released (usually by host power on) +* */ + reg =readl (AST_IO (AST_BASE_LPC |0x98 )); +/* Clear "Enable UART1 reset source from LPC" */ +writel (reg & ~BIT (4 ),AST_IO (AST_BASE_LPC |0x98 )); }static void __init do_witherspoon_setup (void )
Signature · 1 line
2.11.0.483.g087da7b7c-goog
I still don't follow. Is this changing it to drop bytes until the host powers on? Is this change making it so the device won't open?
Quoted 40 lines · Xo Wang
Currently, UART1 on Zaius BMC is unusable until brought out of reset by powering the host on. In this reset state, ttyS0 can still be opened and UART1 silently drops bytes, which is not obviously expected behavior.
Clear the LPC block control bit that enables LPCRST# as a reset source for UART1.
Signed-off-by Xo Wang <[email protected]--- arch/arm/mach-aspeed/aspeed.c | 7 +++++++ 1 file changed, 7 insertions(+)arch/arm/mach-aspeed/aspeed.c +7
-0@@ -185,6 +185,13 @@ static void __init do_zaius_setup(void)/* Set SPI1 CE0 decoding window to 0x30000000 */ writel (0x68600000 ,AST_IO (AST_BASE_SPI |0x30 )); + +/* Disable LPC reset for UART1, otherwise held in reset by LPCRST#, +* silently dropping bytes until released (usually by host power on) +* */ + reg =readl (AST_IO (AST_BASE_LPC |0x98 )); +/* Clear "Enable UART1 reset source from LPC" */ +writel (reg & ~BIT (4 ),AST_IO (AST_BASE_LPC |0x98 )); }static void
__initdo_witherspoon_setup(void)
--
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Quoted 2 lines · Rick Altherr
I still don't follow. Is this changing it to drop bytes until the host powers on? Is this change making it so the device won't open?
I understand it to be the other way around:
In the existing configuration UART1 will drop bytes by being held in reset until the host initialises the LPC bus (i.e. releases LPCRST#) during boot.
Xo's change reconfigures the SoC so that UART1 reset state doesn't depend on LPCRST# (i.e. the host initialising the LPC bus), so it is immediately useful in that it won't discard bytes.
Xo?
Andrew
Quoted 46 lines
Quoted 36 lines · Xo Wang
Currently, UART1 on Zaius BMC is unusable until brought out of reset by powering the host on. In this reset state, ttyS0 can still be opened and UART1 silently drops bytes, which is not obviously expected behavior.
Clear the LPC block control bit that enables LPCRST# as a reset source for UART1.
Signed-off-by Xo Wang <[email protected]---
arch/arm/mach-aspeed/aspeed.c | 7 +++++++1 file changed, 7 insertions(+)arch/arm/mach-aspeed/aspeed.c +7
-1@@ -185,6 +185,13 @@ static void __init do_zaius_setup(void) /* Set SPI1 CE0 decoding window to 0x30000000 */ writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30)); + + /* Disable LPC reset for UART1, otherwise held in reset by LPCRST#, + * silently dropping bytes until released (usually by host power on) + * */ + reg = readl(AST_IO(AST_BASE_LPC | 0x98)); + /* Clear "Enable UART1 reset source from LPC" */ + writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98)); } static void __init do_witherspoon_setup(void) --2.11.0.483.g087da7b7c-goog
Quoted 5 lines
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Quoted 10 lines · Andrew Jeffery
Quoted 2 lines · Rick Altherr
I still don't follow. Is this changing it to drop bytes until the host powers on? Is this change making it so the device won't open?
I understand it to be the other way around:
In the existing configuration UART1 will drop bytes by being held in reset until the host initialises the LPC bus (i.e. releases LPCRST#) during boot.
Quoted 5 lines
Xo's change reconfigures the SoC so that UART1 reset state doesn't depend on LPCRST# (i.e. the host initialising the LPC bus), so it is immediately useful in that it won't discard bytes.
Xo?
Yes, what Andrew said. It releases UART1 from being controlled by LPC reset, so that it's available regardless of the host being up.
cheers
xo
OK. I didn't get that from the commit message or comments as written.
Quoted 27 lines · Xo Wang via openbmc
Quoted 10 lines · Andrew Jeffery
Quoted 2 lines · Rick Altherr
I still don't follow. Is this changing it to drop bytes until the host powers on? Is this change making it so the device won't open?
I understand it to be the other way around:
In the existing configuration UART1 will drop bytes by being held in reset until the host initialises the LPC bus (i.e. releases LPCRST#) during boot.
Quoted 5 lines
Xo's change reconfigures the SoC so that UART1 reset state doesn't depend on LPCRST# (i.e. the host initialising the LPC bus), so it is immediately useful in that it won't discard bytes.
Xo?
Yes, what Andrew said. It releases UART1 from being controlled by LPC reset, so that it's available regardless of the host being up.
cheers
xo
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