Fix H-PLL and M-PLL clock rate calculation in ast2500 clock driver

PATCH New Maxim Sloyko 3 participants 4 messages Jan 30, 2017 – Feb 9, 2017

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Common clk Arm/Aspeed machine support Arm/Aspeed clock support

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Maxim Sloyko

author

2017-01-30 19:35 UTC #0 lore raw

cover Fix H-PLL and M-PLL clock rate calculation in ast2500 clock driver

This is a fix to a very dumb (division by zero) mistake I made in the series where I added support for ast2500 eval board. It is not causing any problems for that board yet, because no driver requests the rate of any clock yet, but I think it's still better to fix it for this release.

Maxim Sloyko (1):
aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation

 drivers/clk/aspeed/clk_ast2500.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Signature · 1 line

2.11.0.483.g087da7b7c-goog

Maxim Sloyko

author

2017-01-30 19:35 UTC #1 lore raw

PATCH 1/1 aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation

Fix H-PLL and M-PLL rate calculation in ast2500 clock driver. Without this fix, valid setting can lead to division by zero when requesting the rate of H-PLL or M-PLL clocks.

Signed-off-by Maxim Sloyko <[email protected]>

---

---
 drivers/clk/aspeed/clk_ast2500.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/clk/aspeed/clk_ast2500.c +2 -2

index af369cc4c8..26a5e58221 100644
@@ -35,7 +35,7 @@ static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
 	const ulong post_div = (mpll_reg >> SCU_MPLL_POST_SHIFT)
 			& SCU_MPLL_POST_MASK;
 
-	return (clkin * ((num + 1) / (denum + 1))) / post_div;
+	return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
 }
 
 /*

@@ -50,7 +50,7 @@ static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
 	const ulong post_div = (hpll_reg >> SCU_HPLL_POST_SHIFT)
 			& SCU_HPLL_POST_MASK;
 
-	return (clkin * ((num + 1) / (denum + 1))) / post_div;
+	return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
 }
 
 static ulong ast2500_get_clkin(struct ast2500_scu *scu)

Signature · 1 line

2.11.0.483.g087da7b7c-goog

Simon Glass

2017-02-05 03:34 UTC #2 lore raw

PATCH 1/1 aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation

Quoted 6 lines · Maxim Sloyko

Fix H-PLL and M-PLL rate calculation in ast2500 clock driver. Without this fix, valid setting can lead to division by zero when requesting the rate of H-PLL or M-PLL clocks.
Signed-off-by Maxim Sloyko <[email protected]>

Reviewed-by Simon Glass <[email protected]>

Tom Rini

2017-02-09 03:01 UTC #3 lore raw

PATCH 1/1 aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation

In reply to Maxim Sloyko

Quoted 6 lines · maxims at google.com

Fix H-PLL and M-PLL rate calculation in ast2500 clock driver. Without this fix, valid setting can lead to division by zero when requesting the rate of H-PLL or M-PLL clocks.
Signed-off-by Maxim Sloyko <[email protected]>
Reviewed-by Simon Glass <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines

Tom
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