Mark legacy/PCIe/hybrid PCI devices using interface names

Those two interfaces will be used to indicate which device types support legacy PCI or PCI-express buses. Management software will be able to use the qom-list-types QMP command to query that information.

Signed-off-by Eduardo Habkost <[email protected]>

---
 include/hw/pci/pci.h |  6 ++++++
 hw/pci/pci.c         | 12 ++++++++++++
 2 files changed, 18 insertions(+)

include/hw/pci/pci.h +6 -0

index e598b09..f5e8ab9 100644
@@ -195,6 +195,12 @@ enum {
 #define PCI_DEVICE_GET_CLASS(obj) \
      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 
+/* Interface implemented by devices that can be plugged on PCIe buses */
+#define INTERFACE_PCIE_DEVICE "pci-express-device"
+
+/* Interface implemented by devices that can be plugged on legacy PCI buses */
+#define INTERFACE_LEGACY_PCI_DEVICE "legacy-pci-device"
+
 typedef struct PCIINTxRoute {
     enum {
         PCI_INTX_ENABLED,

hw/pci/pci.c +12 -1

index 258fbe5..baa3429 100644
@@ -168,6 +168,16 @@ static const TypeInfo pci_bus_info = {
     .class_init = pci_bus_class_init,
 };
 
+static const TypeInfo pcie_interface_info = {
+    .name          = INTERFACE_PCIE_DEVICE,
+    .parent        = TYPE_INTERFACE,
+};
+
+static const TypeInfo legacy_pci_interface_info = {
+    .name          = INTERFACE_LEGACY_PCI_DEVICE,
+    .parent        = TYPE_INTERFACE,
+};
+
 static const TypeInfo pcie_bus_info = {
     .name = TYPE_PCIE_BUS,
     .parent = TYPE_PCI_BUS,

@@ -2645,6 +2655,8 @@ static void pci_register_types(void)
 {
     type_register_static(&pci_bus_info);
     type_register_static(&pcie_bus_info);
+    type_register_static(&legacy_pci_interface_info);
+    type_register_static(&pcie_interface_info);
     type_register_static(&pci_device_type_info);
 }
 
--

2.9.4

Those two interfaces will be used to indicate which device types support legacy PCI or PCI-express buses. Management software will be able to use the qom-list-types QMP command to query that information.

Signed-off-by Eduardo Habkost <[email protected]>

---
 include/hw/pci/pci.h |  6 ++++++
 hw/pci/pci.c         | 12 ++++++++++++
 2 files changed, 18 insertions(+)

include/hw/pci/pci.h +6 -0

index e598b09..f5e8ab9 100644
@@ -195,6 +195,12 @@ enum {
 #define PCI_DEVICE_GET_CLASS(obj) \
      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 
+/* Interface implemented by devices that can be plugged on PCIe buses */
+#define INTERFACE_PCIE_DEVICE "pci-express-device"
+
+/* Interface implemented by devices that can be plugged on legacy PCI buses */
+#define INTERFACE_LEGACY_PCI_DEVICE "legacy-pci-device"
+
 typedef struct PCIINTxRoute {
     enum {
         PCI_INTX_ENABLED,

hw/pci/pci.c +12 -0

index 258fbe5..baa3429 100644
@@ -168,6 +168,16 @@ static const TypeInfo pci_bus_info = {
     .class_init = pci_bus_class_init,
 };
 
+static const TypeInfo pcie_interface_info = {
+    .name          = INTERFACE_PCIE_DEVICE,
+    .parent        = TYPE_INTERFACE,
+};
+
+static const TypeInfo legacy_pci_interface_info = {
+    .name          = INTERFACE_LEGACY_PCI_DEVICE,
+    .parent        = TYPE_INTERFACE,
+};
+
 static const TypeInfo pcie_bus_info = {
     .name = TYPE_PCIE_BUS,
     .parent = TYPE_PCI_BUS,

@@ -2645,6 +2655,8 @@ static void pci_register_types(void)
 {
     type_register_static(&pci_bus_info);
     type_register_static(&pcie_bus_info);
+    type_register_static(&legacy_pci_interface_info);
+    type_register_static(&pcie_interface_info);
     type_register_static(&pci_device_type_info);
 }
 

Quoted 4 lines · On Wed, 23 Aug 2017 19:14:41 -0300 Eduardo Habkost <[email protected]> wrote:

Those two interfaces will be used to indicate which device types support legacy PCI or PCI-express buses. Management software will be able to use the qom-list-types QMP command to query that information.

Nit, while "legacy PCI" and "conventional PCI" have about the same number of google hits, I believe the latter is the more correct term. The quality of hits is certainly a lot better with "conventional". Calling something "legacy" also spurs an immediate negative reaction for some folks, "conventional" is more neutral. Thanks,

The following devices support both PCIe and legacy PCI, by including special code to handle the QEMU_PCI_CAP_EXPRESS flag:

* vfio-pci (is_express=1, but legacy PCI handled by vfio_populate_device())
* vmxnet3 (is_express=0, but PCIe handled by vmxnet3_realize())
* pvscsi (is_express=0, but PCIe handled by pvscsi_realize())
* virtio-pci (is_express=0, but PCIe handled by virtio_pci_dc_realize(), and additional legacy PCI code at virtio_pci_realize())

Signed-off-by Eduardo Habkost <[email protected]>

---
 hw/net/vmxnet3.c       | 5 +++++
 hw/scsi/vmw_pvscsi.c   | 2 ++
 hw/vfio/pci.c          | 5 +++++
 hw/virtio/virtio-pci.c | 5 +++++
 4 files changed, 17 insertions(+)

hw/net/vmxnet3.c +5 -0

index a19a7a3..61feacf 100644
@@ -2651,6 +2651,11 @@ static const TypeInfo vmxnet3_info = {
     .instance_size = sizeof(VMXNET3State),
     .class_init    = vmxnet3_class_init,
     .instance_init = vmxnet3_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { }
+    },
 };
 
 static void vmxnet3_register_types(void)

hw/scsi/vmw_pvscsi.c +2 -0

index 77d8b6f..40dfffa 100644
@@ -1300,6 +1300,8 @@ static const TypeInfo pvscsi_info = {
     .class_init    = pvscsi_class_init,
     .interfaces = (InterfaceInfo[]) {
         { TYPE_HOTPLUG_HANDLER },
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
         { }
     }
 };

hw/vfio/pci.c +5 -0

index 31e1edf..2b21391 100644
@@ -3023,6 +3023,11 @@ static const TypeInfo vfio_pci_dev_info = {
     .class_init = vfio_pci_dev_class_init,
     .instance_init = vfio_instance_init,
     .instance_finalize = vfio_instance_finalize,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { }
+    },
 };
 
 static void register_vfio_pci_dev_type(void)

hw/virtio/virtio-pci.c +5 -0

index 8b0d6b6..8c0b6bf 100644
@@ -1958,6 +1958,11 @@ static const TypeInfo virtio_pci_info = {
     .class_init    = virtio_pci_class_init,
     .class_size    = sizeof(VirtioPCIClass),
     .abstract      = true,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { }
+    },
 };
 
 /* virtio-blk-pci */

Signature · 1 line

2.9.4

Quoted 10 lines · Eduardo Habkost

The following devices support both PCIe and legacy PCI, by including special code to handle the QEMU_PCI_CAP_EXPRESS flag:

* vfio-pci (is_express=1, but legacy PCI handled by vfio_populate_device())
* vmxnet3 (is_express=0, but PCIe handled by vmxnet3_realize())
* pvscsi (is_express=0, but PCIe handled by pvscsi_realize())
* virtio-pci (is_express=0, but PCIe handled by virtio_pci_dc_realize(), and additional legacy PCI code at virtio_pci_realize())

Oh, the rules are even messier than that: QEMU_PCI_CAP_EXPRESS controls _some_ of the code that makes a device become a PCI Express device, but not every case.

In addition to vmxnet3, pvscsi and virtio-pci, PCIe caps initialization is conditional on hcd-xhci (see below).

This means xhci is also a hybrid device. But it doesn't seem to clear QEMU_PCI_CAP_EXPRESS. Doesn't it mean pci_config_size() is broken if xhci is plugged to a legacy PCI bus? How does it affect migration?

Full list of pci_endpoint_cap*_init() calls:

hw/usb/hcd-xhci.c- if (pci_bus_is_express(dev->bus) ||
hw/usb/hcd-xhci.c- xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) {
hw/usb/hcd-xhci.c: ret = pcie_endpoint_cap_init(dev, 0xa0);

hw/net/vmxnet3.c- if (pci_is_express(pci_dev)) {
hw/net/vmxnet3.c- if (pci_bus_is_express(pci_dev->bus)) {
hw/net/vmxnet3.c: pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET);
hw/net/vmxnet3.c- }

hw/scsi/megasas.c- if (pci_is_express(dev)) {
hw/scsi/megasas.c: pcie_endpoint_cap_init(dev, 0xa0);
hw/scsi/megasas.c- }

hw/scsi/vmw_pvscsi.c- if (pci_is_express(pci_dev) && pci_bus_is_express(pci_dev->bus)) {
hw/scsi/vmw_pvscsi.c: pcie_endpoint_cap_init(pci_dev, PVSCSI_EXP_EP_OFFSET);
hw/scsi/vmw_pvscsi.c- }

hw/virtio/virtio-pci.c- if (pcie_port && pci_is_express(pci_dev)) {
hw/virtio/virtio-pci.c- int pos;
hw/virtio/virtio-pci.c-
hw/virtio/virtio-pci.c: pos = pcie_endpoint_cap_init(pci_dev, 0);

Note: on megasas, pci_endpoitn_cap_init() is conditional on pci_is_express(), but pci_is_express() will never be false on megasas-gen2 (because QEMU_PCI_CAP_EXPRESS is always set).

Full list of unconditional pci_endpoint_cap*init() calls:

hw/block/nvme.c: pcie_endpoint_cap_init(&n->parent_obj, 0x80);

hw/net/e1000e.c: if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) {

hw/pci-bridge/pcie_root_port.c: rc = pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT,
hw/pci-bridge/pcie_root_port.c- p->port, errp);

hw/pci-bridge/xio3130_downstream.c: rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
hw/pci-bridge/xio3130_downstream.c- p->port, errp);

hw/pci-bridge/xio3130_upstream.c: rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,
hw/pci-bridge/xio3130_upstream.c- p->port, errp);

hw/pci-host/xilinx-pcie.c: if (pcie_endpoint_cap_v1_init(dev, 0x80) < 0) {

Quoted 74 lines

Signed-off-by Eduardo Habkost <[email protected]>

---
  hw/net/vmxnet3.c       | 5 +++++
  hw/scsi/vmw_pvscsi.c   | 2 ++
  hw/vfio/pci.c          | 5 +++++
  hw/virtio/virtio-pci.c | 5 +++++
  4 files changed, 17 insertions(+)

hw/net/vmxnet3.c +5 -0

index a19a7a3..61feacf 100644
@@ -2651,6 +2651,11 @@ static const TypeInfo vmxnet3_info = {
      .instance_size = sizeof(VMXNET3State),
      .class_init    = vmxnet3_class_init,
      .instance_init = vmxnet3_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { }
+    },
  };
 
  static void vmxnet3_register_types(void)

hw/scsi/vmw_pvscsi.c +2 -0

index 77d8b6f..40dfffa 100644
@@ -1300,6 +1300,8 @@ static const TypeInfo pvscsi_info = {
      .class_init    = pvscsi_class_init,
      .interfaces = (InterfaceInfo[]) {
          { TYPE_HOTPLUG_HANDLER },
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
          { }
      }
  };

hw/vfio/pci.c +5 -0

index 31e1edf..2b21391 100644
@@ -3023,6 +3023,11 @@ static const TypeInfo vfio_pci_dev_info = {
      .class_init = vfio_pci_dev_class_init,
      .instance_init = vfio_instance_init,
      .instance_finalize = vfio_instance_finalize,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { }
+    },
  };
 
  static void register_vfio_pci_dev_type(void)

hw/virtio/virtio-pci.c +5 -0

index 8b0d6b6..8c0b6bf 100644
@@ -1958,6 +1958,11 @@ static const TypeInfo virtio_pci_info = {
      .class_init    = virtio_pci_class_init,
      .class_size    = sizeof(VirtioPCIClass),
      .abstract      = true,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { }
+    },
  };
 
  /* virtio-blk-pci */

Signature · 1 line

2.9.4

Hi Eduardo,

Quoted 19 lines · Eduardo Habkost

Quoted 10 lines · Eduardo Habkost

The following devices support both PCIe and legacy PCI, by including special code to handle the QEMU_PCI_CAP_EXPRESS flag:

* vfio-pci (is_express=1, but legacy PCI handled by vfio_populate_device())
* vmxnet3 (is_express=0, but PCIe handled by vmxnet3_realize())
* pvscsi (is_express=0, but PCIe handled by pvscsi_realize())
* virtio-pci (is_express=0, but PCIe handled by virtio_pci_dc_realize(), and additional legacy PCI code at virtio_pci_realize())

Oh, the rules are even messier than that: QEMU_PCI_CAP_EXPRESS controls _some_ of the code that makes a device become a PCI Express device, but not every case.

In addition to vmxnet3, pvscsi and virtio-pci, PCIe caps initialization is conditional on hcd-xhci (see below).

Quoted 5 lines

This means xhci is also a hybrid device. But it doesn't seem to clear QEMU_PCI_CAP_EXPRESS. Doesn't it mean pci_config_size() is broken if xhci is plugged to a legacy PCI bus? How does it affect migration?

If this is the case we reserve more config space than needed. Other than wasted space it should be OK, including migration.

The following devices support both PCIe and legacy PCI, by including special code to handle the QEMU_PCI_CAP_EXPRESS flag:

* vfio-pci (is_express=1, but legacy PCI handled by vfio_populate_device())
* vmxnet3 (is_express=0, but PCIe handled by vmxnet3_realize())
* pvscsi (is_express=0, but PCIe handled by pvscsi_realize())
* virtio-pci (is_express=0, but PCIe handled by virtio_pci_dc_realize(), and additional legacy PCI code at virtio_pci_realize())

Signed-off-by Eduardo Habkost <[email protected]>

---
 hw/net/vmxnet3.c       | 5 +++++
 hw/scsi/vmw_pvscsi.c   | 2 ++
 hw/vfio/pci.c          | 5 +++++
 hw/virtio/virtio-pci.c | 5 +++++
 4 files changed, 17 insertions(+)

hw/net/vmxnet3.c +5 -0

index a19a7a3..61feacf 100644
@@ -2651,6 +2651,11 @@ static const TypeInfo vmxnet3_info = {
     .instance_size = sizeof(VMXNET3State),
     .class_init    = vmxnet3_class_init,
     .instance_init = vmxnet3_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { }
+    },
 };
 
 static void vmxnet3_register_types(void)

hw/scsi/vmw_pvscsi.c +2 -0

index 77d8b6f..40dfffa 100644
@@ -1300,6 +1300,8 @@ static const TypeInfo pvscsi_info = {
     .class_init    = pvscsi_class_init,
     .interfaces = (InterfaceInfo[]) {
         { TYPE_HOTPLUG_HANDLER },
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
         { }
     }
 };

hw/vfio/pci.c +5 -0

index 31e1edf..2b21391 100644
@@ -3023,6 +3023,11 @@ static const TypeInfo vfio_pci_dev_info = {
     .class_init = vfio_pci_dev_class_init,
     .instance_init = vfio_instance_init,
     .instance_finalize = vfio_instance_finalize,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { }
+    },
 };
 
 static void register_vfio_pci_dev_type(void)

hw/virtio/virtio-pci.c +5 -0

index 8b0d6b6..8c0b6bf 100644
@@ -1958,6 +1958,11 @@ static const TypeInfo virtio_pci_info = {
     .class_init    = virtio_pci_class_init,
     .class_size    = sizeof(VirtioPCIClass),
     .abstract      = true,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { }
+    },
 };
 
 /* virtio-blk-pci */

Signature · 1 line

2.9.4

The following devices support both PCIe and legacy PCI, by including special code to handle the QEMU_PCI_CAP_EXPRESS flag:

* vfio-pci (is_express=1, but legacy PCI handled by vfio_populate_device())
* vmxnet3 (is_express=0, but PCIe handled by vmxnet3_realize())
* pvscsi (is_express=0, but PCIe handled by pvscsi_realize())
* virtio-pci (is_express=0, but PCIe handled by virtio_pci_dc_realize(), and additional legacy PCI code at virtio_pci_realize())

Signed-off-by Eduardo Habkost <[email protected]>

---
  hw/net/vmxnet3.c       | 5 +++++
  hw/scsi/vmw_pvscsi.c   | 2 ++
  hw/vfio/pci.c          | 5 +++++
  hw/virtio/virtio-pci.c | 5 +++++
  4 files changed, 17 insertions(+)

hw/net/vmxnet3.c +5 -0

index a19a7a3..61feacf 100644
@@ -2651,6 +2651,11 @@ static const TypeInfo vmxnet3_info = {
      .instance_size = sizeof(VMXNET3State),
      .class_init    = vmxnet3_class_init,
      .instance_init = vmxnet3_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { }
+    },
  };
 
  static void vmxnet3_register_types(void)

hw/scsi/vmw_pvscsi.c +2 -0

index 77d8b6f..40dfffa 100644
@@ -1300,6 +1300,8 @@ static const TypeInfo pvscsi_info = {
      .class_init    = pvscsi_class_init,
      .interfaces = (InterfaceInfo[]) {
          { TYPE_HOTPLUG_HANDLER },
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
          { }
      }
  };

hw/vfio/pci.c +5 -0

index 31e1edf..2b21391 100644
@@ -3023,6 +3023,11 @@ static const TypeInfo vfio_pci_dev_info = {
      .class_init = vfio_pci_dev_class_init,
      .instance_init = vfio_instance_init,
      .instance_finalize = vfio_instance_finalize,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { }
+    },
  };
 
  static void register_vfio_pci_dev_type(void)

hw/virtio/virtio-pci.c +5 -0

index 8b0d6b6..8c0b6bf 100644
@@ -1958,6 +1958,11 @@ static const TypeInfo virtio_pci_info = {
      .class_init    = virtio_pci_class_init,
      .class_size    = sizeof(VirtioPCIClass),
      .abstract      = true,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { }
+    },
  };
 
  /* virtio-blk-pci */

Quoted 11 lines · Eduardo Habkost

The following devices support both PCIe and legacy PCI, by including special code to handle the QEMU_PCI_CAP_EXPRESS flag:

* vfio-pci (is_express=1, but legacy PCI handled by vfio_populate_device())
* vmxnet3 (is_express=0, but PCIe handled by vmxnet3_realize())
* pvscsi (is_express=0, but PCIe handled by pvscsi_realize())
* virtio-pci (is_express=0, but PCIe handled by virtio_pci_dc_realize(), and additional legacy PCI code at virtio_pci_realize())

Hi Eduardo,

We also have a "hybrid" USB controller (not sure which one :)).

Thanks,
Marcel

Quoted 67 lines

Signed-off-by Eduardo Habkost <[email protected]>

---
  hw/net/vmxnet3.c       | 5 +++++
  hw/scsi/vmw_pvscsi.c   | 2 ++
  hw/vfio/pci.c          | 5 +++++
  hw/virtio/virtio-pci.c | 5 +++++
  4 files changed, 17 insertions(+)

hw/net/vmxnet3.c +5 -0

index a19a7a3..61feacf 100644
@@ -2651,6 +2651,11 @@ static const TypeInfo vmxnet3_info = {
      .instance_size = sizeof(VMXNET3State),
      .class_init    = vmxnet3_class_init,
      .instance_init = vmxnet3_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { }
+    },
  };
  static void vmxnet3_register_types(void)

hw/scsi/vmw_pvscsi.c +2 -0

index 77d8b6f..40dfffa 100644
@@ -1300,6 +1300,8 @@ static const TypeInfo pvscsi_info = {
      .class_init    = pvscsi_class_init,
      .interfaces = (InterfaceInfo[]) {
          { TYPE_HOTPLUG_HANDLER },
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
          { }
      }
  };

hw/vfio/pci.c +5 -0

index 31e1edf..2b21391 100644
@@ -3023,6 +3023,11 @@ static const TypeInfo vfio_pci_dev_info = {
      .class_init = vfio_pci_dev_class_init,
      .instance_init = vfio_instance_init,
      .instance_finalize = vfio_instance_finalize,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { }
+    },
  };
  static void register_vfio_pci_dev_type(void)

hw/virtio/virtio-pci.c +5 -0

index 8b0d6b6..8c0b6bf 100644
@@ -1958,6 +1958,11 @@ static const TypeInfo virtio_pci_info = {
      .class_init    = virtio_pci_class_init,
      .class_size    = sizeof(VirtioPCIClass),
      .abstract      = true,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { }
+    },
  };
  /* virtio-blk-pci */
 

Change all devices that set is_express=1 to implement INTERFACE_PCIE_DEVICE.

Signed-off-by Eduardo Habkost <[email protected]>

---
 hw/block/nvme.c                    | 4 ++++
 hw/net/e1000e.c                    | 4 ++++
 hw/pci-bridge/pcie_root_port.c     | 4 ++++
 hw/pci-bridge/xio3130_downstream.c | 4 ++++
 hw/pci-bridge/xio3130_upstream.c   | 4 ++++
 hw/pci-host/xilinx-pcie.c          | 4 ++++
 hw/scsi/megasas.c                  | 6 ++++++
 hw/usb/hcd-xhci.c                  | 4 ++++
 8 files changed, 34 insertions(+)

hw/block/nvme.c +4 -0

index 6071dc1..26d58b6 100644
@@ -1110,6 +1110,10 @@ static const TypeInfo nvme_info = {
     .instance_size = sizeof(NvmeCtrl),
     .class_init    = nvme_class_init,
     .instance_init = nvme_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
 };
 
 static void nvme_register_types(void)

hw/net/e1000e.c +4 -0

index 6c42b44..81f7934 100644
@@ -708,6 +708,10 @@ static const TypeInfo e1000e_info = {
     .instance_size = sizeof(E1000EState),
     .class_init = e1000e_class_init,
     .instance_init = e1000e_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
 };
 
 static void e1000e_register_types(void)

hw/pci-bridge/pcie_root_port.c +4 -0

index 4d588cb..9b6e4ce 100644
@@ -161,6 +161,10 @@ static const TypeInfo rp_info = {
     .class_init    = rp_class_init,
     .abstract      = true,
     .class_size = sizeof(PCIERootPortClass),
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
 };
 
 static void rp_register_types(void)

hw/pci-bridge/xio3130_downstream.c +4 -0

index e706f36..7d2f762 100644
@@ -195,6 +195,10 @@ static const TypeInfo xio3130_downstream_info = {
     .name          = "xio3130-downstream",
     .parent        = TYPE_PCIE_SLOT,
     .class_init    = xio3130_downstream_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
 };
 
 static void xio3130_downstream_register_types(void)

hw/pci-bridge/xio3130_upstream.c +4 -0

index a052224..227997c 100644
@@ -166,6 +166,10 @@ static const TypeInfo xio3130_upstream_info = {
     .name          = "x3130-upstream",
     .parent        = TYPE_PCIE_PORT,
     .class_init    = xio3130_upstream_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
 };
 
 static void xio3130_upstream_register_types(void)

hw/pci-host/xilinx-pcie.c +4 -0

index 4613dda..7659253 100644
@@ -317,6 +317,10 @@ static const TypeInfo xilinx_pcie_root_info = {
     .parent = TYPE_PCI_BRIDGE,
     .instance_size = sizeof(XilinxPCIERoot),
     .class_init = xilinx_pcie_root_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
 };
 
 static void xilinx_pcie_register(void)

hw/scsi/megasas.c +6 -0

index 734fdae..3641c30 100644
@@ -2451,6 +2451,7 @@ typedef struct MegasasInfo {
     int osts;
     const VMStateDescription *vmsd;
     Property *props;
+    InterfaceInfo *interfaces;
 } MegasasInfo;
 
 static struct MegasasInfo megasas_devices[] = {

@@ -2480,6 +2481,10 @@ static struct MegasasInfo megasas_devices[] = {
         .is_express = true,
         .vmsd = &vmstate_megasas_gen2,
         .props = megasas_properties_gen2,
+        .interfaces = (InterfaceInfo[]) {
+            { INTERFACE_PCIE_DEVICE },
+            { }
+        },
     }
 };
 

@@ -2531,6 +2536,7 @@ static void megasas_register_types(void)
         type_info.parent = TYPE_MEGASAS_BASE;
         type_info.class_data = (void *)info;
         type_info.class_init = megasas_class_init;
+        type_info.interfaces = info->interfaces;
 
         type_register(&type_info);
     }

hw/usb/hcd-xhci.c +4 -1

index 204ea69..d95ed4f 100644
@@ -3670,6 +3670,10 @@ static const TypeInfo xhci_info = {
     .instance_size = sizeof(XHCIState),
     .class_init    = xhci_class_init,
     .abstract      = true,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
 };
 
 static void qemu_xhci_class_init(ObjectClass *klass, void *data)
--

2.9.4

Change all devices that set is_express=1 to implement INTERFACE_PCIE_DEVICE.

Signed-off-by Eduardo Habkost <[email protected]>

---
 hw/block/nvme.c                    | 4 ++++
 hw/net/e1000e.c                    | 4 ++++
 hw/pci-bridge/pcie_root_port.c     | 4 ++++
 hw/pci-bridge/xio3130_downstream.c | 4 ++++
 hw/pci-bridge/xio3130_upstream.c   | 4 ++++
 hw/pci-host/xilinx-pcie.c          | 4 ++++
 hw/scsi/megasas.c                  | 6 ++++++
 hw/usb/hcd-xhci.c                  | 4 ++++
 8 files changed, 34 insertions(+)

hw/block/nvme.c +4 -0

index 6071dc1..26d58b6 100644
@@ -1110,6 +1110,10 @@ static const TypeInfo nvme_info = {
     .instance_size = sizeof(NvmeCtrl),
     .class_init    = nvme_class_init,
     .instance_init = nvme_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
 };
 
 static void nvme_register_types(void)

hw/net/e1000e.c +4 -0

index 6c42b44..81f7934 100644
@@ -708,6 +708,10 @@ static const TypeInfo e1000e_info = {
     .instance_size = sizeof(E1000EState),
     .class_init = e1000e_class_init,
     .instance_init = e1000e_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
 };
 
 static void e1000e_register_types(void)

hw/pci-bridge/pcie_root_port.c +4 -0

index 4d588cb..9b6e4ce 100644
@@ -161,6 +161,10 @@ static const TypeInfo rp_info = {
     .class_init    = rp_class_init,
     .abstract      = true,
     .class_size = sizeof(PCIERootPortClass),
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
 };
 
 static void rp_register_types(void)

hw/pci-bridge/xio3130_downstream.c +4 -0

index e706f36..7d2f762 100644
@@ -195,6 +195,10 @@ static const TypeInfo xio3130_downstream_info = {
     .name          = "xio3130-downstream",
     .parent        = TYPE_PCIE_SLOT,
     .class_init    = xio3130_downstream_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
 };
 
 static void xio3130_downstream_register_types(void)

hw/pci-bridge/xio3130_upstream.c +4 -0

index a052224..227997c 100644
@@ -166,6 +166,10 @@ static const TypeInfo xio3130_upstream_info = {
     .name          = "x3130-upstream",
     .parent        = TYPE_PCIE_PORT,
     .class_init    = xio3130_upstream_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
 };
 
 static void xio3130_upstream_register_types(void)

hw/pci-host/xilinx-pcie.c +4 -0

index 4613dda..7659253 100644
@@ -317,6 +317,10 @@ static const TypeInfo xilinx_pcie_root_info = {
     .parent = TYPE_PCI_BRIDGE,
     .instance_size = sizeof(XilinxPCIERoot),
     .class_init = xilinx_pcie_root_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
 };
 
 static void xilinx_pcie_register(void)

hw/scsi/megasas.c +6 -0

index 734fdae..3641c30 100644
@@ -2451,6 +2451,7 @@ typedef struct MegasasInfo {
     int osts;
     const VMStateDescription *vmsd;
     Property *props;
+    InterfaceInfo *interfaces;
 } MegasasInfo;
 
 static struct MegasasInfo megasas_devices[] = {

@@ -2480,6 +2481,10 @@ static struct MegasasInfo megasas_devices[] = {
         .is_express = true,
         .vmsd = &vmstate_megasas_gen2,
         .props = megasas_properties_gen2,
+        .interfaces = (InterfaceInfo[]) {
+            { INTERFACE_PCIE_DEVICE },
+            { }
+        },
     }
 };
 

@@ -2531,6 +2536,7 @@ static void megasas_register_types(void)
         type_info.parent = TYPE_MEGASAS_BASE;
         type_info.class_data = (void *)info;
         type_info.class_init = megasas_class_init;
+        type_info.interfaces = info->interfaces;
 
         type_register(&type_info);
     }

hw/usb/hcd-xhci.c +4 -0

index 204ea69..d95ed4f 100644
@@ -3670,6 +3670,10 @@ static const TypeInfo xhci_info = {
     .instance_size = sizeof(XHCIState),
     .class_init    = xhci_class_init,
     .abstract      = true,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
 };
 
 static void qemu_xhci_class_init(ObjectClass *klass, void *data)

Signature · 1 line

2.9.4

Change all devices that set is_express=1 to implement INTERFACE_PCIE_DEVICE.

Signed-off-by Eduardo Habkost <[email protected]>

---
  hw/block/nvme.c                    | 4 ++++
  hw/net/e1000e.c                    | 4 ++++
  hw/pci-bridge/pcie_root_port.c     | 4 ++++
  hw/pci-bridge/xio3130_downstream.c | 4 ++++
  hw/pci-bridge/xio3130_upstream.c   | 4 ++++
  hw/pci-host/xilinx-pcie.c          | 4 ++++
  hw/scsi/megasas.c                  | 6 ++++++
  hw/usb/hcd-xhci.c                  | 4 ++++
  8 files changed, 34 insertions(+)

hw/block/nvme.c +4 -0

index 6071dc1..26d58b6 100644
@@ -1110,6 +1110,10 @@ static const TypeInfo nvme_info = {
      .instance_size = sizeof(NvmeCtrl),
      .class_init    = nvme_class_init,
      .instance_init = nvme_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
  };
 
  static void nvme_register_types(void)

hw/net/e1000e.c +4 -0

index 6c42b44..81f7934 100644
@@ -708,6 +708,10 @@ static const TypeInfo e1000e_info = {
      .instance_size = sizeof(E1000EState),
      .class_init = e1000e_class_init,
      .instance_init = e1000e_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
  };
 
  static void e1000e_register_types(void)

hw/pci-bridge/pcie_root_port.c +4 -0

index 4d588cb..9b6e4ce 100644
@@ -161,6 +161,10 @@ static const TypeInfo rp_info = {
      .class_init    = rp_class_init,
      .abstract      = true,
      .class_size = sizeof(PCIERootPortClass),
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
  };
 
  static void rp_register_types(void)

hw/pci-bridge/xio3130_downstream.c +4 -0

index e706f36..7d2f762 100644
@@ -195,6 +195,10 @@ static const TypeInfo xio3130_downstream_info = {
      .name          = "xio3130-downstream",
      .parent        = TYPE_PCIE_SLOT,
      .class_init    = xio3130_downstream_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
  };
 
  static void xio3130_downstream_register_types(void)

hw/pci-bridge/xio3130_upstream.c +4 -0

index a052224..227997c 100644
@@ -166,6 +166,10 @@ static const TypeInfo xio3130_upstream_info = {
      .name          = "x3130-upstream",
      .parent        = TYPE_PCIE_PORT,
      .class_init    = xio3130_upstream_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
  };
 
  static void xio3130_upstream_register_types(void)

hw/pci-host/xilinx-pcie.c +4 -0

index 4613dda..7659253 100644
@@ -317,6 +317,10 @@ static const TypeInfo xilinx_pcie_root_info = {
      .parent = TYPE_PCI_BRIDGE,
      .instance_size = sizeof(XilinxPCIERoot),
      .class_init = xilinx_pcie_root_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
  };
 
  static void xilinx_pcie_register(void)

hw/scsi/megasas.c +6 -0

index 734fdae..3641c30 100644
@@ -2451,6 +2451,7 @@ typedef struct MegasasInfo {
      int osts;
      const VMStateDescription *vmsd;
      Property *props;
+    InterfaceInfo *interfaces;
  } MegasasInfo;
 
  static struct MegasasInfo megasas_devices[] = {

@@ -2480,6 +2481,10 @@ static struct MegasasInfo megasas_devices[] = {
          .is_express = true,
          .vmsd = &vmstate_megasas_gen2,
          .props = megasas_properties_gen2,
+        .interfaces = (InterfaceInfo[]) {
+            { INTERFACE_PCIE_DEVICE },
+            { }
+        },
      }
  };
 

@@ -2531,6 +2536,7 @@ static void megasas_register_types(void)
          type_info.parent = TYPE_MEGASAS_BASE;
          type_info.class_data = (void *)info;
          type_info.class_init = megasas_class_init;
+        type_info.interfaces = info->interfaces;
 
          type_register(&type_info);
      }

hw/usb/hcd-xhci.c +4 -0

index 204ea69..d95ed4f 100644
@@ -3670,6 +3670,10 @@ static const TypeInfo xhci_info = {
      .instance_size = sizeof(XHCIState),
      .class_init    = xhci_class_init,
      .abstract      = true,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
  };
 
  static void qemu_xhci_class_init(ObjectClass *klass, void *data)

Hi Eduardo,

Quoted 3 lines · Eduardo Habkost

Change all devices that set is_express=1 to implement INTERFACE_PCIE_DEVICE.

Can this interface *replace* is_express field?

Add INTERFACE_LEGACY_PCI_DEVICE to all direct subtypes of TYPE_PCI_DEVICE, except:

1) The ones that already have INTERFACE_PCIE_DEVICE set:

* base-xhci
* e1000e
* nvme
* pvscsi
* vfio-pci
* virtio-pci
* vmxnet3

2) base-pci-bridge

Not all PCI bridges are legacy PCI devices, so INTERFACE_LEGACY_PCI_DEVICE is added only to the subtypes that are actually legacy PCI devices:

* dec-21154-p2p-bridge
* i82801b11-bridge
* pbm-bridge
* pci-bridge

The direct subtypes of base-pci-bridge not touched by this patch are:

* xilinx-pcie-root: Already marked as PCIe-only device.
* pcie-port: all non-abstract subtypes of pcie-port are already marked as PCIe-only devices.

3) megasas-base

Not all megasas devices are legacy PCI devices, so the interface names are added to the subclasses registered by megasas_register_types(), according to information in the megasas_devices[] array.

"megasas-gen2" already implements INTERFACE_PCIE_DEVICE, so add INTERFACE_LEGACY_PCI_DEVICE only to "megasas".

Signed-off-by Eduardo Habkost <[email protected]>

---
 hw/acpi/piix4.c                     |  1 +
 hw/audio/ac97.c                     |  4 ++++
 hw/audio/es1370.c                   |  4 ++++
 hw/audio/intel-hda.c                |  4 ++++
 hw/char/serial-pci.c                | 12 ++++++++++++
 hw/display/cirrus_vga.c             |  4 ++++
 hw/display/qxl.c                    |  4 ++++
 hw/display/sm501.c                  |  4 ++++
 hw/display/vga-pci.c                |  4 ++++
 hw/display/vmware_vga.c             |  4 ++++
 hw/i2c/smbus_ich9.c                 |  4 ++++
 hw/i386/amd_iommu.c                 |  4 ++++
 hw/i386/kvm/pci-assign.c            |  4 ++++
 hw/i386/pc_piix.c                   |  4 ++++
 hw/i386/xen/xen_platform.c          |  4 ++++
 hw/i386/xen/xen_pvdevice.c          |  4 ++++
 hw/ide/ich.c                        |  4 ++++
 hw/ide/pci.c                        |  4 ++++
 hw/ipack/tpci200.c                  |  4 ++++
 hw/isa/i82378.c                     |  4 ++++
 hw/isa/lpc_ich9.c                   |  1 +
 hw/isa/piix4.c                      |  4 ++++
 hw/isa/vt82c686.c                   | 16 ++++++++++++++++
 hw/mips/gt64xxx_pci.c               |  4 ++++
 hw/misc/edu.c                       |  5 +++++
 hw/misc/ivshmem.c                   |  4 ++++
 hw/misc/macio/macio.c               |  4 ++++
 hw/misc/pci-testdev.c               |  4 ++++
 hw/net/e1000.c                      |  4 ++++
 hw/net/eepro100.c                   |  4 ++++
 hw/net/ne2000.c                     |  4 ++++
 hw/net/pcnet-pci.c                  |  4 ++++
 hw/net/rocker/rocker.c              |  4 ++++
 hw/net/rtl8139.c                    |  4 ++++
 hw/pci-bridge/dec.c                 |  8 ++++++++
 hw/pci-bridge/i82801b11.c           |  4 ++++
 hw/pci-bridge/pci_bridge_dev.c      |  1 +
 hw/pci-bridge/pci_expander_bridge.c |  8 ++++++++
 hw/pci-host/apb.c                   |  8 ++++++++
 hw/pci-host/bonito.c                |  4 ++++
 hw/pci-host/gpex.c                  |  4 ++++
 hw/pci-host/grackle.c               |  4 ++++
 hw/pci-host/piix.c                  |  8 ++++++++
 hw/pci-host/ppce500.c               |  4 ++++
 hw/pci-host/prep.c                  |  4 ++++
 hw/pci-host/q35.c                   |  4 ++++
 hw/pci-host/uninorth.c              | 16 ++++++++++++++++
 hw/pci-host/versatile.c             |  4 ++++
 hw/ppc/ppc4xx_pci.c                 |  4 ++++
 hw/scsi/esp-pci.c                   |  4 ++++
 hw/scsi/lsi53c895a.c                |  4 ++++
 hw/scsi/megasas.c                   |  4 ++++
 hw/scsi/mptsas.c                    |  4 ++++
 hw/sd/sdhci.c                       |  4 ++++
 hw/sh4/sh_pci.c                     |  4 ++++
 hw/sparc64/sun4u.c                  |  4 ++++
 hw/usb/hcd-ehci-pci.c               |  4 ++++
 hw/usb/hcd-ohci.c                   |  4 ++++
 hw/usb/hcd-uhci.c                   |  4 ++++
 hw/vfio/pci-quirks.c                |  4 ++++
 hw/watchdog/wdt_i6300esb.c          |  4 ++++
 hw/xen/xen_pt.c                     |  4 ++++
 62 files changed, 288 insertions(+)

hw/acpi/piix4.c +1 -0

index f276967..defe98a 100644
@@ -723,6 +723,7 @@ static const TypeInfo piix4_pm_info = {
     .interfaces = (InterfaceInfo[]) {
         { TYPE_HOTPLUG_HANDLER },
         { TYPE_ACPI_DEVICE_IF },
+        { INTERFACE_LEGACY_PCI_DEVICE },
         { }
     }
 };

hw/audio/ac97.c +4 -0

index 959c786..6027e15 100644
@@ -1431,6 +1431,10 @@ static const TypeInfo ac97_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof (AC97LinkState),
     .class_init    = ac97_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void ac97_register_types (void)

hw/audio/es1370.c +4 -0

index dd7c23d..ed14ec3 100644
@@ -1082,6 +1082,10 @@ static const TypeInfo es1370_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof (ES1370State),
     .class_init    = es1370_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void es1370_register_types (void)

hw/audio/intel-hda.c +4 -0

index 06acc98..e2b9bf5 100644
@@ -1299,6 +1299,10 @@ static const TypeInfo intel_hda_info = {
     .instance_size = sizeof(IntelHDAState),
     .class_init    = intel_hda_class_init,
     .abstract      = true,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static const TypeInfo intel_hda_info_ich6 = {

hw/char/serial-pci.c +12 -0

index 303104d..c2dbcc0 100644
@@ -250,6 +250,10 @@ static const TypeInfo serial_pci_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCISerialState),
     .class_init    = serial_pci_class_initfn,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static const TypeInfo multi_2x_serial_pci_info = {

@@ -257,6 +261,10 @@ static const TypeInfo multi_2x_serial_pci_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIMultiSerialState),
     .class_init    = multi_2x_serial_pci_class_initfn,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static const TypeInfo multi_4x_serial_pci_info = {

@@ -264,6 +272,10 @@ static const TypeInfo multi_4x_serial_pci_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIMultiSerialState),
     .class_init    = multi_4x_serial_pci_class_initfn,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void serial_pci_register_types(void)

hw/display/cirrus_vga.c +4 -0

index afc290a..9a39fa0 100644
@@ -3162,6 +3162,10 @@ static const TypeInfo cirrus_vga_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCICirrusVGAState),
     .class_init    = cirrus_vga_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void cirrus_vga_register_types(void)

hw/display/qxl.c +4 -0

index ae3677f..1a010e8 100644
@@ -2430,6 +2430,10 @@ static const TypeInfo qxl_pci_type_info = {
     .instance_size = sizeof(PCIQXLDevice),
     .abstract = true,
     .class_init = qxl_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void qxl_primary_class_init(ObjectClass *klass, void *data)

hw/display/sm501.c +4 -0

index 9aa515b..7538f0c 100644
@@ -1843,6 +1843,10 @@ static const TypeInfo sm501_pci_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(SM501PCIState),
     .class_init    = sm501_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void sm501_register_types(void)

hw/display/vga-pci.c +4 -0

index ac9a764..72477e4 100644
@@ -338,6 +338,10 @@ static const TypeInfo vga_pci_type_info = {
     .instance_size = sizeof(PCIVGAState),
     .abstract = true,
     .class_init = vga_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void vga_class_init(ObjectClass *klass, void *data)

hw/display/vmware_vga.c +4 -0

index 4a64b41..9c2aa2d 100644
@@ -1350,6 +1350,10 @@ static const TypeInfo vmsvga_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(struct pci_vmsvga_state_s),
     .class_init    = vmsvga_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void vmsvga_register_types(void)

hw/i2c/smbus_ich9.c +4 -0

index ea51e09..83b0512 100644
@@ -119,6 +119,10 @@ static const TypeInfo ich9_smb_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(ICH9SMBState),
     .class_init = ich9_smb_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void ich9_smb_register(void)

hw/i386/amd_iommu.c +4 -0

index 334938a..471c7a9 100644
@@ -1227,6 +1227,10 @@ static const TypeInfo amdviPCI = {
     .name = "AMDVI-PCI",
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(AMDVIPCIState),
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void amdvi_iommu_memory_region_class_init(ObjectClass *klass, void *data)

hw/i386/kvm/pci-assign.c +4 -0

index 33e20cb..57800d3 100644
@@ -1864,6 +1864,10 @@ static const TypeInfo assign_info = {
     .instance_size      = sizeof(AssignedDevice),
     .class_init         = assign_class_init,
     .instance_init      = assigned_dev_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void assign_register_types(void)

hw/i386/pc_piix.c +4 -0

index 46dfd2c..eafc207 100644
@@ -1049,6 +1049,10 @@ static TypeInfo isa_bridge_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init = isa_bridge_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pt_graphics_register_types(void)

hw/i386/xen/xen_platform.c +4 -0

index 9ba7474..2113bd0 100644
@@ -517,6 +517,10 @@ static const TypeInfo xen_platform_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIXenPlatformState),
     .class_init    = xen_platform_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void xen_platform_register_types(void)

hw/i386/xen/xen_pvdevice.c +4 -0

index c093b34..e2ae81b 100644
@@ -127,6 +127,10 @@ static const TypeInfo xen_pv_type_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(XenPVDevice),
     .class_init    = xen_pv_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void xen_pv_register_types(void)

hw/ide/ich.c +4 -0

index 9472a60..0c60aa3 100644
@@ -184,6 +184,10 @@ static const TypeInfo ich_ahci_info = {
     .instance_size = sizeof(AHCIPCIState),
     .instance_init = pci_ich9_ahci_init,
     .class_init    = ich_ahci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void ich_ahci_register_types(void)

hw/ide/pci.c +4 -0

index 3cfb510..f437298 100644
@@ -458,6 +458,10 @@ static const TypeInfo pci_ide_type_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIIDEState),
     .abstract = true,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pci_ide_register_types(void)

hw/ipack/tpci200.c +4 -0

index 4dfa6b3..e380378 100644
@@ -646,6 +646,10 @@ static const TypeInfo tpci200_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(TPCI200State),
     .class_init    = tpci200_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void tpci200_register_types(void)

hw/isa/i82378.c +4 -0

index 4d29a99..13702b8 100644
@@ -138,6 +138,10 @@ static const TypeInfo i82378_type_info = {
     .instance_size = sizeof(I82378State),
     .instance_init = i82378_init,
     .class_init = i82378_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void i82378_register_types(void)

hw/isa/lpc_ich9.c +1 -0

index ac8416d..dcde152 100644
@@ -823,6 +823,7 @@ static const TypeInfo ich9_lpc_info = {
     .interfaces = (InterfaceInfo[]) {
         { TYPE_HOTPLUG_HANDLER },
         { TYPE_ACPI_DEVICE_IF },
+        { INTERFACE_LEGACY_PCI_DEVICE },
         { }
     }
 };

hw/isa/piix4.c +4 -0

index f811eba..515e55d 100644
@@ -132,6 +132,10 @@ static const TypeInfo piix4_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PIIX4State),
     .class_init    = piix4_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void piix4_register_types(void)

hw/isa/vt82c686.c +16 -0

index 50dc83d..319dc7f 100644
@@ -301,6 +301,10 @@ static const TypeInfo via_ac97_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(VT686AC97State),
     .class_init    = via_ac97_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp)

@@ -341,6 +345,10 @@ static const TypeInfo via_mc97_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(VT686MC97State),
     .class_init    = via_mc97_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 /* vt82c686 pm init */

@@ -419,6 +427,10 @@ static const TypeInfo via_pm_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(VT686PMState),
     .class_init    = via_pm_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static const VMStateDescription vmstate_via = {

@@ -502,6 +514,10 @@ static const TypeInfo via_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(VT82C686BState),
     .class_init    = via_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void vt82c686b_register_types(void)

hw/mips/gt64xxx_pci.c +4 -0

index e8b2eef..96d8cd0 100644
@@ -1232,6 +1232,10 @@ static const TypeInfo gt64120_pci_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init    = gt64120_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void gt64120_class_init(ObjectClass *klass, void *data)

hw/misc/edu.c +5 -0

index 01acacf..64b12b3 100644
@@ -408,12 +408,17 @@ static void edu_class_init(ObjectClass *class, void *data)
 
 static void pci_edu_register_types(void)
 {
+    static InterfaceInfo interfaces[] = {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    };
     static const TypeInfo edu_info = {
         .name          = "edu",
         .parent        = TYPE_PCI_DEVICE,
         .instance_size = sizeof(EduState),
         .instance_init = edu_instance_init,
         .class_init    = edu_class_init,
+        .interfaces = interfaces,
     };
 
     type_register_static(&edu_info);

hw/misc/ivshmem.c +4 -0

index 47a015f..da63c90 100644
@@ -1010,6 +1010,10 @@ static const TypeInfo ivshmem_common_info = {
     .instance_size = sizeof(IVShmemState),
     .abstract      = true,
     .class_init    = ivshmem_common_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static const VMStateDescription ivshmem_plain_vmsd = {

hw/misc/macio/macio.c +4 -0

index 5d57f45..fa163e3 100644
@@ -415,6 +415,10 @@ static const TypeInfo macio_type_info = {
     .instance_init = macio_instance_init,
     .abstract      = true,
     .class_init    = macio_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void macio_register_types(void)

hw/misc/pci-testdev.c +4 -0

index 7d59902..992157f 100644
@@ -326,6 +326,10 @@ static const TypeInfo pci_testdev_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCITestDevState),
     .class_init    = pci_testdev_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pci_testdev_register_types(void)

hw/net/e1000.c +4 -0

index f2e5072..51ab83d 100644
@@ -1685,6 +1685,10 @@ static const TypeInfo e1000_base_info = {
     .instance_init = e1000_instance_init,
     .class_size    = sizeof(E1000BaseClass),
     .abstract      = true,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static const E1000Info e1000_devices[] = {

hw/net/eepro100.c +4 -0

index 5a4774a..8f5c567 100644
@@ -2117,6 +2117,10 @@ static void eepro100_register_types(void)
         type_info.class_init = eepro100_class_init;
         type_info.instance_size = sizeof(EEPRO100State);
         type_info.instance_init = eepro100_instance_init;
+        type_info.interfaces = (InterfaceInfo[]) {
+            { INTERFACE_LEGACY_PCI_DEVICE },
+            { },
+        };
 
         type_register(&type_info);
     }

hw/net/ne2000.c +4 -0

index 798d681..fce3420 100644
@@ -786,6 +786,10 @@ static const TypeInfo ne2000_info = {
     .instance_size = sizeof(PCINE2000State),
     .class_init    = ne2000_class_init,
     .instance_init = ne2000_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void ne2000_register_types(void)

hw/net/pcnet-pci.c +4 -0

index 0acf8a4..cbe6e99 100644
@@ -365,6 +365,10 @@ static const TypeInfo pcnet_info = {
     .instance_size = sizeof(PCIPCNetState),
     .class_init    = pcnet_class_init,
     .instance_init = pcnet_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pci_pcnet_register_types(void)

hw/net/rocker/rocker.c +4 -0

index 4f0f6d7..2eb53ad 100644
@@ -1573,6 +1573,10 @@ static const TypeInfo rocker_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(Rocker),
     .class_init    = rocker_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void rocker_register_types(void)

hw/net/rtl8139.c +4 -0

index 671c7e4..3371318 100644
@@ -3489,6 +3489,10 @@ static const TypeInfo rtl8139_info = {
     .instance_size = sizeof(RTL8139State),
     .class_init    = rtl8139_class_init,
     .instance_init = rtl8139_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void rtl8139_register_types(void)

hw/pci-bridge/dec.c +8 -0

index eb275e1..77a07d0 100644
@@ -79,6 +79,10 @@ static const TypeInfo dec_21154_pci_bridge_info = {
     .parent        = TYPE_PCI_BRIDGE,
     .instance_size = sizeof(PCIBridge),
     .class_init    = dec_21154_pci_bridge_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn)

@@ -138,6 +142,10 @@ static const TypeInfo dec_21154_pci_host_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init    = dec_21154_pci_host_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pci_dec_21154_device_class_init(ObjectClass *klass, void *data)

hw/pci-bridge/i82801b11.c +4 -0

index 2c1b747..baac63b 100644
@@ -106,6 +106,10 @@ static const TypeInfo i82801b11_bridge_info = {
     .parent        = TYPE_PCI_BRIDGE,
     .instance_size = sizeof(I82801b11Bridge),
     .class_init    = i82801b11_bridge_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void d2pbr_register(void)

hw/pci-bridge/pci_bridge_dev.c +1 -0

index 4373f1d..d83824b 100644
@@ -238,6 +238,7 @@ static const TypeInfo pci_bridge_dev_info = {
     .instance_finalize = pci_bridge_dev_instance_finalize,
     .interfaces = (InterfaceInfo[]) {
         { TYPE_HOTPLUG_HANDLER },
+        { INTERFACE_LEGACY_PCI_DEVICE },
         { }
     }
 };

hw/pci-bridge/pci_expander_bridge.c +8 -0

index ff59abf..cc9ec88 100644
@@ -316,6 +316,10 @@ static const TypeInfo pxb_dev_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PXBDev),
     .class_init    = pxb_dev_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pxb_pcie_dev_realize(PCIDevice *dev, Error **errp)

@@ -350,6 +354,10 @@ static const TypeInfo pxb_pcie_dev_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PXBDev),
     .class_init    = pxb_pcie_dev_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pxb_register_types(void)

hw/pci-host/apb.c +8 -0

index 96e5d0b..c2c8c6d 100644
@@ -817,6 +817,10 @@ static const TypeInfo pbm_pci_host_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init    = pbm_pci_host_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pbm_host_class_init(ObjectClass *klass, void *data)

@@ -857,6 +861,10 @@ static const TypeInfo pbm_pci_bridge_info = {
     .name          = "pbm-bridge",
     .parent        = TYPE_PCI_BRIDGE,
     .class_init    = pbm_pci_bridge_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pbm_iommu_memory_region_class_init(ObjectClass *klass, void *data)

hw/pci-host/bonito.c +4 -0

index 89133a9..f037378 100644
@@ -833,6 +833,10 @@ static const TypeInfo bonito_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIBonitoState),
     .class_init    = bonito_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void bonito_pcihost_class_init(ObjectClass *klass, void *data)

hw/pci-host/gpex.c +4 -0

index 83084b9..c348e84 100644
@@ -144,6 +144,10 @@ static const TypeInfo gpex_root_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(GPEXRootState),
     .class_init = gpex_root_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void gpex_register(void)

hw/pci-host/grackle.c +4 -0

index 2e281f6..01d3edc 100644
@@ -142,6 +142,10 @@ static const TypeInfo grackle_pci_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init = grackle_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pci_grackle_class_init(ObjectClass *klass, void *data)

hw/pci-host/piix.c +8 -0

index 072a04e..d35520e 100644
@@ -694,6 +694,10 @@ static const TypeInfo piix3_pci_type_info = {
     .instance_size = sizeof(PIIX3State),
     .abstract = true,
     .class_init = pci_piix3_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void piix3_class_init(ObjectClass *klass, void *data)

@@ -748,6 +752,10 @@ static const TypeInfo i440fx_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCII440FXState),
     .class_init    = i440fx_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 /* IGD Passthrough Host Bridge. */

hw/pci-host/ppce500.c +4 -0

index becc0ee..6dd66c4 100644
@@ -516,6 +516,10 @@ static const TypeInfo e500_host_bridge_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PPCE500PCIBridgeState),
     .class_init    = e500_host_bridge_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static Property pcihost_properties[] = {

hw/pci-host/prep.c +4 -0

index 8b293ba..bb19b6d 100644
@@ -372,6 +372,10 @@ static const TypeInfo raven_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(RavenPCIState),
     .class_init = raven_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static Property raven_pcihost_properties[] = {

hw/pci-host/q35.c +4 -0

index 0e472f2..a6f93f1 100644
@@ -591,6 +591,10 @@ static const TypeInfo mch_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(MCHPCIState),
     .class_init = mch_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void q35_register(void)

hw/pci-host/uninorth.c +16 -0

index 6cf5e59..3b40a9a 100644
@@ -374,6 +374,10 @@ static const TypeInfo unin_main_pci_host_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init = unin_main_pci_host_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)

@@ -398,6 +402,10 @@ static const TypeInfo u3_agp_pci_host_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init = u3_agp_pci_host_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)

@@ -422,6 +430,10 @@ static const TypeInfo unin_agp_pci_host_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init = unin_agp_pci_host_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)

@@ -446,6 +458,10 @@ static const TypeInfo unin_internal_pci_host_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init = unin_internal_pci_host_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pci_unin_main_class_init(ObjectClass *klass, void *data)

hw/pci-host/versatile.c +4 -0

index aa1fdf7..e1ba6f4 100644
@@ -487,6 +487,10 @@ static const TypeInfo versatile_pci_host_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init    = versatile_pci_host_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static Property pci_vpb_properties[] = {

hw/ppc/ppc4xx_pci.c +4 -0

index 6953f8b..92027c3 100644
@@ -359,6 +359,10 @@ static const TypeInfo ppc4xx_host_bridge_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init    = ppc4xx_host_bridge_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)

hw/scsi/esp-pci.c +4 -0

index e295d88..2f0c659 100644
@@ -398,6 +398,10 @@ static const TypeInfo esp_pci_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIESPState),
     .class_init = esp_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 typedef struct {

hw/scsi/lsi53c895a.c +4 -0

index 3e56ab2..788bfc3 100644
@@ -2244,6 +2244,10 @@ static const TypeInfo lsi_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(LSIState),
     .class_init    = lsi_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void lsi53c810_class_init(ObjectClass *klass, void *data)

hw/scsi/megasas.c +4 -0

index 3641c30..cf69b56 100644
@@ -2468,6 +2468,10 @@ static struct MegasasInfo megasas_devices[] = {
         .is_express = false,
         .vmsd = &vmstate_megasas_gen1,
         .props = megasas_properties_gen1,
+        .interfaces = (InterfaceInfo[]) {
+            { INTERFACE_LEGACY_PCI_DEVICE },
+            { },
+        },
     },{
         .name = TYPE_MEGASAS_GEN2,
         .desc = "LSI MegaRAID SAS 2108",

hw/scsi/mptsas.c +4 -0

index 765ab53..6ff773e 100644
@@ -1441,6 +1441,10 @@ static const TypeInfo mptsas_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(MPTSASState),
     .class_init = mptsas1068_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void mptsas_register_types(void)

hw/sd/sdhci.c +4 -0

index 6d6a791..f6b18d6 100644
@@ -1315,6 +1315,10 @@ static const TypeInfo sdhci_pci_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(SDHCIState),
     .class_init = sdhci_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static Property sdhci_sysbus_properties[] = {

hw/sh4/sh_pci.c +4 -0

index 38395c0..6cec225 100644
@@ -179,6 +179,10 @@ static const TypeInfo sh_pci_host_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init    = sh_pci_host_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void sh_pci_device_class_init(ObjectClass *klass, void *data)

hw/sparc64/sun4u.c +4 -0

index bbdb40c..b2b3bab 100644
@@ -277,6 +277,10 @@ static const TypeInfo ebus_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(EbusState),
     .class_init    = ebus_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 #define TYPE_OPENPROM "openprom"

hw/usb/hcd-ehci-pci.c +4 -0

index 6dedcb8..464178d 100644
@@ -170,6 +170,10 @@ static const TypeInfo ehci_pci_type_info = {
     .instance_finalize = usb_ehci_pci_finalize,
     .abstract = true,
     .class_init = ehci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void ehci_data_class_init(ObjectClass *klass, void *data)

hw/usb/hcd-ohci.c +4 -0

index 267982e..8b5e579 100644
@@ -2139,6 +2139,10 @@ static const TypeInfo ohci_pci_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(OHCIPCIState),
     .class_init    = ohci_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static Property ohci_sysbus_properties[] = {

hw/usb/hcd-uhci.c +4 -0

index e3562a4..8842ea6 100644
@@ -1323,6 +1323,10 @@ static const TypeInfo uhci_pci_type_info = {
     .class_size    = sizeof(UHCIPCIDeviceClass),
     .abstract = true,
     .class_init = uhci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void uhci_data_class_init(ObjectClass *klass, void *data)

hw/vfio/pci-quirks.c +4 -0

index 349085e..83a820a 100644
@@ -1197,6 +1197,10 @@ static TypeInfo vfio_pci_igd_lpc_bridge_info = {
     .name = "vfio-pci-igd-lpc-bridge",
     .parent = TYPE_PCI_DEVICE,
     .class_init = vfio_pci_igd_lpc_bridge_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void vfio_pci_igd_register_types(void)

hw/watchdog/wdt_i6300esb.c +4 -0

index 49b3cd1..f8b7e0c 100644
@@ -463,6 +463,10 @@ static const TypeInfo i6300esb_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(I6300State),
     .class_init    = i6300esb_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void i6300esb_register_types(void)

hw/xen/xen_pt.c +4 -0

index 375efa6..66664fc 100644
@@ -964,6 +964,10 @@ static const TypeInfo xen_pci_passthrough_info = {
     .instance_size = sizeof(XenPCIPassthroughState),
     .instance_finalize = xen_pci_passthrough_finalize,
     .class_init = xen_pci_passthrough_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void xen_pci_passthrough_register_types(void)

Signature · 1 line

2.9.4

Add INTERFACE_LEGACY_PCI_DEVICE to all direct subtypes of TYPE_PCI_DEVICE, except:

1) The ones that already have INTERFACE_PCIE_DEVICE set:

* base-xhci
* e1000e
* nvme
* pvscsi
* vfio-pci
* virtio-pci
* vmxnet3

2) base-pci-bridge

Not all PCI bridges are legacy PCI devices, so INTERFACE_LEGACY_PCI_DEVICE is added only to the subtypes that are actually legacy PCI devices:

* dec-21154-p2p-bridge
* i82801b11-bridge
* pbm-bridge
* pci-bridge

The direct subtypes of base-pci-bridge not touched by this patch are:

* xilinx-pcie-root: Already marked as PCIe-only device.
* pcie-port: all non-abstract subtypes of pcie-port are already marked as PCIe-only devices.

3) megasas-base

Not all megasas devices are legacy PCI devices, so the interface names are added to the subclasses registered by megasas_register_types(), according to information in the megasas_devices[] array.

"megasas-gen2" already implements INTERFACE_PCIE_DEVICE, so add INTERFACE_LEGACY_PCI_DEVICE only to "megasas".

Signed-off-by Eduardo Habkost <[email protected]>

---
 hw/acpi/piix4.c                     |  1 +
 hw/audio/ac97.c                     |  4 ++++
 hw/audio/es1370.c                   |  4 ++++
 hw/audio/intel-hda.c                |  4 ++++
 hw/char/serial-pci.c                | 12 ++++++++++++
 hw/display/cirrus_vga.c             |  4 ++++
 hw/display/qxl.c                    |  4 ++++
 hw/display/sm501.c                  |  4 ++++
 hw/display/vga-pci.c                |  4 ++++
 hw/display/vmware_vga.c             |  4 ++++
 hw/i2c/smbus_ich9.c                 |  4 ++++
 hw/i386/amd_iommu.c                 |  4 ++++
 hw/i386/kvm/pci-assign.c            |  4 ++++
 hw/i386/pc_piix.c                   |  4 ++++
 hw/i386/xen/xen_platform.c          |  4 ++++
 hw/i386/xen/xen_pvdevice.c          |  4 ++++
 hw/ide/ich.c                        |  4 ++++
 hw/ide/pci.c                        |  4 ++++
 hw/ipack/tpci200.c                  |  4 ++++
 hw/isa/i82378.c                     |  4 ++++
 hw/isa/lpc_ich9.c                   |  1 +
 hw/isa/piix4.c                      |  4 ++++
 hw/isa/vt82c686.c                   | 16 ++++++++++++++++
 hw/mips/gt64xxx_pci.c               |  4 ++++
 hw/misc/edu.c                       |  5 +++++
 hw/misc/ivshmem.c                   |  4 ++++
 hw/misc/macio/macio.c               |  4 ++++
 hw/misc/pci-testdev.c               |  4 ++++
 hw/net/e1000.c                      |  4 ++++
 hw/net/eepro100.c                   |  4 ++++
 hw/net/ne2000.c                     |  4 ++++
 hw/net/pcnet-pci.c                  |  4 ++++
 hw/net/rocker/rocker.c              |  4 ++++
 hw/net/rtl8139.c                    |  4 ++++
 hw/pci-bridge/dec.c                 |  8 ++++++++
 hw/pci-bridge/i82801b11.c           |  4 ++++
 hw/pci-bridge/pci_bridge_dev.c      |  1 +
 hw/pci-bridge/pci_expander_bridge.c |  8 ++++++++
 hw/pci-host/apb.c                   |  8 ++++++++
 hw/pci-host/bonito.c                |  4 ++++
 hw/pci-host/gpex.c                  |  4 ++++
 hw/pci-host/grackle.c               |  4 ++++
 hw/pci-host/piix.c                  |  8 ++++++++
 hw/pci-host/ppce500.c               |  4 ++++
 hw/pci-host/prep.c                  |  4 ++++
 hw/pci-host/q35.c                   |  4 ++++
 hw/pci-host/uninorth.c              | 16 ++++++++++++++++
 hw/pci-host/versatile.c             |  4 ++++
 hw/ppc/ppc4xx_pci.c                 |  4 ++++
 hw/scsi/esp-pci.c                   |  4 ++++
 hw/scsi/lsi53c895a.c                |  4 ++++
 hw/scsi/megasas.c                   |  4 ++++
 hw/scsi/mptsas.c                    |  4 ++++
 hw/sd/sdhci.c                       |  4 ++++
 hw/sh4/sh_pci.c                     |  4 ++++
 hw/sparc64/sun4u.c                  |  4 ++++
 hw/usb/hcd-ehci-pci.c               |  4 ++++
 hw/usb/hcd-ohci.c                   |  4 ++++
 hw/usb/hcd-uhci.c                   |  4 ++++
 hw/vfio/pci-quirks.c                |  4 ++++
 hw/watchdog/wdt_i6300esb.c          |  4 ++++
 hw/xen/xen_pt.c                     |  4 ++++
 62 files changed, 288 insertions(+)

hw/acpi/piix4.c +1 -0

index f276967..defe98a 100644
@@ -723,6 +723,7 @@ static const TypeInfo piix4_pm_info = {
     .interfaces = (InterfaceInfo[]) {
         { TYPE_HOTPLUG_HANDLER },
         { TYPE_ACPI_DEVICE_IF },
+        { INTERFACE_LEGACY_PCI_DEVICE },
         { }
     }
 };

hw/audio/ac97.c +4 -0

index 959c786..6027e15 100644
@@ -1431,6 +1431,10 @@ static const TypeInfo ac97_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof (AC97LinkState),
     .class_init    = ac97_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void ac97_register_types (void)

hw/audio/es1370.c +4 -0

index dd7c23d..ed14ec3 100644
@@ -1082,6 +1082,10 @@ static const TypeInfo es1370_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof (ES1370State),
     .class_init    = es1370_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void es1370_register_types (void)

hw/audio/intel-hda.c +4 -0

index 06acc98..e2b9bf5 100644
@@ -1299,6 +1299,10 @@ static const TypeInfo intel_hda_info = {
     .instance_size = sizeof(IntelHDAState),
     .class_init    = intel_hda_class_init,
     .abstract      = true,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static const TypeInfo intel_hda_info_ich6 = {

hw/char/serial-pci.c +12 -0

index 303104d..c2dbcc0 100644
@@ -250,6 +250,10 @@ static const TypeInfo serial_pci_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCISerialState),
     .class_init    = serial_pci_class_initfn,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static const TypeInfo multi_2x_serial_pci_info = {

@@ -257,6 +261,10 @@ static const TypeInfo multi_2x_serial_pci_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIMultiSerialState),
     .class_init    = multi_2x_serial_pci_class_initfn,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static const TypeInfo multi_4x_serial_pci_info = {

@@ -264,6 +272,10 @@ static const TypeInfo multi_4x_serial_pci_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIMultiSerialState),
     .class_init    = multi_4x_serial_pci_class_initfn,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void serial_pci_register_types(void)

hw/display/cirrus_vga.c +4 -0

index afc290a..9a39fa0 100644
@@ -3162,6 +3162,10 @@ static const TypeInfo cirrus_vga_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCICirrusVGAState),
     .class_init    = cirrus_vga_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void cirrus_vga_register_types(void)

hw/display/qxl.c +4 -0

index ae3677f..1a010e8 100644
@@ -2430,6 +2430,10 @@ static const TypeInfo qxl_pci_type_info = {
     .instance_size = sizeof(PCIQXLDevice),
     .abstract = true,
     .class_init = qxl_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void qxl_primary_class_init(ObjectClass *klass, void *data)

hw/display/sm501.c +4 -0

index 9aa515b..7538f0c 100644
@@ -1843,6 +1843,10 @@ static const TypeInfo sm501_pci_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(SM501PCIState),
     .class_init    = sm501_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void sm501_register_types(void)

hw/display/vga-pci.c +4 -0

index ac9a764..72477e4 100644
@@ -338,6 +338,10 @@ static const TypeInfo vga_pci_type_info = {
     .instance_size = sizeof(PCIVGAState),
     .abstract = true,
     .class_init = vga_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void vga_class_init(ObjectClass *klass, void *data)

hw/display/vmware_vga.c +4 -0

index 4a64b41..9c2aa2d 100644
@@ -1350,6 +1350,10 @@ static const TypeInfo vmsvga_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(struct pci_vmsvga_state_s),
     .class_init    = vmsvga_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void vmsvga_register_types(void)

hw/i2c/smbus_ich9.c +4 -0

index ea51e09..83b0512 100644
@@ -119,6 +119,10 @@ static const TypeInfo ich9_smb_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(ICH9SMBState),
     .class_init = ich9_smb_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void ich9_smb_register(void)

hw/i386/amd_iommu.c +4 -0

index 334938a..471c7a9 100644
@@ -1227,6 +1227,10 @@ static const TypeInfo amdviPCI = {
     .name = "AMDVI-PCI",
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(AMDVIPCIState),
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void amdvi_iommu_memory_region_class_init(ObjectClass *klass, void *data)

hw/i386/kvm/pci-assign.c +4 -0

index 33e20cb..57800d3 100644
@@ -1864,6 +1864,10 @@ static const TypeInfo assign_info = {
     .instance_size      = sizeof(AssignedDevice),
     .class_init         = assign_class_init,
     .instance_init      = assigned_dev_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void assign_register_types(void)

hw/i386/pc_piix.c +4 -0

index 46dfd2c..eafc207 100644
@@ -1049,6 +1049,10 @@ static TypeInfo isa_bridge_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init = isa_bridge_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pt_graphics_register_types(void)

hw/i386/xen/xen_platform.c +4 -0

index 9ba7474..2113bd0 100644
@@ -517,6 +517,10 @@ static const TypeInfo xen_platform_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIXenPlatformState),
     .class_init    = xen_platform_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void xen_platform_register_types(void)

hw/i386/xen/xen_pvdevice.c +4 -0

index c093b34..e2ae81b 100644
@@ -127,6 +127,10 @@ static const TypeInfo xen_pv_type_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(XenPVDevice),
     .class_init    = xen_pv_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void xen_pv_register_types(void)

hw/ide/ich.c +4 -0

index 9472a60..0c60aa3 100644
@@ -184,6 +184,10 @@ static const TypeInfo ich_ahci_info = {
     .instance_size = sizeof(AHCIPCIState),
     .instance_init = pci_ich9_ahci_init,
     .class_init    = ich_ahci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void ich_ahci_register_types(void)

hw/ide/pci.c +4 -0

index 3cfb510..f437298 100644
@@ -458,6 +458,10 @@ static const TypeInfo pci_ide_type_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIIDEState),
     .abstract = true,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pci_ide_register_types(void)

hw/ipack/tpci200.c +4 -0

index 4dfa6b3..e380378 100644
@@ -646,6 +646,10 @@ static const TypeInfo tpci200_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(TPCI200State),
     .class_init    = tpci200_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void tpci200_register_types(void)

hw/isa/i82378.c +4 -0

index 4d29a99..13702b8 100644
@@ -138,6 +138,10 @@ static const TypeInfo i82378_type_info = {
     .instance_size = sizeof(I82378State),
     .instance_init = i82378_init,
     .class_init = i82378_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void i82378_register_types(void)

hw/isa/lpc_ich9.c +1 -0

index ac8416d..dcde152 100644
@@ -823,6 +823,7 @@ static const TypeInfo ich9_lpc_info = {
     .interfaces = (InterfaceInfo[]) {
         { TYPE_HOTPLUG_HANDLER },
         { TYPE_ACPI_DEVICE_IF },
+        { INTERFACE_LEGACY_PCI_DEVICE },
         { }
     }
 };

hw/isa/piix4.c +4 -0

index f811eba..515e55d 100644
@@ -132,6 +132,10 @@ static const TypeInfo piix4_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PIIX4State),
     .class_init    = piix4_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void piix4_register_types(void)

hw/isa/vt82c686.c +16 -0

index 50dc83d..319dc7f 100644
@@ -301,6 +301,10 @@ static const TypeInfo via_ac97_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(VT686AC97State),
     .class_init    = via_ac97_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp)

@@ -341,6 +345,10 @@ static const TypeInfo via_mc97_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(VT686MC97State),
     .class_init    = via_mc97_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 /* vt82c686 pm init */

@@ -419,6 +427,10 @@ static const TypeInfo via_pm_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(VT686PMState),
     .class_init    = via_pm_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static const VMStateDescription vmstate_via = {

@@ -502,6 +514,10 @@ static const TypeInfo via_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(VT82C686BState),
     .class_init    = via_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void vt82c686b_register_types(void)

hw/mips/gt64xxx_pci.c +4 -0

index e8b2eef..96d8cd0 100644
@@ -1232,6 +1232,10 @@ static const TypeInfo gt64120_pci_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init    = gt64120_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void gt64120_class_init(ObjectClass *klass, void *data)

hw/misc/edu.c +5 -0

index 01acacf..64b12b3 100644
@@ -408,12 +408,17 @@ static void edu_class_init(ObjectClass *class, void *data)
 
 static void pci_edu_register_types(void)
 {
+    static InterfaceInfo interfaces[] = {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    };
     static const TypeInfo edu_info = {
         .name          = "edu",
         .parent        = TYPE_PCI_DEVICE,
         .instance_size = sizeof(EduState),
         .instance_init = edu_instance_init,
         .class_init    = edu_class_init,
+        .interfaces = interfaces,
     };
 
     type_register_static(&edu_info);

hw/misc/ivshmem.c +4 -0

index 47a015f..da63c90 100644
@@ -1010,6 +1010,10 @@ static const TypeInfo ivshmem_common_info = {
     .instance_size = sizeof(IVShmemState),
     .abstract      = true,
     .class_init    = ivshmem_common_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static const VMStateDescription ivshmem_plain_vmsd = {

hw/misc/macio/macio.c +4 -0

index 5d57f45..fa163e3 100644
@@ -415,6 +415,10 @@ static const TypeInfo macio_type_info = {
     .instance_init = macio_instance_init,
     .abstract      = true,
     .class_init    = macio_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void macio_register_types(void)

hw/misc/pci-testdev.c +4 -0

index 7d59902..992157f 100644
@@ -326,6 +326,10 @@ static const TypeInfo pci_testdev_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCITestDevState),
     .class_init    = pci_testdev_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pci_testdev_register_types(void)

hw/net/e1000.c +4 -0

index f2e5072..51ab83d 100644
@@ -1685,6 +1685,10 @@ static const TypeInfo e1000_base_info = {
     .instance_init = e1000_instance_init,
     .class_size    = sizeof(E1000BaseClass),
     .abstract      = true,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static const E1000Info e1000_devices[] = {

hw/net/eepro100.c +4 -0

index 5a4774a..8f5c567 100644
@@ -2117,6 +2117,10 @@ static void eepro100_register_types(void)
         type_info.class_init = eepro100_class_init;
         type_info.instance_size = sizeof(EEPRO100State);
         type_info.instance_init = eepro100_instance_init;
+        type_info.interfaces = (InterfaceInfo[]) {
+            { INTERFACE_LEGACY_PCI_DEVICE },
+            { },
+        };
 
         type_register(&type_info);
     }

hw/net/ne2000.c +4 -0

index 798d681..fce3420 100644
@@ -786,6 +786,10 @@ static const TypeInfo ne2000_info = {
     .instance_size = sizeof(PCINE2000State),
     .class_init    = ne2000_class_init,
     .instance_init = ne2000_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void ne2000_register_types(void)

hw/net/pcnet-pci.c +4 -0

index 0acf8a4..cbe6e99 100644
@@ -365,6 +365,10 @@ static const TypeInfo pcnet_info = {
     .instance_size = sizeof(PCIPCNetState),
     .class_init    = pcnet_class_init,
     .instance_init = pcnet_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pci_pcnet_register_types(void)

hw/net/rocker/rocker.c +4 -0

index 4f0f6d7..2eb53ad 100644
@@ -1573,6 +1573,10 @@ static const TypeInfo rocker_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(Rocker),
     .class_init    = rocker_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void rocker_register_types(void)

hw/net/rtl8139.c +4 -0

index 671c7e4..3371318 100644
@@ -3489,6 +3489,10 @@ static const TypeInfo rtl8139_info = {
     .instance_size = sizeof(RTL8139State),
     .class_init    = rtl8139_class_init,
     .instance_init = rtl8139_instance_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void rtl8139_register_types(void)

hw/pci-bridge/dec.c +8 -0

index eb275e1..77a07d0 100644
@@ -79,6 +79,10 @@ static const TypeInfo dec_21154_pci_bridge_info = {
     .parent        = TYPE_PCI_BRIDGE,
     .instance_size = sizeof(PCIBridge),
     .class_init    = dec_21154_pci_bridge_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn)

@@ -138,6 +142,10 @@ static const TypeInfo dec_21154_pci_host_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init    = dec_21154_pci_host_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pci_dec_21154_device_class_init(ObjectClass *klass, void *data)

hw/pci-bridge/i82801b11.c +4 -0

index 2c1b747..baac63b 100644
@@ -106,6 +106,10 @@ static const TypeInfo i82801b11_bridge_info = {
     .parent        = TYPE_PCI_BRIDGE,
     .instance_size = sizeof(I82801b11Bridge),
     .class_init    = i82801b11_bridge_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void d2pbr_register(void)

hw/pci-bridge/pci_bridge_dev.c +1 -0

index 4373f1d..d83824b 100644
@@ -238,6 +238,7 @@ static const TypeInfo pci_bridge_dev_info = {
     .instance_finalize = pci_bridge_dev_instance_finalize,
     .interfaces = (InterfaceInfo[]) {
         { TYPE_HOTPLUG_HANDLER },
+        { INTERFACE_LEGACY_PCI_DEVICE },
         { }
     }
 };

hw/pci-bridge/pci_expander_bridge.c +8 -0

index ff59abf..cc9ec88 100644
@@ -316,6 +316,10 @@ static const TypeInfo pxb_dev_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PXBDev),
     .class_init    = pxb_dev_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pxb_pcie_dev_realize(PCIDevice *dev, Error **errp)

@@ -350,6 +354,10 @@ static const TypeInfo pxb_pcie_dev_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PXBDev),
     .class_init    = pxb_pcie_dev_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pxb_register_types(void)

hw/pci-host/apb.c +8 -0

index 96e5d0b..c2c8c6d 100644
@@ -817,6 +817,10 @@ static const TypeInfo pbm_pci_host_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init    = pbm_pci_host_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pbm_host_class_init(ObjectClass *klass, void *data)

@@ -857,6 +861,10 @@ static const TypeInfo pbm_pci_bridge_info = {
     .name          = "pbm-bridge",
     .parent        = TYPE_PCI_BRIDGE,
     .class_init    = pbm_pci_bridge_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pbm_iommu_memory_region_class_init(ObjectClass *klass, void *data)

hw/pci-host/bonito.c +4 -0

index 89133a9..f037378 100644
@@ -833,6 +833,10 @@ static const TypeInfo bonito_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIBonitoState),
     .class_init    = bonito_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void bonito_pcihost_class_init(ObjectClass *klass, void *data)

hw/pci-host/gpex.c +4 -0

index 83084b9..c348e84 100644
@@ -144,6 +144,10 @@ static const TypeInfo gpex_root_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(GPEXRootState),
     .class_init = gpex_root_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void gpex_register(void)

hw/pci-host/grackle.c +4 -0

index 2e281f6..01d3edc 100644
@@ -142,6 +142,10 @@ static const TypeInfo grackle_pci_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init = grackle_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pci_grackle_class_init(ObjectClass *klass, void *data)

hw/pci-host/piix.c +8 -0

index 072a04e..d35520e 100644
@@ -694,6 +694,10 @@ static const TypeInfo piix3_pci_type_info = {
     .instance_size = sizeof(PIIX3State),
     .abstract = true,
     .class_init = pci_piix3_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void piix3_class_init(ObjectClass *klass, void *data)

@@ -748,6 +752,10 @@ static const TypeInfo i440fx_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCII440FXState),
     .class_init    = i440fx_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 /* IGD Passthrough Host Bridge. */

hw/pci-host/ppce500.c +4 -0

index becc0ee..6dd66c4 100644
@@ -516,6 +516,10 @@ static const TypeInfo e500_host_bridge_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PPCE500PCIBridgeState),
     .class_init    = e500_host_bridge_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static Property pcihost_properties[] = {

hw/pci-host/prep.c +4 -0

index 8b293ba..bb19b6d 100644
@@ -372,6 +372,10 @@ static const TypeInfo raven_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(RavenPCIState),
     .class_init = raven_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static Property raven_pcihost_properties[] = {

hw/pci-host/q35.c +4 -0

index 0e472f2..a6f93f1 100644
@@ -591,6 +591,10 @@ static const TypeInfo mch_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(MCHPCIState),
     .class_init = mch_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void q35_register(void)

hw/pci-host/uninorth.c +16 -0

index 6cf5e59..3b40a9a 100644
@@ -374,6 +374,10 @@ static const TypeInfo unin_main_pci_host_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init = unin_main_pci_host_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)

@@ -398,6 +402,10 @@ static const TypeInfo u3_agp_pci_host_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init = u3_agp_pci_host_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)

@@ -422,6 +430,10 @@ static const TypeInfo unin_agp_pci_host_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init = unin_agp_pci_host_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)

@@ -446,6 +458,10 @@ static const TypeInfo unin_internal_pci_host_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init = unin_internal_pci_host_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void pci_unin_main_class_init(ObjectClass *klass, void *data)

hw/pci-host/versatile.c +4 -0

index aa1fdf7..e1ba6f4 100644
@@ -487,6 +487,10 @@ static const TypeInfo versatile_pci_host_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init    = versatile_pci_host_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static Property pci_vpb_properties[] = {

hw/ppc/ppc4xx_pci.c +4 -0

index 6953f8b..92027c3 100644
@@ -359,6 +359,10 @@ static const TypeInfo ppc4xx_host_bridge_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init    = ppc4xx_host_bridge_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)

hw/scsi/esp-pci.c +4 -0

index e295d88..2f0c659 100644
@@ -398,6 +398,10 @@ static const TypeInfo esp_pci_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIESPState),
     .class_init = esp_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 typedef struct {

hw/scsi/lsi53c895a.c +4 -0

index 3e56ab2..788bfc3 100644
@@ -2244,6 +2244,10 @@ static const TypeInfo lsi_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(LSIState),
     .class_init    = lsi_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void lsi53c810_class_init(ObjectClass *klass, void *data)

hw/scsi/megasas.c +4 -0

index 3641c30..cf69b56 100644
@@ -2468,6 +2468,10 @@ static struct MegasasInfo megasas_devices[] = {
         .is_express = false,
         .vmsd = &vmstate_megasas_gen1,
         .props = megasas_properties_gen1,
+        .interfaces = (InterfaceInfo[]) {
+            { INTERFACE_LEGACY_PCI_DEVICE },
+            { },
+        },
     },{
         .name = TYPE_MEGASAS_GEN2,
         .desc = "LSI MegaRAID SAS 2108",

hw/scsi/mptsas.c +4 -0

index 765ab53..6ff773e 100644
@@ -1441,6 +1441,10 @@ static const TypeInfo mptsas_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(MPTSASState),
     .class_init = mptsas1068_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void mptsas_register_types(void)

hw/sd/sdhci.c +4 -0

index 6d6a791..f6b18d6 100644
@@ -1315,6 +1315,10 @@ static const TypeInfo sdhci_pci_info = {
     .parent = TYPE_PCI_DEVICE,
     .instance_size = sizeof(SDHCIState),
     .class_init = sdhci_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static Property sdhci_sysbus_properties[] = {

hw/sh4/sh_pci.c +4 -0

index 38395c0..6cec225 100644
@@ -179,6 +179,10 @@ static const TypeInfo sh_pci_host_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PCIDevice),
     .class_init    = sh_pci_host_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void sh_pci_device_class_init(ObjectClass *klass, void *data)

hw/sparc64/sun4u.c +4 -0

index bbdb40c..b2b3bab 100644
@@ -277,6 +277,10 @@ static const TypeInfo ebus_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(EbusState),
     .class_init    = ebus_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 #define TYPE_OPENPROM "openprom"

hw/usb/hcd-ehci-pci.c +4 -0

index 6dedcb8..464178d 100644
@@ -170,6 +170,10 @@ static const TypeInfo ehci_pci_type_info = {
     .instance_finalize = usb_ehci_pci_finalize,
     .abstract = true,
     .class_init = ehci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void ehci_data_class_init(ObjectClass *klass, void *data)

hw/usb/hcd-ohci.c +4 -0

index 267982e..8b5e579 100644
@@ -2139,6 +2139,10 @@ static const TypeInfo ohci_pci_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(OHCIPCIState),
     .class_init    = ohci_pci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static Property ohci_sysbus_properties[] = {

hw/usb/hcd-uhci.c +4 -0

index e3562a4..8842ea6 100644
@@ -1323,6 +1323,10 @@ static const TypeInfo uhci_pci_type_info = {
     .class_size    = sizeof(UHCIPCIDeviceClass),
     .abstract = true,
     .class_init = uhci_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void uhci_data_class_init(ObjectClass *klass, void *data)

hw/vfio/pci-quirks.c +4 -0

index 349085e..83a820a 100644
@@ -1197,6 +1197,10 @@ static TypeInfo vfio_pci_igd_lpc_bridge_info = {
     .name = "vfio-pci-igd-lpc-bridge",
     .parent = TYPE_PCI_DEVICE,
     .class_init = vfio_pci_igd_lpc_bridge_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void vfio_pci_igd_register_types(void)

hw/watchdog/wdt_i6300esb.c +4 -0

index 49b3cd1..f8b7e0c 100644
@@ -463,6 +463,10 @@ static const TypeInfo i6300esb_info = {
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(I6300State),
     .class_init    = i6300esb_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void i6300esb_register_types(void)

hw/xen/xen_pt.c +4 -0

index 375efa6..66664fc 100644
@@ -964,6 +964,10 @@ static const TypeInfo xen_pci_passthrough_info = {
     .instance_size = sizeof(XenPCIPassthroughState),
     .instance_finalize = xen_pci_passthrough_finalize,
     .class_init = xen_pci_passthrough_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_LEGACY_PCI_DEVICE },
+        { },
+    },
 };
 
 static void xen_pci_passthrough_register_types(void)

Signature · 1 line

2.9.4