ddr: marvell: only assert M_ODT[0] on write for a single CS
PATCH 1/1 ddr: marvell: only assert M_ODT[0] on write for a single CS
When using only a single DDR chip select only assert M_ODT[0] on write. Do not assert it on read and do not assert M_ODT[1] at all.
Signed-off-by Chris Packham <[email protected]>
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I have a custom board that sees correctable ECC errors (when running memtester[1] from Linux). When I used Marvell's bootloader I didn't see the errors.
There are a number of differences in Marvell's bootloader but this seems to be the minimal change that fixes my issue and may help other boards using a single CS. I've regression tested the db-88f6820-amc board.
drivers/ddr/marvell/a38x/ddr3_init.h | 3 ++- drivers/ddr/marvell/a38x/ddr3_training.c | 14 +++++++++----- drivers/ddr/marvell/a38x/ddr3_training_static.c | 3 ++- 3 files changed, 13 insertions(+), 7 deletions(-)
drivers/ddr/marvell/a38x/ddr3_init.h +2 -1
@@ -183,7 +183,8 @@ extern u32 g_znodt_data;extern u32 g_zpodt_ctrl;extern u32 g_znodt_ctrl;extern u32 g_dic; -extern u32 g_odt_config; +extern u32 g_odt_config_2cs; +extern u32 g_odt_config_1cs;extern u32 g_rtt_nom;extern u8 debug_training_access;
drivers/ddr/marvell/a38x/ddr3_training.c +9 -5
@@ -315,6 +315,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_enum hws_access_type access_type =ACCESS_TYPE_UNICAST ;u32 data_read[MAX_INTERFACE_NUM ];struct hws_topology_map *tm =ddr3_get_topology_map (); +u32 odt_config = g_odt_config_2cs; DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n",
@@ -570,6 +571,10 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_DUNIT_CONTROL_HIGH_REG , (init_cntr_prm->msys_init << 7), (1 << 7))); +/* calculate number of CS (per interface) */ +CHECK_STATUS (calc_cs_num + (dev_num, if_id, &cs_num)); + timing = tm->interface_params[if_id].timing;if (mode2_t !=0xff ) {
@@ -578,9 +583,6 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_/* Board topology map is forcing timing */ t2t = (timing ==HWS_TIM_2T ) ?1 :0 ; }else { -/* calculate number of CS (per interface) */ -CHECK_STATUS (calc_cs_num - (dev_num, if_id, &cs_num)); t2t = (cs_num ==1 ) ?0 :1 ; }
@@ -623,9 +625,11 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ (1 << 11)));/* Set Active control for ODT write transactions */ +if (cs_num ==1 ) + odt_config = g_odt_config_1cs;CHECK_STATUS (ddr3_tip_if_write (dev_num,ACCESS_TYPE_MULTICAST , -PARAM_NOT_CARE ,0x1494 , g_odt_config, +PARAM_NOT_CARE ,0x1494 , odt_config,MASK_ALL_BITS )); } }else {
@@ -1591,7 +1595,7 @@ static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,CHECK_STATUS (ddr3_tip_if_write (dev_num, access_type, if_id,ODT_TIMING_LOW , val,0xffff0 )); - val =0x71 | ((cwl_value -1 ) <<8 ) | ((cwl_value +5 ) <<12 ); + val =0x91 | ((cwl_value -1 ) <<8 ) | ((cwl_value +5 ) <<12 );CHECK_STATUS (ddr3_tip_if_write (dev_num, access_type, if_id,ODT_TIMING_HI_REG , val,0xffff ));if (odt_additional ==1 ) {
drivers/ddr/marvell/a38x/ddr3_training_static.c +2 -1
@@ -21,7 +21,8 @@ u32 g_zpodt_data = 45; /* controller data - P ODT */u32 g_znodt_data =45 ;/* controller data - N ODT */ u32 g_zpodt_ctrl =45 ;/* controller data - P ODT */ u32 g_znodt_ctrl =45 ;/* controller data - N ODT */ -u32 g_odt_config =0x120012 ; +u32 g_odt_config_2cs =0x120012 ; +u32 g_odt_config_1cs =0x10000 ;u32 g_rtt_nom =0x44 ;u32 g_dic =0x2 ;
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