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Linux Patch #8

PATCH In review [email protected] 1 participant 1 message Apr 27, 2018

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x86 x86 hardware vulnerabilities
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PATCH v6 8/10 Linux Patch #8

Intel and AMD SPEC_CTRL (0x48) MSR semantics may differ in the future (or in fact use different MSRs for the same functionality).

As such we need a run-time way to whitelist the appropriate MSR values.

Signed-off-by Konrad Rzeszutek Wilk <[email protected]>

---
v5: New patch
v6: static!
Changed the comment to describe the variable better.

---
 arch/x86/kernel/cpu/bugs.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)
arch/x86/kernel/cpu/bugs.c +9 -2
index 0cda27398a73..e7338b04770f 100644
@@ -35,6 +35,11 @@ static void __init ssb_select_mitigation(void);
  */
 static u64 __read_mostly x86_spec_ctrl_base;
 
+/*
+ * Allowed per-vendor SPEC_CTRL MSR bits.
+ */
+static u64 __read_mostly x86_spec_ctrl_mask = ~(SPEC_CTRL_IBRS);
+
 void __init check_bugs(void)
 {
 	/*

@@ -122,7 +127,7 @@ static enum spectre_v2_mitigation spectre_v2_enabled = SPECTRE_V2_NONE;
 
 void x86_set_spec_ctrl(u64 val)
 {
-	if (val & ~(SPEC_CTRL_IBRS | SPEC_CTRL_RDS))
+	if (val & x86_spec_ctrl_mask)
 		WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);
 	else
 		wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val);

@@ -469,8 +474,10 @@ static void __init ssb_select_mitigation(void)
 		/*
 		 * Intel uses the SPEC CTRL MSR Bit(2) for this.
 		 */
-		if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
+		if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
 			x86_spec_ctrl_base |= SPEC_CTRL_RDS;
+			x86_spec_ctrl_mask &= ~(SPEC_CTRL_RDS);
+		}
 
 	}
 }
Signature · 1 line
2.14.3