sunxi: fix eMMC stability issues on A64
cover sunxi: fix eMMC stability issues on A64
eMMC seems to require new clocking mode and calibration on A64, otherwise it is pretty unstable on some boards (e.g. Pinebook) with some eMMCs.
Vasily Khoruzhick (2):
sunxi-mmc: use new mode on A64
mmc: sunxi: run calibration on A64
arch/arm/include/asm/arch-sunxi/mmc.h | 6 +++++- arch/arm/mach-sunxi/Kconfig | 1 + drivers/mmc/sunxi_mmc.c | 10 ++++++++++ 3 files changed, 16 insertions(+), 1 deletion(-)
Signature · 1 line
2.17.0
PATCH 1/2 sunxi-mmc: use new mode on A64
That is necessary for using automatic calibration on A64 eMMC.
--- arch/arm/mach-sunxi/Kconfig | 1 + drivers/mmc/sunxi_mmc.c | 4 ++++ 2 files changed, 5 insertions(+)
arch/arm/mach-sunxi/Kconfig +1 -0
@@ -256,6 +256,7 @@ config MACH_SUN50I select SUNXI_DE2 select SUNXI_GEN_SUN6I select SUNXI_HIGH_SRAM + select MMC_SUNXI_HAS_NEW_MODE select SUPPORT_SPL select SUNXI_DRAM_DW select SUNXI_DRAM_DW_32BIT
drivers/mmc/sunxi_mmc.c +4 -0
@@ -167,8 +167,12 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)if (new_mode) {#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE +#ifdef CONFIG_MACH_SUN50I + val =0 ; +#else val =CCM_MMC_CTRL_MODE_SEL_NEW ;setbits_le32 (&priv->reg->ntsr,SUNXI_MMC_NTSR_MODE_SEL_NEW ); +#endif #endif }else { val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
Signature · 1 line
2.17.0
PATCH 1/2 sunxi-mmc: use new mode on A64
Hi,
Quoted 25 lines · Vasily Khoruzhick
That is necessary for using automatic calibration on A64 eMMC.
Signed-off-by Vasily khoruzhick <[email protected]>--- arch/arm/mach-sunxi/Kconfig | 1 + drivers/mmc/sunxi_mmc.c | 4 ++++ 2 files changed, 5 insertions(+)arch/arm/mach-sunxi/Kconfig +1
-0@@ -256,6 +256,7 @@ config MACH_SUN50I select SUNXI_DE2 select SUNXI_GEN_SUN6I select SUNXI_HIGH_SRAM + select MMC_SUNXI_HAS_NEW_MODE select SUPPORT_SPL select SUNXI_DRAM_DW select SUNXI_DRAM_DW_32BITdrivers/mmc/sunxi_mmc.c +0
-0
drivers/mmc/sunxi_mmc.c static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) · line 175
Quoted 9 lines
drivers/mmc/sunxi_mmc.c +4
-0@@ -167,8 +167,12 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)if (new_mode) {#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE +#ifdef CONFIG_MACH_SUN50I + val =0 ; +#else val =CCM_MMC_CTRL_MODE_SEL_NEW ;setbits_le32 (&priv->reg->ntsr,SUNXI_MMC_NTSR_MODE_SEL_NEW ); +#endif
Maybe we just can have #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE && !CONFIG_MACH_SUN50I ?
Thanks!
maxime
Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 833 bytes Desc: not available URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180502/fd5184a5/attachment.sig>
PATCH 2/2 mmc: sunxi: run calibration on A64
In reply to Vasily KhoruzhickAlong with using new mode it fixes eMMC instability on Pinebook
--- arch/arm/include/asm/arch-sunxi/mmc.h | 6 +++++- drivers/mmc/sunxi_mmc.c | 6 ++++++ 2 files changed, 11 insertions(+), 1 deletion(-)
arch/arm/include/asm/arch-sunxi/mmc.h +5 -1
@@ -47,7 +47,9 @@ struct sunxi_mmc {u32 cbda;/* 0x94 */ u32 res2[26 ];#ifdef CONFIG_SUNXI_GEN_SUN6I -u32 res3[64 ]; +u32 res3[17 ]; +u32 samp_dl; +u32 res4[46 ];#endif u32 fifo;/* 0x100 / 0x200 FIFO access address */ };
@@ -131,5 +133,7 @@ struct sunxi_mmc {#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)#define SUNXI_MMC_COMMON_RESET (1 << 18) +#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7) +struct mmc *sunxi_mmc_init (int sdc_no);#endif /* _SUNXI_MMC_H */
drivers/mmc/sunxi_mmc.c +6 -0
@@ -227,6 +227,12 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc) rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK ;writel (rval, &priv->reg->clkcr); +#ifdef CONFIG_MACH_SUN50I +/* Run calibration on A64 */ +if (priv->mmc_no ==2 ) +writel (SUNXI_MMC_CAL_DL_SW_EN , &priv->reg->samp_dl); +#endif +/* Re-enable Clock */ rval |=SUNXI_MMC_CLK_ENABLE ;writel (rval, &priv->reg->clkcr);
Signature · 1 line
2.17.0
PATCH 2/2 mmc: sunxi: run calibration on A64
Quoted 36 lines · Vasily Khoruzhick
Along with using new mode it fixes eMMC instability on Pinebook
Signed-off-by Vasily Khoruzhick <[email protected]>--- arch/arm/include/asm/arch-sunxi/mmc.h | 6 +++++- drivers/mmc/sunxi_mmc.c | 6 ++++++ 2 files changed, 11 insertions(+), 1 deletion(-)arch/arm/include/asm/arch-sunxi/mmc.h +5
-1@@ -47,7 +47,9 @@ struct sunxi_mmc {u32 cbda;/* 0x94 */ u32 res2[26 ];#ifdef CONFIG_SUNXI_GEN_SUN6I -u32 res3[64 ]; +u32 res3[17 ]; +u32 samp_dl; +u32 res4[46 ];#endif u32 fifo;/* 0x100 / 0x200 FIFO access address */ };@@ -131,5 +133,7 @@ struct sunxi_mmc {#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)#define SUNXI_MMC_COMMON_RESET (1 << 18) +#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7) +struct mmc *sunxi_mmc_init (int sdc_no);#endif /* _SUNXI_MMC_H */ drivers/mmc/sunxi_mmc.c +0
-0
drivers/mmc/sunxi_mmc.c static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc) · line 231
Quoted 5 lines
drivers/mmc/sunxi_mmc.c +2
-0@@ -227,6 +227,12 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc) rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK ;writel (rval, &priv->reg->clkcr); +#ifdef CONFIG_MACH_SUN50I +/* Run calibration on A64 */
I guess we could improve the comment here. This is needed only on the A64 eMMC controller, and we have to have a delay of zero before starting the calibration. The Allwinner BSP sets a delay only in the case of using in HS400, that is not supported in U-Boot (or Linux, for that matter).
Maxime
Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 833 bytes Desc: not available URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180502/acb153bf/attachment.sig>