fpu_helper.c: fix helper_fpscr_clrbit() function
PATCH 1/1 fpu_helper.c: fix helper_fpscr_clrbit() function
Fix the helper_fpscr_clrbit() function so it correctly sets the FEX and VX bits.
--- target/ppc/fpu_helper.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+)
target/ppc/fpu_helper.c +57 -0
@@ -325,6 +325,63 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)case FPSCR_RN :fpscr_set_rounding_mode (env);break ; +case FPSCR_VXSNAN : +case FPSCR_VXISI : +case FPSCR_VXIDI : +case FPSCR_VXZDZ : +case FPSCR_VXIMZ : +case FPSCR_VXVC : +case FPSCR_VXSOFT : +case FPSCR_VXSQRT : +case FPSCR_VXCVI : + { +int vxsnan, vxisi, vxidi, vxzdz, vximz, vxvc, vxsoft, vxsqrt, vxcvi; + vxsnan = (env->fpscr >> (31 -FPSCR_VXSNAN )) &1 ; + vxisi = (env->fpscr >> (31 -FPSCR_VXISI )) &1 ; + vxidi = (env->fpscr >> (31 -FPSCR_VXIDI )) &1 ; + vxzdz = (env->fpscr >> (31 -FPSCR_VXZDZ )) &1 ; + vximz = (env->fpscr >> (31 -FPSCR_VXIMZ )) &1 ; + vxvc = (env->fpscr >> (31 -FPSCR_VXVC )) &1 ; + vxsoft = (env->fpscr >> (31 -FPSCR_VXSOFT )) &1 ; + vxsqrt = (env->fpscr >> (31 -FPSCR_VXSQRT )) &1 ; + vxcvi = (env->fpscr >> (31 -FPSCR_VXCVI )) &1 ; +if (~(vxsnan & vxisi & vxidi & vxzdz & vximz & vxvc & vxsoft & + vxsqrt & vxcvi)) { +/* Set VX bit to zero */ + env->fpscr = env->fpscr & ~(1 <<FPSCR_VX ); + } + } +break ; +case FPSCR_VX : +case FPSCR_OX : +case FPSCR_UX : +case FPSCR_ZX : +case FPSCR_XX : +case FPSCR_VE : +case FPSCR_OE : +case FPSCR_UE : +case FPSCR_ZE : +case FPSCR_XE : + { +int vx, ox, ux, zx, xx, ve, oe, ue, ze, xe; + vx = (env->fpscr >> (31 -FPSCR_VX )) &1 ; + ox = (env->fpscr >> (31 -FPSCR_OX )) &1 ; + ux = (env->fpscr >> (31 -FPSCR_UX )) &1 ; + zx = (env->fpscr >> (31 -FPSCR_ZX )) &1 ; + xx = (env->fpscr >> (31 -FPSCR_XX )) &1 ; + ve = (env->fpscr >> (31 -FPSCR_VE )) &1 ; + oe = (env->fpscr >> (31 -FPSCR_OE )) &1 ; + ue = (env->fpscr >> (31 -FPSCR_UE )) &1 ; + ze = (env->fpscr >> (31 -FPSCR_ZE )) &1 ; + xe = (env->fpscr >> (31 -FPSCR_XE )) &1 ; +bool fex; + fex = (vx & ve) | (ox & oe) | (ux & ue) | (zx & ze) | (xx & xe); +unsigned int mask; + mask = (1 <<FPSCR_FEX ); +/* Set the FEX bit */ + env->fpscr = (env->fpscr & ~mask) | (-fex & mask); + } +break ;default :break ; }
Signature · 1 line
2.14.3 (Apple Git-98)
Quoted 2 lines · John Arbuckle
Fix the
helper_fpscr_clrbit()function so it correctly sets the FEX and VX bits.
This needs a lot more information in the commit message:
* What exactly was wrong with the previous setting of the FEX and VX bits?
* Where can we find documentation which describes how they should be set correctly?
This is information we need to properly review the patch.
Quoted 74 lines
Signed-off-by John Arbuckle <[email protected]>--- target/ppc/fpu_helper.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+)target/ppc/fpu_helper.c +57
-0@@ -325,6 +325,63 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)case FPSCR_RN :fpscr_set_rounding_mode (env);break ; +case FPSCR_VXSNAN : +case FPSCR_VXISI : +case FPSCR_VXIDI : +case FPSCR_VXZDZ : +case FPSCR_VXIMZ : +case FPSCR_VXVC : +case FPSCR_VXSOFT : +case FPSCR_VXSQRT : +case FPSCR_VXCVI : + { +int vxsnan, vxisi, vxidi, vxzdz, vximz, vxvc, vxsoft, vxsqrt, vxcvi; + vxsnan = (env->fpscr >> (31 -FPSCR_VXSNAN )) &1 ; + vxisi = (env->fpscr >> (31 -FPSCR_VXISI )) &1 ; + vxidi = (env->fpscr >> (31 -FPSCR_VXIDI )) &1 ; + vxzdz = (env->fpscr >> (31 -FPSCR_VXZDZ )) &1 ; + vximz = (env->fpscr >> (31 -FPSCR_VXIMZ )) &1 ; + vxvc = (env->fpscr >> (31 -FPSCR_VXVC )) &1 ; + vxsoft = (env->fpscr >> (31 -FPSCR_VXSOFT )) &1 ; + vxsqrt = (env->fpscr >> (31 -FPSCR_VXSQRT )) &1 ; + vxcvi = (env->fpscr >> (31 -FPSCR_VXCVI )) &1 ; +if (~(vxsnan & vxisi & vxidi & vxzdz & vximz & vxvc & vxsoft & + vxsqrt & vxcvi)) { +/* Set VX bit to zero */ + env->fpscr = env->fpscr & ~(1 <<FPSCR_VX ); + } + } +break ; +case FPSCR_VX : +case FPSCR_OX : +case FPSCR_UX : +case FPSCR_ZX : +case FPSCR_XX : +case FPSCR_VE : +case FPSCR_OE : +case FPSCR_UE : +case FPSCR_ZE : +case FPSCR_XE : + { +int vx, ox, ux, zx, xx, ve, oe, ue, ze, xe; + vx = (env->fpscr >> (31 -FPSCR_VX )) &1 ; + ox = (env->fpscr >> (31 -FPSCR_OX )) &1 ; + ux = (env->fpscr >> (31 -FPSCR_UX )) &1 ; + zx = (env->fpscr >> (31 -FPSCR_ZX )) &1 ; + xx = (env->fpscr >> (31 -FPSCR_XX )) &1 ; + ve = (env->fpscr >> (31 -FPSCR_VE )) &1 ; + oe = (env->fpscr >> (31 -FPSCR_OE )) &1 ; + ue = (env->fpscr >> (31 -FPSCR_UE )) &1 ; + ze = (env->fpscr >> (31 -FPSCR_ZE )) &1 ; + xe = (env->fpscr >> (31 -FPSCR_XE )) &1 ; +bool fex; + fex = (vx & ve) | (ox & oe) | (ux & ue) | (zx & ze) | (xx & xe); +unsigned int mask; + mask = (1 <<FPSCR_FEX ); +/* Set the FEX bit */ + env->fpscr = (env->fpscr & ~mask) | (-fex & mask); + } +break ;default :break ; }
Signature · 4 lines
David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
Quoted 11 lines · David Gibson
Quoted 2 lines · John Arbuckle
Fix the
helper_fpscr_clrbit()function so it correctly sets the FEX and VX bits.This needs a lot more information in the commit message:
* What exactly was wrong with the previous setting of the FEX and VX bits?
Determining the value for the FEX bit is suppose to be done like this:
FEX = (VX & VE) | (OX & OE) | (UX & UE) | (ZX & ZE) | (XX & XE))
It is described as "the logical OR of all the floating-point exception bits
masked by their respective enable bits". It was not implemented correctly. The value of FEX would stay on even when all other bits were set to off.
The VX bit is described as "the logical OR of all of the invalid operation exceptions". This bit was also not implemented correctly.
Quoted 2 lines
* Where can we find documentation which describes how they should be set correctly?
My main source of information is an IBM document called:
PowerPC Microprocessor Family:
The Programming Environments for 32-Bit Microprocessors
Page 62 is where the FPSCR information is located.
This is an older copy than the one I use but it is still very useful:
https://www.pdfdrive.net/powerpc-microprocessor-family-the-programming-environments-for-32-e3087633.html
I have an G3 and G5 iMac that I used to compare values with QEMU. This patch fixed all the problems I was having with these bits.
Please let me know if there is anything else I could provide to help.
Quoted 83 lines
This is information we need to properly review the patch.
Quoted 74 lines
Signed-off-by John Arbuckle <[email protected]>---
target/ppc/fpu_helper.c| 57 +++++++++++++++++++++++++++++++++++++++++++++++++1 file changed, 57 insertions(+)target/ppc/fpu_helper.c +57
-0@@ -325,6 +325,63 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)case FPSCR_RN :fpscr_set_rounding_mode (env);break ; +case FPSCR_VXSNAN : +case FPSCR_VXISI : +case FPSCR_VXIDI : +case FPSCR_VXZDZ : +case FPSCR_VXIMZ : +case FPSCR_VXVC : +case FPSCR_VXSOFT : +case FPSCR_VXSQRT : +case FPSCR_VXCVI : + { +int vxsnan, vxisi, vxidi, vxzdz, vximz, vxvc, vxsoft, vxsqrt, vxcvi; + vxsnan = (env->fpscr >> (31 -FPSCR_VXSNAN )) &1 ; + vxisi = (env->fpscr >> (31 -FPSCR_VXISI )) &1 ; + vxidi = (env->fpscr >> (31 -FPSCR_VXIDI )) &1 ; + vxzdz = (env->fpscr >> (31 -FPSCR_VXZDZ )) &1 ; + vximz = (env->fpscr >> (31 -FPSCR_VXIMZ )) &1 ; + vxvc = (env->fpscr >> (31 -FPSCR_VXVC )) &1 ; + vxsoft = (env->fpscr >> (31 -FPSCR_VXSOFT )) &1 ; + vxsqrt = (env->fpscr >> (31 -FPSCR_VXSQRT )) &1 ; + vxcvi = (env->fpscr >> (31 -FPSCR_VXCVI )) &1 ; +if (~(vxsnan & vxisi & vxidi & vxzdz & vximz & vxvc & vxsoft & + vxsqrt & vxcvi)) { +/* Set VX bit to zero */ + env->fpscr = env->fpscr & ~(1 <<FPSCR_VX ); + } + } +break ; +case FPSCR_VX : +case FPSCR_OX : +case FPSCR_UX : +case FPSCR_ZX : +case FPSCR_XX : +case FPSCR_VE : +case FPSCR_OE : +case FPSCR_UE : +case FPSCR_ZE : +case FPSCR_XE : + { +int vx, ox, ux, zx, xx, ve, oe, ue, ze, xe; + vx = (env->fpscr >> (31 -FPSCR_VX )) &1 ; + ox = (env->fpscr >> (31 -FPSCR_OX )) &1 ; + ux = (env->fpscr >> (31 -FPSCR_UX )) &1 ; + zx = (env->fpscr >> (31 -FPSCR_ZX )) &1 ; + xx = (env->fpscr >> (31 -FPSCR_XX )) &1 ; + ve = (env->fpscr >> (31 -FPSCR_VE )) &1 ; + oe = (env->fpscr >> (31 -FPSCR_OE )) &1 ; + ue = (env->fpscr >> (31 -FPSCR_UE )) &1 ; + ze = (env->fpscr >> (31 -FPSCR_ZE )) &1 ; + xe = (env->fpscr >> (31 -FPSCR_XE )) &1 ; +bool fex; + fex = (vx & ve) | (ox & oe) | (ux & ue) | (zx & ze) | (xx & xe); +unsigned int mask; + mask = (1 <<FPSCR_FEX ); +/* Set the FEX bit */ + env->fpscr = (env->fpscr & ~mask) | (-fex & mask); + } +break ;default :break ; }Signature · 4 lines
David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
Quoted 28 lines · John Arbuckle
Fix the
helper_fpscr_clrbit()function so it correctly sets the FEX and VX bits.Signed-off-by John Arbuckle <[email protected]>--- target/ppc/fpu_helper.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+)target/ppc/fpu_helper.c +12
-0@@ -325,6 +325,63 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)case FPSCR_RN :fpscr_set_rounding_mode (env);break ; +case FPSCR_VXSNAN : +case FPSCR_VXISI : +case FPSCR_VXIDI : +case FPSCR_VXZDZ : +case FPSCR_VXIMZ : +case FPSCR_VXVC : +case FPSCR_VXSOFT : +case FPSCR_VXSQRT : +case FPSCR_VXCVI : + { +int vxsnan, vxisi, vxidi, vxzdz, vximz, vxvc, vxsoft, vxsqrt, vxcvi; + vxsnan = (env->fpscr >> (31 -FPSCR_VXSNAN )) &1 ;
target/ppc/fpu_helper.c void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit) · line 349
Quoted 10 lines
target/ppc/fpu_helper.c +10
-0+ vxisi = (env->fpscr >> (31 -FPSCR_VXISI )) &1 ; + vxidi = (env->fpscr >> (31 -FPSCR_VXIDI )) &1 ; + vxzdz = (env->fpscr >> (31 -FPSCR_VXZDZ )) &1 ; + vximz = (env->fpscr >> (31 -FPSCR_VXIMZ )) &1 ; + vxvc = (env->fpscr >> (31 -FPSCR_VXVC )) &1 ; + vxsoft = (env->fpscr >> (31 -FPSCR_VXSOFT )) &1 ; + vxsqrt = (env->fpscr >> (31 -FPSCR_VXSQRT )) &1 ; + vxcvi = (env->fpscr >> (31 -FPSCR_VXCVI )) &1 ; +if (~(vxsnan & vxisi & vxidi & vxzdz & vximz & vxvc & vxsoft & + vxsqrt & vxcvi)) {
If all you're doing is checking "are none of these bits set" then you don't need to laboriously extract every bit and then AND them together -- you can just use
if (!(env->fpscr & some_mask))
In fact the headers already define a macro which does that mask on env->fpscr, so this can just be
if (!fpscr_ix) {
env->fpscr &= ~(1 << FPSCR_VX);
}Quoted 23 lines
target/ppc/fpu_helper.c +23
-0+/* Set VX bit to zero */ + env->fpscr = env->fpscr & ~(1 <<FPSCR_VX ); + } + } +break ; +case FPSCR_VX : +case FPSCR_OX : +case FPSCR_UX : +case FPSCR_ZX : +case FPSCR_XX : +case FPSCR_VE : +case FPSCR_OE : +case FPSCR_UE : +case FPSCR_ZE : +case FPSCR_XE : + { +int vx, ox, ux, zx, xx, ve, oe, ue, ze, xe; + vx = (env->fpscr >> (31 -FPSCR_VX )) &1 ; + ox = (env->fpscr >> (31 -FPSCR_OX )) &1 ; + ux = (env->fpscr >> (31 -FPSCR_UX )) &1 ; + zx = (env->fpscr >> (31 -FPSCR_ZX )) &1 ; + xx = (env->fpscr >> (31 -FPSCR_XX )) &1 ; + ve = (env->fpscr >> (31 -FPSCR_VE )) &1 ;
target/ppc/fpu_helper.c void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit) · line 382
Quoted 10 lines
target/ppc/fpu_helper.c +10
-0+ oe = (env->fpscr >> (31 -FPSCR_OE )) &1 ; + ue = (env->fpscr >> (31 -FPSCR_UE )) &1 ; + ze = (env->fpscr >> (31 -FPSCR_ZE )) &1 ; + xe = (env->fpscr >> (31 -FPSCR_XE )) &1 ; +bool fex; + fex = (vx & ve) | (ox & oe) | (ux & ue) | (zx & ze) | (xx & xe); +unsigned int mask; + mask = (1 <<FPSCR_FEX ); +/* Set the FEX bit */ + env->fpscr = (env->fpscr & ~mask) | (-fex & mask);
Similarly I think this is
if (!fpscr_eex) {
env->fpscr &= ~(1 << FPSCR_FEX);
}Quoted 8 lines
target/ppc/fpu_helper.c +2
-1+ } +break ;default :break ; } --2.14.3 (Apple Git-98)
thanks
-- PMM
Quoted 102 lines · Peter Maydell
Quoted 28 lines · John Arbuckle
Fix the
helper_fpscr_clrbit()function so it correctly sets the FEX and VX bits.Signed-off-by John Arbuckle <[email protected]>---
target/ppc/fpu_helper.c| 57 +++++++++++++++++++++++++++++++++++++++++++++++++1 file changed, 57 insertions(+)target/ppc/fpu_helper.c +12
-0@@ -325,6 +325,63 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)case FPSCR_RN :fpscr_set_rounding_mode (env);break ; +case FPSCR_VXSNAN : +case FPSCR_VXISI : +case FPSCR_VXIDI : +case FPSCR_VXZDZ : +case FPSCR_VXIMZ : +case FPSCR_VXVC : +case FPSCR_VXSOFT : +case FPSCR_VXSQRT : +case FPSCR_VXCVI : + { +int vxsnan, vxisi, vxidi, vxzdz, vximz, vxvc, vxsoft, vxsqrt, vxcvi; + vxsnan = (env->fpscr >> (31 -FPSCR_VXSNAN )) &1 ;target/ppc/fpu_helper.c void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit) · line 349
Quoted 10 lines
target/ppc/fpu_helper.c +10
-0+ vxisi = (env->fpscr >> (31 -FPSCR_VXISI )) &1 ; + vxidi = (env->fpscr >> (31 -FPSCR_VXIDI )) &1 ; + vxzdz = (env->fpscr >> (31 -FPSCR_VXZDZ )) &1 ; + vximz = (env->fpscr >> (31 -FPSCR_VXIMZ )) &1 ; + vxvc = (env->fpscr >> (31 -FPSCR_VXVC )) &1 ; + vxsoft = (env->fpscr >> (31 -FPSCR_VXSOFT )) &1 ; + vxsqrt = (env->fpscr >> (31 -FPSCR_VXSQRT )) &1 ; + vxcvi = (env->fpscr >> (31 -FPSCR_VXCVI )) &1 ; +if (~(vxsnan & vxisi & vxidi & vxzdz & vximz & vxvc & vxsoft & + vxsqrt & vxcvi)) {If all you're doing is checking "are none of these bits set" then you don't need to laboriously extract every bit and then AND them together -- you can just use
if (!(env->fpscr &some_mask))
In fact the headers already define a macro which does that mask onenv->fpscr, so this can just beif (!fpscr_ix) { env->fpscr &= ~(1 << FPSCR_VX); }Quoted 23 lines
target/ppc/fpu_helper.c +23
-0+/* Set VX bit to zero */ + env->fpscr = env->fpscr & ~(1 <<FPSCR_VX ); + } + } +break ; +case FPSCR_VX : +case FPSCR_OX : +case FPSCR_UX : +case FPSCR_ZX : +case FPSCR_XX : +case FPSCR_VE : +case FPSCR_OE : +case FPSCR_UE : +case FPSCR_ZE : +case FPSCR_XE : + { +int vx, ox, ux, zx, xx, ve, oe, ue, ze, xe; + vx = (env->fpscr >> (31 -FPSCR_VX )) &1 ; + ox = (env->fpscr >> (31 -FPSCR_OX )) &1 ; + ux = (env->fpscr >> (31 -FPSCR_UX )) &1 ; + zx = (env->fpscr >> (31 -FPSCR_ZX )) &1 ; + xx = (env->fpscr >> (31 -FPSCR_XX )) &1 ; + ve = (env->fpscr >> (31 -FPSCR_VE )) &1 ;target/ppc/fpu_helper.c void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit) · line 382
Quoted 10 lines
target/ppc/fpu_helper.c +10
-0+ oe = (env->fpscr >> (31 -FPSCR_OE )) &1 ; + ue = (env->fpscr >> (31 -FPSCR_UE )) &1 ; + ze = (env->fpscr >> (31 -FPSCR_ZE )) &1 ; + xe = (env->fpscr >> (31 -FPSCR_XE )) &1 ; +bool fex; + fex = (vx & ve) | (ox & oe) | (ux & ue) | (zx & ze) | (xx & xe); +unsigned int mask; + mask = (1 <<FPSCR_FEX ); +/* Set the FEX bit */ + env->fpscr = (env->fpscr & ~mask) | (-fex & mask);Similarly I think this is
if (!fpscr_eex) { env->fpscr &= ~(1 << FPSCR_FEX);}
Quoted 8 lines
target/ppc/fpu_helper.c +2
-1+ } +break ;default :break ; } --2.14.3 (Apple Git-98)
Quoted 2 lines
thanks
-- PMM
Your suggestions look great. Thank you. I will be sure to implement your suggestions and make a better commit message for version 2 of this patch.