Add support for MIPS Creator CI20

A new round.

For this new round:

* Replaced infinite while loop with wait_for_bit.
* Added a MAINTAINERS file. If anyone wants to co-maintain this, please let me know.

This is based on top of yesterday's master (ee168783ae8) and has been tested by SD-card booting both U-Boot and Linux. Booting Linux via TFTP was also tested.

Toolchain used to test:

$ mips-linux-gcc -v
Using built-in specs.
COLLECT_GCC=mips-linux-gcc
COLLECT_LTO_WRAPPER=/home/zeta/.buildman-toolchains/gcc-7.3.0-nolibc/mips-linux/bin/../libexec/gcc/mips-linux/7.3.0/lto-wrapper
Target: mips-linux
Configured with: /home/arnd/git/gcc/configure --target=mips-linux --enable-targets=all --prefix=/opt/crosstool/gcc-7.3.0-nolibc/mips-linux --enable-languages=c --without-headers --disable-bootstrap --disable-nls --disable-threads --disable-shared --disable-libmudflap --disable-libssp --disable-libgomp --disable-decimal-float --disable-libquadmath --disable-libatomic --disable-libcc1 --disable-libmpx --enable-checking=release
Thread model: single
gcc version 7.3.0 (GCC) 

SPL size:

$ size spl/u-boot-spl
   text	   data	    bss	    dec	    hex	filename
   9252	    752	    736	  10740	   29f4	spl/u-boot-spl

I've pushed a branch to https://github.com/ezequielgarcia/u-boot/tree/ci20-v2
and made sure travis passed.

Note that Paul's contributions are recorded using his imgtec.com mail although it's no longer valid, and that we will rely on mailmap to map it to mips.com.

It would be terrific to fit this on the next release.

Thanks!

Paul Burton (6):
misc: Add JZ47xx efuse driver
gpio: Add JZ47xx GPIO driver
mmc: Add JZ47xx SD/MMC controller driver
mips: Add SPL header
mips: jz47xx: Add JZ4780 SoC support
mips: jz47xx: Add Creator CI20 platform

 arch/mips/Kconfig                             |   7 +
 arch/mips/Makefile                            |   1 +
 arch/mips/dts/Makefile                        |   1 +
 arch/mips/dts/ci20.dts                        | 120 ++++
 arch/mips/dts/jz4780.dtsi                     | 162 ++++++
 arch/mips/include/asm/spl.h                   |  35 ++
 arch/mips/mach-jz47xx/Kconfig                 |  26 +
 arch/mips/mach-jz47xx/Makefile                |   7 +
 arch/mips/mach-jz47xx/include/mach/jz4780.h   | 104 ++++
 .../mach-jz47xx/include/mach/jz4780_dram.h    | 457 +++++++++++++++
 arch/mips/mach-jz47xx/jz4780/Makefile         |   5 +
 arch/mips/mach-jz47xx/jz4780/jz4780.c         | 142 +++++
 arch/mips/mach-jz47xx/jz4780/pll.c            | 528 ++++++++++++++++++
 arch/mips/mach-jz47xx/jz4780/sdram.c          | 271 +++++++++
 arch/mips/mach-jz47xx/jz4780/timer.c          | 238 ++++++++
 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds   |  52 ++
 arch/mips/mach-jz47xx/start.S                 |  99 ++++
 board/imgtec/ci20/Kconfig                     |  15 +
 board/imgtec/ci20/MAINTAINERS                 |   6 +
 board/imgtec/ci20/Makefile                    |   5 +
 board/imgtec/ci20/README                      |  10 +
 board/imgtec/ci20/ci20.c                      | 365 ++++++++++++
 configs/ci20_defconfig                        |  47 ++
 drivers/gpio/Kconfig                          |   7 +
 drivers/gpio/Makefile                         |   1 +
 drivers/gpio/gpio-jz47xx.c                    |  78 +++
 drivers/misc/Kconfig                          |   6 +
 drivers/misc/Makefile                         |   1 +
 drivers/misc/jz4780_efuse.c                   | 104 ++++
 drivers/mmc/Kconfig                           |   6 +
 drivers/mmc/Makefile                          |   1 +
 drivers/mmc/jz_mmc.                           |   0
 drivers/mmc/jz_mmc.c                          | 489 ++++++++++++++++
 include/configs/ci20.h                        |  74 +++
 include/dt-bindings/clock/jz4780-cgu.h        |  88 +++
 35 files changed, 3558 insertions(+)
 create mode 100644 arch/mips/dts/ci20.dts
 create mode 100644 arch/mips/dts/jz4780.dtsi
 create mode 100644 arch/mips/include/asm/spl.h
 create mode 100644 arch/mips/mach-jz47xx/Kconfig
 create mode 100644 arch/mips/mach-jz47xx/Makefile
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780.h
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780_dram.h
 create mode 100644 arch/mips/mach-jz47xx/jz4780/Makefile
 create mode 100644 arch/mips/mach-jz47xx/jz4780/jz4780.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/pll.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/sdram.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/timer.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
 create mode 100644 arch/mips/mach-jz47xx/start.S
 create mode 100644 board/imgtec/ci20/Kconfig
 create mode 100644 board/imgtec/ci20/MAINTAINERS
 create mode 100644 board/imgtec/ci20/Makefile
 create mode 100644 board/imgtec/ci20/README
 create mode 100644 board/imgtec/ci20/ci20.c
 create mode 100644 configs/ci20_defconfig
 create mode 100644 drivers/gpio/gpio-jz47xx.c
 create mode 100644 drivers/misc/jz4780_efuse.c
 create mode 100644 drivers/mmc/jz_mmc.
 create mode 100644 drivers/mmc/jz_mmc.c
 create mode 100644 include/configs/ci20.h
 create mode 100644 include/dt-bindings/clock/jz4780-cgu.h

2.20.0.rc2

From: Paul Burton <[email protected]>

Add driver for the efuse block in the JZ47xx SOC.

---
 drivers/misc/Kconfig        |   6 +++
 drivers/misc/Makefile       |   1 +
 drivers/misc/jz4780_efuse.c | 104 ++++++++++++++++++++++++++++++++++++
 3 files changed, 111 insertions(+)
 create mode 100644 drivers/misc/jz4780_efuse.c

index 48febc47d263..704c8dd1955f 100644
@@ -120,6 +120,12 @@ config FSL_SEC_MON
 	  Security Monitor can be transitioned on any security failures,
 	  like software violations or hardware security violations.
 
+config JZ4780_EFUSE
+	bool "Ingenic JZ4780 eFUSE support"
+	depends on ARCH_JZ47XX
+	help
+	  This selects support for the eFUSE on Ingenic JZ4780 SoCs.
+
 config MXC_OCOTP
 	bool "Enable MXC OCOTP Driver"
 	help

index 302d44159274..6bdf5054f475 100644
@@ -62,3 +62,4 @@ obj-$(CONFIG_TEGRA_CAR) += tegra_car.o
 obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
 obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o
 obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
+obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o

2.20.0.rc2

From: Paul Burton <[email protected]>

Add primitive GPIO controller driver for the JZ47xx SoC.

---
 drivers/gpio/Kconfig       |  7 ++++
 drivers/gpio/Makefile      |  1 +
 drivers/gpio/gpio-jz47xx.c | 78 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 86 insertions(+)
 create mode 100644 drivers/gpio/gpio-jz47xx.c

index 35344e57c6c6..46c161c99ce9 100644
@@ -322,4 +322,11 @@ config MT7621_GPIO
 	help
 	  Say yes here to support MediaTek MT7621 compatible GPIOs.
 
+config JZ47XX_GPIO
+	bool "Ingenic JZ47xx GPIO driver"
+	depends on ARCH_JZ47XX
+	default y
+	help
+	  Supports GPIO access on Ingenic JZ47xx SoCs.
+
 endmenu

index 7ed9a4ec4221..92310e9ba934 100644
@@ -59,3 +59,4 @@ obj-$(CONFIG_MSM_GPIO)		+= msm_gpio.o
 obj-$(CONFIG_$(SPL_)PCF8575_GPIO)	+= pcf8575_gpio.o
 obj-$(CONFIG_PM8916_GPIO)	+= pm8916_gpio.o
 obj-$(CONFIG_MT7621_GPIO)	+= mt7621_gpio.o
+obj-$(CONFIG_JZ47XX_GPIO)	+= gpio-jz47xx.o

2.20.0.rc2

From: Paul Burton <[email protected]>

Add driver for the JZ47xx MSC controller.

---
 drivers/mmc/Kconfig  |   6 +
 drivers/mmc/Makefile |   1 +
 drivers/mmc/jz_mmc.  |   0
 drivers/mmc/jz_mmc.c | 489 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 496 insertions(+)
 create mode 100644 drivers/mmc/jz_mmc.
 create mode 100644 drivers/mmc/jz_mmc.c

index fbd13964a084..496b2cba6405 100644
@@ -332,6 +332,12 @@ config MMC_BCM2835
 
 	  If unsure, say N.
 
+config JZ47XX_MMC
+	bool "Ingenic JZ47xx SD/MMC Host Controller support"
+	depends on ARCH_JZ47XX
+	help
+	  This selects support for the SD Card Controller on Ingenic JZ47xx SoCs.
+
 config MMC_SANDBOX
 	bool "Sandbox MMC support"
 	depends on SANDBOX

index 801a26d82192..7892c468f05c 100644
@@ -40,6 +40,7 @@ obj-$(CONFIG_MMC_SANDBOX)		+= sandbox_mmc.o
 obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
 obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
 obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o
+obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o
 
 # SDHCI
 obj-$(CONFIG_MMC_SDHCI)			+= sdhci.o

new file mode 100644
index 000000000000..e69de29bb2d1

2.20.0.rc2

From: Paul Burton <[email protected]>

Add header with SPL boot mode and type definitions.

---
 arch/mips/include/asm/spl.h | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 arch/mips/include/asm/spl.h

new file mode 100644
index 000000000000..01baab606606
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_ASM_SPL_H_
+#define	_ASM_SPL_H_
+
+enum {
+	BOOT_DEVICE_RAM,
+	BOOT_DEVICE_MMC1,
+	BOOT_DEVICE_MMC2,
+	BOOT_DEVICE_MMC2_2,
+	BOOT_DEVICE_NAND,
+	BOOT_DEVICE_ONENAND,
+	BOOT_DEVICE_NOR,
+	BOOT_DEVICE_UART,
+	BOOT_DEVICE_SPI,
+	BOOT_DEVICE_USB,
+	BOOT_DEVICE_SATA,
+	BOOT_DEVICE_I2C,
+	BOOT_DEVICE_BOARD,
+	BOOT_DEVICE_NONE
+};
+
+/* Linker symbols. */
+extern char __bss_start[];
+extern ulong __bss_end;
+
+#ifndef CONFIG_DM
+extern gd_t gdata;
+#endif
+
+#endif

2.20.0.rc2

From: Paul Burton <[email protected]>

Add initial support for the Ingenic JZ47xx MIPS SoC.

---
 arch/mips/Kconfig                             |   7 +
 arch/mips/Makefile                            |   1 +
 arch/mips/dts/jz4780.dtsi                     | 162 ++++++
 arch/mips/mach-jz47xx/Kconfig                 |  15 +
 arch/mips/mach-jz47xx/Makefile                |   7 +
 arch/mips/mach-jz47xx/include/mach/jz4780.h   | 104 ++++
 .../mach-jz47xx/include/mach/jz4780_dram.h    | 457 +++++++++++++++
 arch/mips/mach-jz47xx/jz4780/Makefile         |   5 +
 arch/mips/mach-jz47xx/jz4780/jz4780.c         | 142 +++++
 arch/mips/mach-jz47xx/jz4780/pll.c            | 528 ++++++++++++++++++
 arch/mips/mach-jz47xx/jz4780/sdram.c          | 271 +++++++++
 arch/mips/mach-jz47xx/jz4780/timer.c          | 238 ++++++++
 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds   |  52 ++
 arch/mips/mach-jz47xx/start.S                 |  99 ++++
 include/dt-bindings/clock/jz4780-cgu.h        |  88 +++
 15 files changed, 2176 insertions(+)
 create mode 100644 arch/mips/dts/jz4780.dtsi
 create mode 100644 arch/mips/mach-jz47xx/Kconfig
 create mode 100644 arch/mips/mach-jz47xx/Makefile
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780.h
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780_dram.h
 create mode 100644 arch/mips/mach-jz47xx/jz4780/Makefile
 create mode 100644 arch/mips/mach-jz47xx/jz4780/jz4780.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/pll.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/sdram.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/timer.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
 create mode 100644 arch/mips/mach-jz47xx/start.S
 create mode 100644 include/dt-bindings/clock/jz4780-cgu.h

index 1b1b1d7d0031..44b25460b8cc 100644
@@ -88,6 +88,12 @@ config ARCH_MT7620
 	select SUPPORTS_LITTLE_ENDIAN
 	select SYSRESET
 
+config ARCH_JZ47XX
+	bool "Support Ingenic JZ47xx"
+	select SUPPORT_SPL
+	select OF_CONTROL
+	select DM
+
 config MACH_PIC32
 	bool "Support Microchip PIC32"
 	select DM

@@ -139,6 +145,7 @@ source "board/micronas/vct/Kconfig"
 source "board/qemu-mips/Kconfig"
 source "arch/mips/mach-ath79/Kconfig"
 source "arch/mips/mach-bmips/Kconfig"
+source "arch/mips/mach-jz47xx/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
 source "arch/mips/mach-mt7620/Kconfig"
 

index 802244a06e5d..a294e9b1e8b9 100644
@@ -13,6 +13,7 @@ libs-y += arch/mips/lib/
 
 machine-$(CONFIG_ARCH_ATH79) += ath79
 machine-$(CONFIG_ARCH_BMIPS) += bmips
+machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
 machine-$(CONFIG_MACH_PIC32) += pic32
 machine-$(CONFIG_ARCH_MT7620) += mt7620
 

new file mode 100644
index 000000000000..cd6944cfc252
@@ -0,0 +1,15 @@
+menu "Ingenic JZ47xx platforms"
+	depends on ARCH_JZ47XX
+
+config SYS_SOC
+	default "jz47xx"
+
+config SOC_JZ4780
+	bool
+	select SUPPORTS_LITTLE_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select SUPPORTS_CPU_MIPS32_R2
+	help
+	  Support for Ingenic JZ4780 family SoCs.
+
+endmenu

new file mode 100644
index 000000000000..5eee9acf559d
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-$(CONFIG_SPL_BUILD)	:= start.o
+
+obj-$(CONFIG_SOC_JZ4780)	+= jz4780/

new file mode 100644
index 000000000000..683eea65c2f1
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y := jz4780.o pll.o sdram.o timer.o

2.20.0.rc2

From: Paul Burton <[email protected]>

Add support for the Creator CI20 platform based on the JZ4780 SoC.

---
 arch/mips/dts/Makefile        |   1 +
 arch/mips/dts/ci20.dts        | 120 +++++++++++
 arch/mips/mach-jz47xx/Kconfig |  11 +
 board/imgtec/ci20/Kconfig     |  15 ++
 board/imgtec/ci20/MAINTAINERS |   6 +
 board/imgtec/ci20/Makefile    |   5 +
 board/imgtec/ci20/README      |  10 +
 board/imgtec/ci20/ci20.c      | 365 ++++++++++++++++++++++++++++++++++
 configs/ci20_defconfig        |  47 +++++
 include/configs/ci20.h        |  74 +++++++
 10 files changed, 654 insertions(+)
 create mode 100644 arch/mips/dts/ci20.dts
 create mode 100644 board/imgtec/ci20/Kconfig
 create mode 100644 board/imgtec/ci20/MAINTAINERS
 create mode 100644 board/imgtec/ci20/Makefile
 create mode 100644 board/imgtec/ci20/README
 create mode 100644 board/imgtec/ci20/ci20.c
 create mode 100644 configs/ci20_defconfig
 create mode 100644 include/configs/ci20.h

index b447141f8717..647d2bf0d53b 100644
@@ -16,6 +16,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
 dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f at st1704.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
+dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
 
 targets += $(dtb-y)
 

index cd6944cfc252..dcaac0162866 100644
@@ -12,4 +12,15 @@ config SOC_JZ4780
 	help
 	  Support for Ingenic JZ4780 family SoCs.
 
+choice
+	prompt "Board select"
+
+config TARGET_JZ4780_CI20
+	bool "Creator CI20 Reference Board"
+	select SOC_JZ4780
+
+endchoice
+
+source "board/imgtec/ci20/Kconfig"
+
 endmenu

new file mode 100644
index 000000000000..82bf65d64f1e
@@ -0,0 +1,15 @@
+if TARGET_JZ4780_CI20
+
+config SYS_BOARD
+	default "ci20"
+
+config SYS_VENDOR
+	default "imgtec"
+
+config SYS_CONFIG_NAME
+	default "ci20"
+
+config SYS_TEXT_BASE
+	default 0x80000000
+
+endif

new file mode 100644
index 000000000000..25971c31a789
@@ -0,0 +1,6 @@
+Creator CI20 BOARD
+M:      Ezequiel Garcia <[email protected]>
+S:      Maintained
+F:      board/imgtec/ci20/
+F:      include/configs/ci20.h
+F:      configs/ci20_defconfig

new file mode 100644
index 000000000000..8c00081e660b
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y := ci20.o

new file mode 100644
index 000000000000..c757d41c7640
@@ -0,0 +1,10 @@
+CI20 U-Boot
+
+Installation to an SD card:
+  Repartition your card with an MBR such that the first partition starts at an
+  offset of no less than 270KB. Then install U-Boot SPL & the full U-Boot image
+  to the card like so:
+
+    dd if=spl/u-boot-spl.bin of=/dev/sdX obs=512 seek=1
+    dd if=u-boot.img of=/dev/sdX obs=1K seek=14
+    sync

2.20.0.rc2

Hi Ezequiel,

Am 12.12.18 um 14:58 schrieb Ezequiel Garcia:

Thanks for working on this but the problem with the original patch series was that it was not fully driver model compatible and that stuff like watchdog, reset and pin-muxing was open-coded instead of using the proper frameworks. As the ship is sailing towards having only driver model and device tree in U-Boot proper, it doesn't make sense to accept new SoC/boards with legacy code especially if there is no active maintainer who would do the conversion work. And with the upcoming dead lines for DM conversions, boards with legacy code will be removed when not converted. This is also one of the reasons why the Ingenic SoC support we already had in mainline was removed. And readding parts of the removed code doesn't make sense either because the patch series is based on that old Ingenic SoC code.

I wanted to work on Marek's patch series to fix those issues because it's quite some work which I couldn't expect from Marek ;) But I got stuck with EJTAG because halting the CPU didn't work. Then I hadn't time anymore.

I'm little busy right now so I can't do a detailed review. But the issues which should be addressed at first are:

- fix all SPDX license identifiers
- convert GPIO driver to DM
- add a DM watchdog driver
- implement machine reset with the generic watchdog reset (see BMIPS for an example)
- don't use SoC specific start.S and u-boot-spl.lds, the generic code is now configurable enough and non-generic things could be done in a lowlevel_init.S
- reduce the hundreds of definitions of register addresses to the ones really needed in assembly or SPL. This stuff should come from device tree
- define the remaining register base addresses as physical addresses and establish a mapping with ioremap_nocache()

- Daniel

Hi Daniel,

I have to say I disagree with all of this.

The open coded drivers are used in SPL, which most likely can't affort any DM. Or **if** it can't afford it, it's a separate question that needs research.

The BootROM for this SoC can only load 14 KiB of code, and we are already at roughly 11 KiB.

This series, on the other side, is quite clean, quite small, has quite simple drivers (with even a DM MMC driver for the second stage)... ... and most importantly it works.

Given how much history this particular series has, if we delay it now with yet more requirements, we risk not ever having it.

We want to put this board on kernelCI labs, and having upstream U-Boot would be really nice for that, so we don't rely on ancient vendor forks.

As for a maintainer doing the work, I'm here and not going anywhere. I can do any follow-up work that's considered needed, including any DM conversions.

But, it would be really important to have a working starting point.

This really sounds that work that can be done as follow-up patches. And, we don't know if any of this will bloat the SPL beyond the current limit :-)

I must admit, I have a hard time understanding this blocker policy, for a series that gives support to a new board, and affects no other platforms.

Thanks,
Ezequiel

And this is a topic that keeps coming up, so I need to chime in again. For SPL, we _have_to_ keep in mind the various boot ROM hard space limits. This means that we end up needing to allow for some level of open-coded drivers used in limited cases like SPL and then a full / real driver in full U-Boot.

Tom
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Am 12.12.18 um 19:03 schrieb Ezequiel Garcia:

I know that and I don't demand DM in SPL, only for U-Boot proper. And there is always a ways of factoring out driver code which can be shared by SPL and a DM compatible driver.

There are no more requirements, only the standard ones which blocked the merge of the original series in the first place. If someone is willing to work these out in the review process, the series will get merged. ?

I'm not blocking anything, it's only my experience because I already have some boards where the original contributor is not reachable anymore and no one is available to test or change the code. So It's either merging code only with the required quality or to have a committment to do the required work after the initial merge.

At least for v3 fix the SPDX identifiers (first line of the file and beginning with //). Also the conversion of the GPIO driver to DM is simple enogh and should be done now. The only user of the legacy GPIO API in SPL is ci20_revision(). But most of the code is already bit-banging on the GPIO registers for muxing and pull-ups. Thus it doesn't matter in this context to replace gpio_direction_input() with another bit-banging to drop the dependency on the GPIO driver ;)

- Daniel