phy: qualcomm: add qcom ipq806x dwc usb phy driver
PATCH v3 1/2 phy: qualcomm: add qcom ipq806x dwc usb phy driver
This has lost in the original push for the dwc3 qcom driver. This is needed for ipq806x SoC as without this the usb ports doesn't work at all.
Signed-off-by Andy Gross <[email protected]>
Signed-off-by Ansuel Smith <[email protected]>
---
v3:
* Use reg instead of regmap phandle
v2:
* Renamed config from PHY_QCOM_DWC3 to PHY_QCOM_IPQ806X_USB
* Rename inline function to generic name to reduce length
* Fix check reported by checkpatch --strict
* Rename compatible to qcom,ipq806x-usb-phy-(hs/ss)
drivers/phy/qualcomm/Kconfig | 12 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 583 ++++++++++++++++++++ 3 files changed, 596 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
drivers/phy/qualcomm/Kconfig +12 -0
@@ -91,3 +91,15 @@ config PHY_QCOM_USB_HSIC select GENERIC_PHY help Support for the USB HSIC ULPI compliant PHY on QCOM chipsets. + +config PHY_QCOM_IPQ806X_USB + tristate "Qualcomm IPQ806x DWC3 USB PHY driver" + depends on ARCH_QCOM + depends on HAS_IOMEM + depends on OF + select GENERIC_PHY + help + This option enables support for the Synopsis PHYs present inside the + Qualcomm USB3.0 DWC3 controller on ipq806x SoC. This driver supports + both HS and SS PHY controllers. +
drivers/phy/qualcomm/Makefile +1 -0
@@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-qcom-ufs-qmp-14nm.o obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o +obj-$(CONFIG_PHY_QCOM_IPQ806X_USB) += phy-qcom-ipq806x-usb.o
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c new file +583 -0
583 lines not on this page · raw message
Signature · 1 line
2.25.1
PATCH v3 2/2 devicetree: bindings: phy: Document ipq806x dwc3 qcom phy
Document dwc3 qcom phy hs and ss phy bindings needed to correctly inizialize and use usb on ipq806x SoC.
Signed-off-by Ansuel Smith <[email protected]>
---
v3:
* Use explicit reg instead of regmap
.../bindings/phy/qcom,ipq806x-usb-phy-hs.yaml | 58 +++++++++++++++ .../bindings/phy/qcom,ipq806x-usb-phy-ss.yaml | 70 +++++++++++++++++++ 2 files changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml
Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml new file +58 -0
@@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER + +maintainers: + - Ansuel Smith <[email protected]> + +description: + DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer + controllers used in ipq806x. Each DWC3 PHY controller should have its + own node. + +properties: + compatible: + const: qcom,ipq806x-usb-phy-hs + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + description: | + - "ref" Is required + - "xo" Optional external reference clock + items: + - const: ref + - const: xo + +required: + - compatible + - "#phy-cells" + - reg + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-ipq806x.h> + + hs_phy_0: phy@110f8800 { + compatible = "qcom,ipq806x-usb-phy-hs"; + reg = <0x110f8800 0x30>; + clocks = <&gcc USB30_0_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + };
Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml new file +70 -0
70 lines not on this page · raw message
Signature · 1 line
2.25.1
Rob Herring
maintainerRe: [PATCH v3 2/2] devicetree: bindings: phy: Document ipq806x dwc3 qcom phy
Quoted 115 lines · Ansuel Smith
Document dwc3 qcom phy hs and ss phy bindings needed to correctly inizialize and use usb on ipq806x SoC.
Signed-off-by Ansuel Smith <[email protected]>---
v3:
* Use explicit reg instead of regmap.../bindings/phy/qcom,ipq806x-usb-phy-hs.yaml | 58 +++++++++++++++ .../bindings/phy/qcom,ipq806x-usb-phy-ss.yaml | 70 +++++++++++++++++++ 2 files changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yamlDocumentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml new file +58
-0@@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER + +maintainers: + - Ansuel Smith <[email protected]> + +description: + DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer + controllers used in ipq806x. Each DWC3 PHY controller should have its + own node. + +properties: + compatible: + const: qcom,ipq806x-usb-phy-hs + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + description: | + - "ref" Is required + - "xo" Optional external reference clock + items: + - const: ref + - const: xo + +required: + - compatible + - "#phy-cells" + - reg + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-ipq806x.h> + + hs_phy_0: phy@110f8800 { + compatible = "qcom,ipq806x-usb-phy-hs"; + reg = <0x110f8800 0x30>; + clocks = <&gcc USB30_0_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + };Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml new file +31
-0@@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-ss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ipq806x usb DWC3 SS PHY CONTROLLER + +maintainers: + - Ansuel Smith <[email protected]> + +description: + DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer + controllers used in ipq806x. Each DWC3 PHY controller should have its + own node. + +properties: + compatible: + const: qcom,ipq806x-usb-phy-ss + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names:
Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml line 41
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Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml new file +10
-0+ minItems: 1 + maxItems: 2 + description: | + - "ref" Is required + - "xo" Optional external reference clock + items: + - const: ref + - const: xo + + rx_eq:
qcom,rx-eq
Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml line 42
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Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml new file +1
-0+ maxItems: 1
Is this an array?
Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml line 45
Quoted 3 lines
Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml new file +3
-0+ description: Override value for rx_eq. Default is 4. + + tx_deamp_3_5db:
qcom,tx-deamp-3-5db
Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml line 47
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Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml new file +2
-0+ maxItems: 1 + description: Override value for transmit preemphasis. Default is 23.
default: 23
Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml line 49
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Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml new file +2
-0+ + mpll:
qcom,mpll
Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml line 51
Quoted 2 lines
Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml new file +2
-0+ maxItems: 1 + description: Override value for mpll. Default is 0.
Constraints?
default: 0
Quoted 22 lines
Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml new file +19
-0+ +required: + - compatible + - "#phy-cells" + - reg + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-ipq806x.h> + + ss_phy_0: phy@110f8830 { + compatible = "qcom,ipq806x-usb-phy-ss"; + reg = <0x110f8830 0x30>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + };Signature · 1 line
2.25.1