make hdmi work on bananapi-r2

From: Frank Wunderlich <[email protected]>

mt7623 uses mt2701/mt8173 for drm, but have own compatibles

Signed-off-by Frank Wunderlich <[email protected]>

Acked-by Rob Herring <[email protected]>

Reviewed-by Chun-Kuang Hu <[email protected]>

---
 .../devicetree/bindings/display/mediatek/mediatek,disp.txt    | 2 +-
 .../devicetree/bindings/display/mediatek/mediatek,dpi.txt     | 2 +-
 .../devicetree/bindings/display/mediatek/mediatek,dsi.txt     | 4 ++--
 .../devicetree/bindings/display/mediatek/mediatek,hdmi.txt    | 4 ++++
 4 files changed, 8 insertions(+), 4 deletions(-)

Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +1 -1

index b91e709db7a4..121220745d46 100644
@@ -43,7 +43,7 @@ Required properties (all function blocks):
        "mediatek,<chip>-dpi"                   - DPI controller, see mediatek,dpi.txt
        "mediatek,<chip>-disp-mutex"            - display mutex
        "mediatek,<chip>-disp-od"               - overdrive
-  the supported chips are mt2701, mt2712 and mt8173.
+  the supported chips are mt2701, mt7623, mt2712 and mt8173.
 - reg: Physical base address and length of the function block register space
 - interrupts: The interrupt signal from the function block (required, except for
   merge and split function blocks).

Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt +1 -1

index 77def4456706..dc1ebd13cc88 100644
@@ -7,7 +7,7 @@ output bus.
 
 Required properties:
 - compatible: "mediatek,<chip>-dpi"
-  the supported chips are mt2701 , mt8173 and mt8183.
+  the supported chips are mt2701, mt7623, mt8173 and mt8183.
 - reg: Physical base address and length of the controller's registers
 - interrupts: The interrupt signal from the function block.
 - clocks: device clocks

Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +2 -2

index 8e4729de8c85..f06f24d405a5 100644
@@ -7,7 +7,7 @@ channel output.
 
 Required properties:
 - compatible: "mediatek,<chip>-dsi"
-  the supported chips are mt2701, mt8173 and mt8183.
+- the supported chips are mt2701, mt7623, mt8173 and mt8183.
 - reg: Physical base address and length of the controller's registers
 - interrupts: The interrupt signal from the function block.
 - clocks: device clocks

@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
 
 Required properties:
 - compatible: "mediatek,<chip>-mipi-tx"
-  the supported chips are mt2701, mt8173 and mt8183.
+- the supported chips are mt2701, 7623, mt8173 and mt8183.
 - reg: Physical base address and length of the controller's registers
 - clocks: PLL reference clock
 - clock-output-names: name of the output clock line to the DSI encoder

Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt +4 -1

index 7b124242b0c5..6b1c586403e4 100644
@@ -6,6 +6,7 @@ its parallel input.
 
 Required properties:
 - compatible: Should be "mediatek,<chip>-hdmi".
+- the supported chips are mt2701, mt7623 and mt8173
 - reg: Physical base address and length of the controller's registers
 - interrupts: The interrupt signal from the function block.
 - clocks: device clocks

@@ -32,6 +33,7 @@ The HDMI CEC controller handles hotplug detection and CEC communication.
 
 Required properties:
 - compatible: Should be "mediatek,<chip>-cec"
+- the supported chips are mt7623 and mt8173
 - reg: Physical base address and length of the controller's registers
 - interrupts: The interrupt signal from the function block.
 - clocks: device clock

@@ -44,6 +46,7 @@ The Mediatek's I2C controller is used to interface with I2C devices.
 
 Required properties:
 - compatible: Should be "mediatek,<chip>-hdmi-ddc"
+- the supported chips are mt7623 and mt8173
 - reg: Physical base address and length of the controller's registers
 - clocks: device clock
 - clock-names: Should be "ddc-i2c".

@@ -56,6 +59,7 @@ output and drives the HDMI pads.
 
 Required properties:
 - compatible: "mediatek,<chip>-hdmi-phy"
+- the supported chips are mt2701, mt7623 and mt8173
 - reg: Physical base address and length of the module's registers
 - clocks: PLL reference clock
 - clock-names: must contain "pll_ref"
--

2.25.1

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From: Frank Wunderlich <[email protected]>

on BPi-R2/mt7623 main-path have to be routed to DPI0 (hdmi) instead of DSI0 using compatible "mt7623-mmsys" already defined in dts

Signed-off-by Frank Wunderlich <[email protected]>

Reviewed-by Chun-Kuang Hu <[email protected]>

---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

drivers/gpu/drm/mediatek/mtk_drm_drv.c +23 -1

index 040a8f393fe2..2350e3200b59 100644
@@ -74,6 +74,19 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
        DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt7623_mtk_ddp_main[] = {
+       DDP_COMPONENT_OVL0,
+       DDP_COMPONENT_RDMA0,
+       DDP_COMPONENT_COLOR0,
+       DDP_COMPONENT_BLS,
+       DDP_COMPONENT_DPI0,
+};
+
+static const enum mtk_ddp_comp_id mt7623_mtk_ddp_ext[] = {
+       DDP_COMPONENT_RDMA1,
+       DDP_COMPONENT_DSI0,
+};
+
 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = {
        DDP_COMPONENT_OVL0,
        DDP_COMPONENT_COLOR0,

@@ -127,6 +140,14 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
        .shadow_register = true,
 };
 
+static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
+       .main_path = mt7623_mtk_ddp_main,
+       .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
+       .ext_path = mt7623_mtk_ddp_ext,
+       .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
+       .shadow_register = true,
+};
+
 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
        .main_path = mt2712_mtk_ddp_main,
        .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),

@@ -422,6 +443,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 static const struct of_device_id mtk_drm_of_ids[] = {
        { .compatible = "mediatek,mt2701-mmsys",
          .data = &mt2701_mmsys_driver_data},
+       { .compatible = "mediatek,mt7623-mmsys",
+         .data = &mt7623_mmsys_driver_data},
        { .compatible = "mediatek,mt2712-mmsys",
          .data = &mt2712_mmsys_driver_data},
        { .compatible = "mediatek,mt8173-mmsys",
--

2.25.1

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From: chunhui dai <[email protected]>

disable tmds on phy on mt2701 to support other resolutions like 1280x1024

Signed-off-by chunhui dai <[email protected]>

Signed-off-by Frank Wunderlich <[email protected]>

Tested-by Frank Wunderlich <[email protected]>

---
  drivers/gpu/drm/mediatek/mtk_hdmi_phy.c        | 3 +++
  drivers/gpu/drm/mediatek/mtk_hdmi_phy.h        | 1 +
  drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 1 +
  3 files changed, 5 insertions(+)

drivers/gpu/drm/mediatek/mtk_hdmi_phy.c +3 -0

index 5223498502c4..edadb7a700f1 100644
@@ -184,6 +184,9 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev)
  		return PTR_ERR(phy_provider);
  	}
 
+	if (hdmi_phy->conf->pll_default_off)
+		hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
+
  	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
  				   hdmi_phy->pll);
  }

drivers/gpu/drm/mediatek/mtk_hdmi_phy.h +1 -0

index 2d8b3182470d..f472fdeb63dc 100644
@@ -22,6 +22,7 @@ struct mtk_hdmi_phy;
  struct mtk_hdmi_phy_conf {
  	bool tz_disabled;
  	unsigned long flags;
+	bool pll_default_off;
  	const struct clk_ops *hdmi_phy_clk_ops;
  	void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
  	void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy);

drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c +0 -0

index d3cc4022e988..6fbedacfc1e8 100644

Isn't that worth a Fixes tag?

Gesendet: Mittwoch, 19. August 2020 um 21:04 Uhr
Von: "Frank Wunderlich" <[email protected]>
Another way to fix it maybe not enabling it (use the flag in mtk_hdmi_phy_power_on) there instead of disabling after enabling it.

Maybe this is less hacky than current way (as ck hu pointed in v2).

drivers/gpu/drm/mediatek/mtk_hdmi_phy.c +0 -0

index 5223498502c4..edadb7a700f1 100644

Quoted 5 lines

drivers/gpu/drm/mediatek/mtk_hdmi_phy.c +0 -0

index 5223498502c4..edadb7a700f1 100644

drivers/gpu/drm/mediatek/mtk_hdmi_phy.c static int mtk_hdmi_phy_probe(struct platform_device *pdev) · line 192

Quoted 9 lines

drivers/gpu/drm/mediatek/mtk_hdmi_phy.c +3 -0

@@ -184,6 +184,9 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev)
  		return PTR_ERR(phy_provider);
  	}
 
+	if (hdmi_phy->conf->pll_default_off)
+		hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
+
  	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
  				   hdmi_phy->pll);
  }

tried modifying mtk_hdmi_phy_power_on using the new flag to not enable tmds instead of enabling and later disabling it, but this does not work...

drivers/gpu/drm/mediatek/mtk_hdmi_phy.c +4 -3

@@ -62,7 +62,8 @@ static int mtk_hdmi_phy_power_on(struct phy *phy)
         if (ret < 0)
                 return ret;
 
-       hdmi_phy->conf->hdmi_phy_enable_tmds(hdmi_phy);
+       if (!hdmi_phy->conf->pll_default_off)
+               hdmi_phy->conf->hdmi_phy_enable_tmds(hdmi_phy);
         return 0;
  }
 

@@ -184,8 +185,8 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev)
                 return PTR_ERR(phy_provider);
         }
 
-       if (hdmi_phy->conf->pll_default_off)
-               hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
+       //if (hdmi_phy->conf->pll_default_off)
+       //      hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
 
         return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
                                    hdmi_phy->pll);

same problem as without this Patch (horizontally distorted image flickering on 1280x1024)

any idea CK Hu?

Hi Matthias,

any opinions about the dts-changes?

maybe series except the tmds-Patch get merged...so i add it only to my own repo till we find a better way?
currently mainline does not support hdmi at all for the board. the tmds-patch is only a fix for specific resolutions which have a "flickering" without this Patch.

Quoted 4 lines

Hi Matthias,

any opinions about the dts-changes?

they look good to me.

Quoted 3 lines

maybe series except the tmds-Patch get merged...so i add it only to my own repo till we find a better way?
currently mainline does not support hdmi at all for the board. the tmds-patch is only a fix for specific resolutions which have a "flickering" without this Patch.

Well let's see what CK's opinion.

Regards,
Matthias

Hi, Frank:

Matthias Brugger <[email protected]> 於 2020年8月27日 週四 下午10:28寫道：

Quoted 12 lines · Frank Wunderlich

Quoted 4 lines

Hi Matthias,

any opinions about the dts-changes?

they look good to me.

Quoted 1 line

maybe series except the tmds-Patch get merged...so i add it only to

my own repo till we find a better way?

Quoted 1 line

Quoted 1 line

currently mainline does not support hdmi at all for the board. the

tmds-patch is only a fix for specific resolutions which have a "flickering" without this Patch.

Quoted 4 lines

Quoted 1 line

Well let's see what CK's opinion.

Because no one has comment on this patch, I could apply this patch but I need you to add more experiment information so if someone meets another bug, he could fix his bug and consider your problem.

Regards,
Chun-Kuang.

Quoted 2 lines

Regards,
Matthias

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Hi, Frank:

Matthias Brugger <[email protected]> 於 2020年8月27日 週四 下午10:28寫道：

Quoted 15 lines · Frank Wunderlich

Quoted 4 lines

Hi Matthias,

any opinions about the dts-changes?

they look good to me.

Quoted 3 lines

maybe series except the tmds-Patch get merged...so i add it only to my own repo till we find a better way?
currently mainline does not support hdmi at all for the board. the tmds-patch is only a fix for specific resolutions which have a "flickering" without this Patch.

Quoted 2 lines

Well let's see what CK's opinion.

Because no one has comment on this patch, I could apply this patch but I need you to add more experiment information so if someone meets another bug, he could fix his bug and consider your problem.

From: Jitao Shi <[email protected]>

For current mediatek dsi encoder, its possible crtc is fixed in crtc 0, and mediatek dpi encoder's possible crtc is fixed in crtc 1. In some SoC the possible crtc is not fixed in this case, so call mtk_drm_find_possible_crtc_by_comp() to find out the correct possible crtc.

Signed-off-by Jitao Shi <[email protected]>

Signed-off-by Frank Wunderlich <[email protected]>

Reviewed-by Chun-Kuang Hu <[email protected]>

---
  drivers/gpu/drm/mediatek/mtk_dpi.c | 3 ++-
  drivers/gpu/drm/mediatek/mtk_dsi.c | 3 ++-
  2 files changed, 4 insertions(+), 2 deletions(-)

drivers/gpu/drm/mediatek/mtk_dpi.c +2 -1

index d4f0fb7ad312..e43977015843 100644
@@ -608,7 +608,8 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
  	drm_encoder_helper_add(&dpi->encoder, &mtk_dpi_encoder_helper_funcs);
 
  	/* Currently DPI0 is fixed to be driven by OVL1 */
-	dpi->encoder.possible_crtcs = BIT(1);
+	dpi->encoder.possible_crtcs =
+		mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->ddp_comp);
 
  	ret = drm_bridge_attach(&dpi->encoder, dpi->bridge, NULL, 0);
  	if (ret) {

drivers/gpu/drm/mediatek/mtk_dsi.c +0 -0

index 16fd99dcdacf..c9f4ad029cb1 100644

Quoted 8 lines

From: Jitao Shi <[email protected]>

For current mediatek dsi encoder, its possible crtc is fixed in crtc 0, and mediatek dpi encoder's possible crtc is fixed in crtc 1. In some SoC the possible crtc is not fixed in this case, so call mtk_drm_find_possible_crtc_by_comp() to find out the correct possible crtc.

Hm, shouldn't we stash this int 4/7, otherwise we will have not used functions in 4/7.

Regards,
Matthias

Quoted 34 lines

Signed-off-by Jitao Shi <[email protected]>

Signed-off-by Frank Wunderlich <[email protected]>

Reviewed-by Chun-Kuang Hu <[email protected]>

---
  drivers/gpu/drm/mediatek/mtk_dpi.c | 3 ++-
  drivers/gpu/drm/mediatek/mtk_dsi.c | 3 ++-
  2 files changed, 4 insertions(+), 2 deletions(-)

drivers/gpu/drm/mediatek/mtk_dpi.c +2 -1

index d4f0fb7ad312..e43977015843 100644
@@ -608,7 +608,8 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
      drm_encoder_helper_add(&dpi->encoder, &mtk_dpi_encoder_helper_funcs);
 
      /* Currently DPI0 is fixed to be driven by OVL1 */
-     dpi->encoder.possible_crtcs = BIT(1);
+     dpi->encoder.possible_crtcs =
+             mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->ddp_comp);
 
      ret = drm_bridge_attach(&dpi->encoder, dpi->bridge, NULL, 0);
      if (ret) {

drivers/gpu/drm/mediatek/mtk_dsi.c +2 -1

index 16fd99dcdacf..c9f4ad029cb1 100644
@@ -974,7 +974,8 @@ static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi)
       * Currently display data paths are statically assigned to a crtc each.
       * crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0
       */
-     dsi->encoder.possible_crtcs = 1;
+     dsi->encoder.possible_crtcs =
+             mtk_drm_find_possible_crtc_by_comp(drm, dsi->ddp_comp);
 

drivers/gpu/drm/mediatek/mtk_dsi.c static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi) · line 981

Quoted 3 lines

drivers/gpu/drm/mediatek/mtk_dsi.c +0 -0

      ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL,
                              DRM_BRIDGE_ATTACH_NO_CONNECTOR);

From: Frank Wunderlich <[email protected]>

mt7623a has no graphics support so move nodes from generic mt7623.dtsi to mt7623n.dtsi

Fixes 1f6ed224594 ("arm: dts: mt7623: add Mali-450 device node")

Suggested-by David Woodhouse <[email protected]>

Signed-off-by Frank Wunderlich <[email protected]>

---
  arch/arm/boot/dts/mt7623.dtsi                 | 123 ----------------
  arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts |   2 +-
  arch/arm/boot/dts/mt7623n-rfb-emmc.dts        |   2 +-
  arch/arm/boot/dts/mt7623n.dtsi                | 134 ++++++++++++++++++
  4 files changed, 136 insertions(+), 125 deletions(-)

create mode 100644 arch/arm/boot/dts/mt7623n.dtsi

arch/arm/boot/dts/mt7623.dtsi +0 -123

index a106c0d90a52..d09b5671c91b 100644
@@ -14,7 +14,6 @@
  #include <dt-bindings/power/mt2701-power.h>
  #include <dt-bindings/gpio/gpio.h>
  #include <dt-bindings/phy/phy.h>
-#include <dt-bindings/memory/mt2701-larb-port.h>
  #include <dt-bindings/reset/mt2701-resets.h>
  #include <dt-bindings/thermal/thermal.h>
 

@@ -297,17 +296,6 @@ timer: timer@10008000 {
  		clock-names = "system-clk", "rtc-clk";
  	};
 
-	smi_common: smi@1000c000 {
-		compatible = "mediatek,mt7623-smi-common",
-			     "mediatek,mt2701-smi-common";
-		reg = <0 0x1000c000 0 0x1000>;
-		clocks = <&infracfg CLK_INFRA_SMI>,
-			 <&mmsys CLK_MM_SMI_COMMON>,
-			 <&infracfg CLK_INFRA_SMI>;
-		clock-names = "apb", "smi", "async";
-		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
-	};
-
  	pwrap: pwrap@1000d000 {
  		compatible = "mediatek,mt7623-pwrap",
  			     "mediatek,mt2701-pwrap";

@@ -339,17 +327,6 @@ sysirq: interrupt-controller@10200100 {
  		reg = <0 0x10200100 0 0x1c>;
  	};
 
-	iommu: mmsys_iommu@10205000 {
-		compatible = "mediatek,mt7623-m4u",
-			     "mediatek,mt2701-m4u";
-		reg = <0 0x10205000 0 0x1000>;
-		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&infracfg CLK_INFRA_M4U>;
-		clock-names = "bclk";
-		mediatek,larbs = <&larb0 &larb1 &larb2>;
-		#iommu-cells = <1>;
-	};
-
  	efuse: efuse@10206000 {
  		compatible = "mediatek,mt7623-efuse",
  			     "mediatek,mt8173-efuse";

@@ -725,94 +702,6 @@ mmc0: mmc@11230000 {
  		status = "disabled";
  	};
 
-	g3dsys: syscon@13000000 {
-		compatible = "mediatek,mt7623-g3dsys",
-			     "mediatek,mt2701-g3dsys",
-			     "syscon";
-		reg = <0 0x13000000 0 0x200>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
-
-	mali: gpu@13040000 {
-		compatible = "mediatek,mt7623-mali", "arm,mali-450";
-		reg = <0 0x13040000 0 0x30000>;
-		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
-				  "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",
-				  "pp";
-		clocks = <&topckgen CLK_TOP_MMPLL>,
-			 <&g3dsys CLK_G3DSYS_CORE>;
-		clock-names = "bus", "core";
-		power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
-		resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
-	};
-
-	mmsys: syscon@14000000 {
-		compatible = "mediatek,mt7623-mmsys",
-			     "mediatek,mt2701-mmsys",
-			     "syscon";
-		reg = <0 0x14000000 0 0x1000>;
-		#clock-cells = <1>;
-	};
-
-	larb0: larb@14010000 {
-		compatible = "mediatek,mt7623-smi-larb",
-			     "mediatek,mt2701-smi-larb";
-		reg = <0 0x14010000 0 0x1000>;
-		mediatek,smi = <&smi_common>;
-		mediatek,larb-id = <0>;
-		clocks = <&mmsys CLK_MM_SMI_LARB0>,
-			 <&mmsys CLK_MM_SMI_LARB0>;
-		clock-names = "apb", "smi";
-		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
-	};
-
-	imgsys: syscon@15000000 {
-		compatible = "mediatek,mt7623-imgsys",
-			     "mediatek,mt2701-imgsys",
-			     "syscon";
-		reg = <0 0x15000000 0 0x1000>;
-		#clock-cells = <1>;
-	};
-
-	larb2: larb@15001000 {
-		compatible = "mediatek,mt7623-smi-larb",
-			     "mediatek,mt2701-smi-larb";
-		reg = <0 0x15001000 0 0x1000>;
-		mediatek,smi = <&smi_common>;
-		mediatek,larb-id = <2>;
-		clocks = <&imgsys CLK_IMG_SMI_COMM>,
-			 <&imgsys CLK_IMG_SMI_COMM>;
-		clock-names = "apb", "smi";
-		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
-	};
-
-	jpegdec: jpegdec@15004000 {
-		compatible = "mediatek,mt7623-jpgdec",
-			     "mediatek,mt2701-jpgdec";
-		reg = <0 0x15004000 0 0x1000>;
-		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
-		clocks =  <&imgsys CLK_IMG_JPGDEC_SMI>,
-			  <&imgsys CLK_IMG_JPGDEC>;
-		clock-names = "jpgdec-smi",
-			      "jpgdec";
-		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
-		mediatek,larb = <&larb2>;
-		iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
-			 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
-	};
-
  	vdecsys: syscon@16000000 {
  		compatible = "mediatek,mt7623-vdecsys",
  			     "mediatek,mt2701-vdecsys",

@@ -821,18 +710,6 @@ vdecsys: syscon@16000000 {
  		#clock-cells = <1>;
  	};
 
-	larb1: larb@16010000 {
-		compatible = "mediatek,mt7623-smi-larb",
-			     "mediatek,mt2701-smi-larb";
-		reg = <0 0x16010000 0 0x1000>;
-		mediatek,smi = <&smi_common>;
-		mediatek,larb-id = <1>;
-		clocks = <&vdecsys CLK_VDEC_CKGEN>,
-			 <&vdecsys CLK_VDEC_LARB>;
-		clock-names = "apb", "smi";
-		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
-	};
-
  	hifsys: syscon@1a000000 {
  		compatible = "mediatek,mt7623-hifsys",
  			     "mediatek,mt2701-hifsys",

arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +1 -1

index 2b760f90f38c..344f8c65c4aa 100644
@@ -6,7 +6,7 @@
 
  /dts-v1/;
  #include <dt-bindings/input/input.h>
-#include "mt7623.dtsi"
+#include "mt7623n.dtsi"
  #include "mt6323.dtsi"
 
  / {

arch/arm/boot/dts/mt7623n-rfb-emmc.dts +1 -1

index 0447748f9fa0..f8efcc364bc3 100644
@@ -7,7 +7,7 @@
 
  /dts-v1/;
  #include <dt-bindings/input/input.h>
-#include "mt7623.dtsi"
+#include "mt7623n.dtsi"
  #include "mt6323.dtsi"
 
  / {

arch/arm/boot/dts/mt7623n.dtsi new file +124 -0

new file mode 100644
index 000000000000..a47e82468895
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2017-2020 MediaTek Inc.
+ * Author: Sean Wang <[email protected]>
+ *	   Ryder Lee <[email protected]>
+ *
+ */
+
+#include "mt7623.dtsi"
+#include <dt-bindings/memory/mt2701-larb-port.h>
+
+/ {
+	g3dsys: syscon@13000000 {
+		compatible = "mediatek,mt7623-g3dsys",
+			     "mediatek,mt2701-g3dsys",
+			     "syscon";
+		reg = <0 0x13000000 0 0x200>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	mali: gpu@13040000 {
+		compatible = "mediatek,mt7623-mali", "arm,mali-450";
+		reg = <0 0x13040000 0 0x30000>;
+		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
+				  "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",
+				  "pp";
+		clocks = <&topckgen CLK_TOP_MMPLL>,
+			 <&g3dsys CLK_G3DSYS_CORE>;
+		clock-names = "bus", "core";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
+		resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
+	};
+
+	mmsys: syscon@14000000 {
+		compatible = "mediatek,mt7623-mmsys",
+			     "mediatek,mt2701-mmsys",
+			     "syscon";
+		reg = <0 0x14000000 0 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	larb0: larb@14010000 {
+		compatible = "mediatek,mt7623-smi-larb",
+			     "mediatek,mt2701-smi-larb";
+		reg = <0 0x14010000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		mediatek,larb-id = <0>;
+		clocks = <&mmsys CLK_MM_SMI_LARB0>,
+			 <&mmsys CLK_MM_SMI_LARB0>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+	};
+
+	larb1: larb@16010000 {
+		compatible = "mediatek,mt7623-smi-larb",
+			     "mediatek,mt2701-smi-larb";
+		reg = <0 0x16010000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		mediatek,larb-id = <1>;
+		clocks = <&vdecsys CLK_VDEC_CKGEN>,
+			 <&vdecsys CLK_VDEC_LARB>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
+	};
+
+	larb2: larb@15001000 {
+		compatible = "mediatek,mt7623-smi-larb",
+			     "mediatek,mt2701-smi-larb";
+		reg = <0 0x15001000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		mediatek,larb-id = <2>;
+		clocks = <&imgsys CLK_IMG_SMI_COMM>,
+			 <&imgsys CLK_IMG_SMI_COMM>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+	};
+
+	imgsys: syscon@15000000 {
+		compatible = "mediatek,mt7623-imgsys",
+			     "mediatek,mt2701-imgsys",
+			     "syscon";
+		reg = <0 0x15000000 0 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	iommu: mmsys_iommu@10205000 {
+		compatible = "mediatek,mt7623-m4u",
+			     "mediatek,mt2701-m4u";
+		reg = <0 0x10205000 0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&infracfg CLK_INFRA_M4U>;
+		clock-names = "bclk";
+		mediatek,larbs = <&larb0 &larb1 &larb2>;
+		#iommu-cells = <1>;
+	};
+
+	jpegdec: jpegdec@15004000 {
+		compatible = "mediatek,mt7623-jpgdec",
+			     "mediatek,mt2701-jpgdec";
+		reg = <0 0x15004000 0 0x1000>;
+		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
+		clocks =  <&imgsys CLK_IMG_JPGDEC_SMI>,
+			  <&imgsys CLK_IMG_JPGDEC>;
+		clock-names = "jpgdec-smi",
+			      "jpgdec";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+		mediatek,larb = <&larb2>;
+		iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
+			 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
+	};
+
+	smi_common: smi@1000c000 {

Quoted 2 lines · Frank Wunderlich

From: Frank Wunderlich <[email protected]>

Quoted 6 lines

mt7623a has no graphics support so move nodes from generic mt7623.dtsi to mt7623n.dtsi

Fixes 1f6ed224594 ("arm: dts: mt7623: add Mali-450 device node")

Suggested-by David Woodhouse <[email protected]>

Signed-off-by Frank Wunderlich <[email protected]>

Applied to v5.9-next/dts32

From: Ryder Lee <[email protected]>

Add display subsystem related device nodes for MT7623.

Cc Chun-Kuang Hu <[email protected]>

Signed-off-by chunhui dai <[email protected]>

Signed-off-by Bibby Hsieh <[email protected]>

Signed-off-by Ryder Lee <[email protected]>

Signed-off-by Frank Wunderlich <[email protected]>

Tested-by Frank Wunderlich <[email protected]>

---
changed
v4->v5:
add nodes to new mt7623n.dtsi to avoid conflict with mt7623a
v3->v4:
drop display_components which is duplicate of existing mmsys
v2->v3:
drop bls to dpi routing

---
  arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts |  72 ++++++++
  arch/arm/boot/dts/mt7623n-rfb-emmc.dts        |  72 ++++++++
  arch/arm/boot/dts/mt7623n.dtsi                | 171 ++++++++++++++++++
  3 files changed, 315 insertions(+)

arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +72 -0

index 344f8c65c4aa..f41f221e56ca 100644
@@ -21,6 +21,19 @@ chosen {
  		stdout-path = "serial2:115200n8";
  	};
 
+	connector {
+		compatible = "hdmi-connector";
+		label = "hdmi";
+		type = "d";
+		ddc-i2c-bus = <&hdmiddc0>;
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&hdmi0_out>;
+			};
+		};
+	};
+
  	cpus {
  		cpu@0 {
  			proc-supply = <&mt6323_vproc_reg>;

@@ -114,10 +127,18 @@ memory@80000000 {
  	};
  };
 
+&bls {
+	status = "okay";
+};
+
  &btif {
  	status = "okay";
  };
 
+&cec {
+	status = "okay";
+};
+
  &cir {
  	pinctrl-names = "default";
  	pinctrl-0 = <&cir_pins_a>;

@@ -128,6 +149,21 @@ &crypto {
  	status = "okay";
  };
 
+&dpi0 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			dpi0_out: endpoint {
+				remote-endpoint = <&hdmi0_in>;
+			};
+		};
+	};
+};
+
  &eth {
  	status = "okay";
 

@@ -199,6 +235,42 @@ fixed-link {
  	};
  };
 
+&hdmi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_pins_a>;
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			hdmi0_in: endpoint {
+				remote-endpoint = <&dpi0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			hdmi0_out: endpoint {
+				remote-endpoint = <&hdmi_connector_in>;
+			};
+		};
+	};
+};
+
+&hdmiddc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_ddc_pins_a>;
+	status = "okay";
+};
+
+&hdmi_phy {
+	mediatek,ibias = <0xa>;
+	mediatek,ibias_up = <0x1c>;
+	status = "okay";
+};
+
  &i2c0 {
  	pinctrl-names = "default";
  	pinctrl-0 = <&i2c0_pins_a>;

arch/arm/boot/dts/mt7623n-rfb-emmc.dts +72 -0

index f8efcc364bc3..1b9b9a8145a7 100644
@@ -24,6 +24,19 @@ chosen {
  		stdout-path = "serial2:115200n8";
  	};
 
+	connector {
+		compatible = "hdmi-connector";
+		label = "hdmi";
+		type = "d";
+		ddc-i2c-bus = <&hdmiddc0>;
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&hdmi0_out>;
+			};
+		};
+	};
+
  	cpus {
  		cpu@0 {
  			proc-supply = <&mt6323_vproc_reg>;

@@ -106,10 +119,18 @@ sound {
  	};
  };
 
+&bls {
+	status = "okay";
+};
+
  &btif {
  	status = "okay";
  };
 
+&cec {
+	status = "okay";
+};
+
  &cir {
  	pinctrl-names = "default";
  	pinctrl-0 = <&cir_pins_a>;

@@ -120,6 +141,21 @@ &crypto {
  	status = "okay";
  };
 
+&dpi0 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			dpi0_out: endpoint {
+				remote-endpoint = <&hdmi0_in>;
+			};
+		};
+	};
+};
+
  &eth {
  	status = "okay";
 

@@ -203,6 +239,42 @@ fixed-link {
  	};
  };
 
+&hdmi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_pins_a>;
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			hdmi0_in: endpoint {
+				remote-endpoint = <&dpi0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			hdmi0_out: endpoint {
+				remote-endpoint = <&hdmi_connector_in>;
+			};
+		};
+	};
+};
+
+&hdmiddc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_ddc_pins_a>;
+	status = "okay";
+};
+
+&hdmi_phy {
+	mediatek,ibias = <0xa>;
+	mediatek,ibias_up = <0x1c>;
+	status = "okay";
+};
+
  &i2c0 {
  	pinctrl-names = "default";
  	pinctrl-0 = <&i2c0_pins_a>;

arch/arm/boot/dts/mt7623n.dtsi +162 -0

index a47e82468895..61545fc541c4 100644
@@ -10,6 +10,10 @@
  #include <dt-bindings/memory/mt2701-larb-port.h>
 
  / {
+	aliases {
+		rdma0 = &rdma0;
+		rdma1 = &rdma1;
+	};
  	g3dsys: syscon@13000000 {
  		compatible = "mediatek,mt7623-g3dsys",
  			     "mediatek,mt2701-g3dsys",

@@ -131,4 +135,171 @@ smi_common: smi@1000c000 {
  		clock-names = "apb", "smi", "async";
  		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
  	};
+
+	ovl: ovl@14007000 {
+		compatible = "mediatek,mt7623-disp-ovl",
+			     "mediatek,mt2701-disp-ovl";
+		reg = <0 0x14007000 0 0x1000>;
+		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&mmsys CLK_MM_DISP_OVL>;
+		iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
+		mediatek,larb = <&larb0>;
+	};
+
+	rdma0: rdma@14008000 {
+		compatible = "mediatek,mt7623-disp-rdma",
+			     "mediatek,mt2701-disp-rdma";
+		reg = <0 0x14008000 0 0x1000>;
+		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&mmsys CLK_MM_DISP_RDMA>;
+		iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
+		mediatek,larb = <&larb0>;
+	};
+
+	wdma@14009000 {
+		compatible = "mediatek,mt7623-disp-wdma",
+			     "mediatek,mt2701-disp-wdma";
+		reg = <0 0x14009000 0 0x1000>;
+		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&mmsys CLK_MM_DISP_WDMA>;
+		iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
+		mediatek,larb = <&larb0>;
+	};
+
+	bls: pwm@1400a000 {
+		compatible = "mediatek,mt7623-disp-pwm",
+			     "mediatek,mt2701-disp-pwm";
+		reg = <0 0x1400a000 0 0x1000>;
+		#pwm-cells = <2>;
+		clocks = <&mmsys CLK_MM_MDP_BLS_26M>,
+			 <&mmsys CLK_MM_DISP_BLS>;
+		clock-names = "main", "mm";
+		status = "disabled";
+	};
+
+	color: color@1400b000 {
+		compatible = "mediatek,mt7623-disp-color",
+			     "mediatek,mt2701-disp-color";
+		reg = <0 0x1400b000 0 0x1000>;
+		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&mmsys CLK_MM_DISP_COLOR>;
+	};
+
+	dsi: dsi@1400c000 {
+		compatible = "mediatek,mt7623-dsi",
+			     "mediatek,mt2701-dsi";
+		reg = <0 0x1400c000 0 0x1000>;
+		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&mmsys CLK_MM_DSI_ENGINE>,
+			 <&mmsys CLK_MM_DSI_DIG>,
+			 <&mipi_tx0>;
+		clock-names = "engine", "digital", "hs";
+		phys = <&mipi_tx0>;
+		phy-names = "dphy";
+		status = "disabled";
+	};
+
+	mutex: mutex@1400e000 {
+		compatible = "mediatek,mt7623-disp-mutex",
+			     "mediatek,mt2701-disp-mutex";
+		reg = <0 0x1400e000 0 0x1000>;
+		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&mmsys CLK_MM_MUTEX_32K>;
+	};
+
+	rdma1: rdma@14012000 {
+		compatible = "mediatek,mt7623-disp-rdma",
+			     "mediatek,mt2701-disp-rdma";
+		reg = <0 0x14012000 0 0x1000>;
+		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+		iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
+		mediatek,larb = <&larb0>;
+	};
+
+	dpi0: dpi@14014000 {
+		compatible = "mediatek,mt7623-dpi",
+			     "mediatek,mt2701-dpi";
+		reg = <0 0x14014000 0 0x1000>;
+		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&mmsys CLK_MM_DPI1_DIGL>,
+			 <&mmsys CLK_MM_DPI1_ENGINE>,
+			 <&apmixedsys CLK_APMIXED_TVDPLL>;
+		clock-names = "pixel", "engine", "pll";
+		status = "disabled";
+	};
+
+	hdmi0: hdmi@14015000 {
+		compatible = "mediatek,mt7623-hdmi",
+			     "mediatek,mt8173-hdmi";
+		reg = <0 0x14015000 0 0x400>;
+		clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+			 <&mmsys CLK_MM_HDMI_PLL>,
+			 <&mmsys CLK_MM_HDMI_AUDIO>,
+			 <&mmsys CLK_MM_HDMI_SPDIF>;
+		clock-names = "pixel", "pll", "bclk", "spdif";
+		phys = <&hdmi_phy>;
+		phy-names = "hdmi";
+		mediatek,syscon-hdmi = <&mmsys 0x900>;
+		cec = <&cec>;
+		status = "disabled";
+	};
+
+	mipi_tx0: mipi-dphy@10010000 {
+		compatible = "mediatek,mt7623-mipi-tx",
+			     "mediatek,mt2701-mipi-tx";
+		reg = <0 0x10010000 0 0x90>;
+		clocks = <&clk26m>;
+		clock-output-names = "mipi_tx0_pll";
+		#clock-cells = <0>;
+		#phy-cells = <0>;
+	};
+
+	cec: cec@10012000 {
+		compatible = "mediatek,mt7623-cec",
+			     "mediatek,mt8173-cec";
+		reg = <0 0x10012000 0 0xbc>;
+		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&infracfg CLK_INFRA_CEC>;
+		status = "disabled";
+	};
+
+	hdmi_phy: phy@10209100 {
+		compatible = "mediatek,mt7623-hdmi-phy",
+			     "mediatek,mt2701-hdmi-phy";
+		reg = <0 0x10209100 0 0x24>;
+		clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+		clock-names = "pll_ref";
+		clock-output-names = "hdmitx_dig_cts";
+		#clock-cells = <0>;
+		#phy-cells = <0>;
+		status = "disabled";
+	};
+
+	hdmiddc0: i2c@11013000 {
+		compatible = "mediatek,mt7623-hdmi-ddc",
+			     "mediatek,mt8173-hdmi-ddc";
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
+		reg = <0 0x11013000 0 0x1C>;
+		clocks = <&pericfg CLK_PERI_I2C3>;
+		clock-names = "ddc-i2c";
+		status = "disabled";
+	};
+};
+
+&pio {
+	hdmi_pins_a: hdmi-default {
+		pins-hdmi {
+			pinmux = <MT7623_PIN_123_HTPLG_FUNC_HTPLG>;
+			input-enable;
+			bias-pull-down;

Hi

Any opinion about DTS Patches? Which maintainer will include it in tree? Is any ack/review needed?

regards Frank