Remove struct pcie_link_state and aspm_register_info

RFC PATCH New Saheed O. Bolarinwa 1 participant 24 messages Aug 22, 2020 PCI

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Saheed O. Bolarinwa

author

2020-08-22 21:03 UTC #0 lore raw

v5 cover Remove struct pcie_link_state and aspm_register_info

This series removes struct pcie_link_state and struct aspm_register_info and reoganise the code in a require.

MERGE:
Please don't merge yet

ToDo
- Remove redundant functions like get_link_state()
- Are locks still needed?
- A few cleanups
- Look for any other redundant code

Saheed O. Bolarinwa (23):
PCI: Migrate ASPM info from struct pcie_link_state to struct pci_dev
PCI: Add l1ss_cap and l1ss_cap_ptr to struct pci_dev
PCI: Rework calc_l*_latency() to take a pci_dev *
PCI: Compute aspm_register_info.support directly
PCI: Read value of aspm_register_info.l1ss_ctl1 directly
PCI: Replace aspm_register_info.l1ss_cap* with their pci_dev version
PCI: Compute aspm_register_info.enable directly
PCI: Remove unused aspm_calc_l1ss_info() arguments
PCI: Remove pcie_get_aspm_reg() and struct aspm_register_info
PCI: Relocate call to aspm_calc_l1ss_info
PCI: Rework and Rename aspm_calc_l1ss_info()
PCI: Add ASPM and CLOCK PM states to struct pci_dev
PCI: Initialise and Update values of pci_dev's PCIe link info
PCI: Change Return and Argument values from pcie_link_state to pci_dev
PCI: Replace pcie_link_state based device list with a pci_dev one
PCI: Remove Exit latencies from struct pcie_link_state
PCI: Remove .clkpm_* from struct pcie_link_state
PCI: Remove .aspm_* from struct pcie_link_state
PCI: Remove .parent from struct pcie_link_state
PCI: Remove .root from struct pcie_link_state
PCI: Remove .downstream from struct pcie_link_state
PCI: Remove .pdev from struct pcie_link_state
PCI: Remove struct pcie_link_state

 drivers/pci/pcie/aspm.c | 570 ++++++++++++++++------------------------
 drivers/pci/probe.c     |   7 +
 include/linux/pci.h     |  37 ++-
 3 files changed, 267 insertions(+), 347 deletions(-)

base-commit: 5f49ff2540e2c2799cde0cfaf6af9e1f824cd393

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Saheed O. Bolarinwa

author

2020-08-22 21:03 UTC #1 lore raw

RFC PATCH v5 1/23 PCI: Migrate ASPM info from struct pcie_link_state to struct pci_dev

pcie_get_aspm_reg() reads LNKCAP to learn whether the device supports ASPM L0s and/or L1 and L1 substates.

If we cache the entire LNKCAP word early enough, we may be able to use it in other places that read LNKCAP, e.g. pcie_get_speed_cap(), pcie_get_width_cap(), pcie_init(), etc.

- Add struct pci_dev.lnkcap (u32)
- Read PCI_EXP_LNKCAP in set_pcie_port_type() and save it in pci_dev.lnkcap
- Use pdev->lnkcap instead of reading PCI_EXP_LNKCAP

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 7 ++-----
 drivers/pci/probe.c     | 1 +
 include/linux/pci.h     | 1 +
 3 files changed, 4 insertions(+), 5 deletions(-)

drivers/pci/pcie/aspm.c +2 -5

index b17e5ffd31b1..3ada61828014 100644
@@ -177,15 +177,13 @@ static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
 static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
 {
 	int capable = 1, enabled = 1;
-	u32 reg32;
 	u16 reg16;
 	struct pci_dev *child;
 	struct pci_bus *linkbus = link->pdev->subordinate;
 
 	/* All functions should have the same cap and state, take the worst */
 	list_for_each_entry(child, &linkbus->devices, bus_list) {
-		pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &reg32);
-		if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
+		if (!(child->lnkcap & PCI_EXP_LNKCAP_CLKPM)) {
 			capable = 0;
 			enabled = 0;
 			break;

@@ -397,9 +395,8 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev,
 			      struct aspm_register_info *info)
 {
 	u16 reg16;
-	u32 reg32;
+	u32 reg32 = pdev->lnkcap;
 
-	pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &reg32);
 	info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
 	info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
 	info->latency_encoding_l1  = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;

drivers/pci/probe.c +1 -0

index 2f66988cea25..6cae7230f3b5 100644
@@ -1480,6 +1480,7 @@ void set_pcie_port_type(struct pci_dev *pdev)
 	pdev->pcie_flags_reg = reg16;
 	pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
 	pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
+	pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &pdev->lnkcap);
 
 	parent = pci_upstream_bridge(pdev);
 	if (!parent)

include/linux/pci.h +1 -0

index 34c1c4f45288..3d30d3650ac9 100644
@@ -375,6 +375,7 @@ struct pci_dev {
 						   bit manually */
 	unsigned int	d3_delay;	/* D3->D0 transition time in ms */
 	unsigned int	d3cold_delay;	/* D3cold->D0 transition time in ms */
+	u32		lnkcap;		/* Link Capabilities */
 
 #ifdef CONFIG_PCIEASPM
 	struct pcie_link_state	*link_state;	/* ASPM link state */

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Saheed O. Bolarinwa

author

2020-08-22 21:03 UTC #2 lore raw

RFC PATCH v5 2/23 PCI: Add l1ss_cap and l1ss_cap_ptr to struct pci_dev

In reply to Saheed O. Bolarinwa

- Add l1ss_cap and l1ss_cap_ptr to struct pci_dev
- Compute the value of pci_dev.l1ss_cap and pci_dev.l1ss_cap_ptr

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/probe.c | 6 ++++++
 include/linux/pci.h | 2 ++
 2 files changed, 8 insertions(+)

drivers/pci/probe.c +6 -0

index 6cae7230f3b5..787ab6e831c7 100644
@@ -2101,6 +2101,12 @@ static void pci_configure_ltr(struct pci_dev *dev)
 	if (!pci_is_pcie(dev))
 		return;
 
+	/* Read L1 PM substate capabilities */
+	dev->l1ss_cap_ptr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
+	if (dev->l1ss_cap_ptr)
+		pci_read_config_dword(dev, dev->l1ss_cap_ptr + PCI_L1SS_CAP,
+								&dev->l1ss_cap);
+
 	pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
 	if (!(cap & PCI_EXP_DEVCAP2_LTR))
 		return;

include/linux/pci.h +2 -0

index 3d30d3650ac9..fa114c5d01e7 100644
@@ -381,6 +381,8 @@ struct pci_dev {
 	struct pcie_link_state	*link_state;	/* ASPM link state */
 	unsigned int	ltr_path:1;	/* Latency Tolerance Reporting
 					   supported from root to here */
+	int		l1ss_cap_ptr;	/* L1SS cap ptr, 0 if not supported */
+	u32		l1ss_cap;	/* L1 PM substate Capabilities */
 #endif
 	unsigned int	eetlp_prefix_path:1;	/* End-to-End TLP Prefix */

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Saheed O. Bolarinwa

author

2020-08-22 21:03 UTC #3 lore raw

RFC PATCH v5 3/23 PCI: Rework calc_l*_latency() to take a pci_dev *

In reply to Saheed O. Bolarinwa

- Change the argument of calc_l0s_latency() to pci_dev *,
- Change the argument of calc_l1_latency() to pci_dev *,
- Compute encodings inside the function
- Change callers to pass in pci_dev *

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

drivers/pci/pcie/aspm.c +10 -6

index 3ada61828014..629737125b36 100644
@@ -306,8 +306,10 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
 }
 
 /* Convert L0s latency encoding to ns */
-static u32 calc_l0s_latency(u32 encoding)
+static u32 calc_l0s_latency(struct pci_dev *pdev)
 {
+	u32 encoding = (pdev->lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
+
 	if (encoding == 0x7)
 		return (5 * 1000);	/* > 4us */
 	return (64 << encoding);

@@ -322,8 +324,10 @@ static u32 calc_l0s_acceptable(u32 encoding)
 }
 
 /* Convert L1 latency encoding to ns */
-static u32 calc_l1_latency(u32 encoding)
+static u32 calc_l1_latency(struct pci_dev *pdev)
 {
+	u32 encoding = (pdev->lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
+
 	if (encoding == 0x7)
 		return (65 * 1000);	/* > 64us */
 	return (1000 << encoding);

@@ -587,16 +591,16 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 		link->aspm_enabled |= ASPM_STATE_L0S_UP;
 	if (upreg.enabled & PCIE_LINK_STATE_L0S)
 		link->aspm_enabled |= ASPM_STATE_L0S_DW;
-	link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
-	link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);
+	link->latency_up.l0s = calc_l0s_latency(parent);
+	link->latency_dw.l0s = calc_l0s_latency(child);
 
 	/* Setup L1 state */
 	if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
 		link->aspm_support |= ASPM_STATE_L1;
 	if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
 		link->aspm_enabled |= ASPM_STATE_L1;
-	link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
-	link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
+	link->latency_up.l1 = calc_l1_latency(parent);
+	link->latency_dw.l1 = calc_l1_latency(child);
 
 	/* Setup L1 substate */
 	if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)

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Saheed O. Bolarinwa

author

2020-08-22 21:03 UTC #4 lore raw

RFC PATCH v5 4/23 PCI: Compute aspm_register_info.support directly

In reply to Saheed O. Bolarinwa

Replace all references to aspm_register_info.support with its computation.

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

drivers/pci/pcie/aspm.c +9 -3

index 629737125b36..64224be52435 100644
@@ -565,7 +565,8 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 	 * If ASPM not supported, don't mess with the clocks and link,
 	 * bail out now.
 	 */
-	if (!(upreg.support & dwreg.support))
+	if (!(((parent->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10) &
+		((child->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10)))
 		return;
 
 	/* Configure common clock before checking latencies */

@@ -585,8 +586,11 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 	 * given link unless components on both sides of the link each
 	 * support L0s.
 	 */
-	if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S)
+	if (((parent->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10) &
+			((child->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10) &
+			PCIE_LINK_STATE_L0S)
 		link->aspm_support |= ASPM_STATE_L0S;
+
 	if (dwreg.enabled & PCIE_LINK_STATE_L0S)
 		link->aspm_enabled |= ASPM_STATE_L0S_UP;
 	if (upreg.enabled & PCIE_LINK_STATE_L0S)

@@ -595,7 +599,9 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 	link->latency_dw.l0s = calc_l0s_latency(child);
 
 	/* Setup L1 state */
-	if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
+	if (((parent->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10) &
+			((child->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10) &
+			PCIE_LINK_STATE_L1)
 		link->aspm_support |= ASPM_STATE_L1;
 	if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
 		link->aspm_enabled |= ASPM_STATE_L1;

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Saheed O. Bolarinwa

author

2020-08-22 21:03 UTC #5 lore raw

RFC PATCH v5 5/23 PCI: Read value of aspm_register_info.l1ss_ctl1 directly

In reply to Saheed O. Bolarinwa

Read the value of PCI_L1SS_CTL1 directly and cache in local variables. Replace references to aspm_register_info.l1ss_ctl1 with the variables.

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

drivers/pci/pcie/aspm.c +10 -4

index 64224be52435..d622affdbbcc 100644
@@ -549,6 +549,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 	struct pci_dev *child = link->downstream, *parent = link->pdev;
 	struct pci_bus *linkbus = parent->subordinate;
 	struct aspm_register_info upreg, dwreg;
+	u32 up_l1ss_ctl1, dw_l1ss_ctl1;
 
 	if (blacklist) {
 		/* Set enabled/disable so that we will disable ASPM later */

@@ -572,6 +573,11 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 	/* Configure common clock before checking latencies */
 	pcie_aspm_configure_common_clock(link);
 
+	pci_read_config_dword(parent, parent->l1ss_cap_ptr + PCI_L1SS_CTL1,
+				&up_l1ss_ctl1);
+	pci_read_config_dword(child, child->l1ss_cap_ptr + PCI_L1SS_CTL1,
+				&dw_l1ss_ctl1);
+
 	/*
 	 * Re-read upstream/downstream components' register state
 	 * after clock configuration

@@ -618,13 +624,13 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 	if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
 		link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
 
-	if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
+	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
 		link->aspm_enabled |= ASPM_STATE_L1_1;
-	if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
+	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
 		link->aspm_enabled |= ASPM_STATE_L1_2;
-	if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
+	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
 		link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
-	if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
+	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
 		link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
 
 	if (link->aspm_support & ASPM_STATE_L1SS)

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Saheed O. Bolarinwa

author

2020-08-22 21:03 UTC #6 lore raw

RFC PATCH v5 6/23 PCI: Replace aspm_register_info.l1ss_cap* with their pci_dev version

In reply to Saheed O. Bolarinwa

Replace all references to aspm_register_info.(l1ss_cap | l1ss_cap_ptr) with pci_dev.(l1ss_cap | l1ss_cap_ptr)

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 34 ++++++++++++++++++----------------
 1 file changed, 18 insertions(+), 16 deletions(-)

drivers/pci/pcie/aspm.c +18 ~~-16~~

index d622affdbbcc..0657cad5f290 100644
@@ -501,32 +501,34 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
 {
 	u32 val1, val2, scale1, scale2;
 	u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
+	struct pci_dev *dw_pdev = link->downstream;
+	struct pci_dev *up_pdev = link->pdev;
 
-	link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr;
-	link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr;
+	link->l1ss.up_cap_ptr = up_pdev->l1ss_cap_ptr;
+	link->l1ss.dw_cap_ptr = dw_pdev->l1ss_cap_ptr;
 	link->l1ss.ctl1 = link->l1ss.ctl2 = 0;
 
 	if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
 		return;
 
 	/* Choose the greater of the two Port Common_Mode_Restore_Times */
-	val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
-	val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
+	val1 = (up_pdev->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
+	val2 = (dw_pdev->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
 	t_common_mode = max(val1, val2);
 
 	/* Choose the greater of the two Port T_POWER_ON times */
-	val1   = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
-	scale1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
-	val2   = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
-	scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
+	val1   = (up_pdev->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
+	scale1 = (up_pdev->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
+	val2   = (dw_pdev->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
+	scale2 = (dw_pdev->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
 
-	if (calc_l1ss_pwron(link->pdev, scale1, val1) >
-	    calc_l1ss_pwron(link->downstream, scale2, val2)) {
+	if (calc_l1ss_pwron(up_pdev, scale1, val1) >
+	    calc_l1ss_pwron(dw_pdev, scale2, val2)) {
 		link->l1ss.ctl2 |= scale1 | (val1 << 3);
-		t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1);
+		t_power_on = calc_l1ss_pwron(up_pdev, scale1, val1);
 	} else {
 		link->l1ss.ctl2 |= scale2 | (val2 << 3);
-		t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2);
+		t_power_on = calc_l1ss_pwron(dw_pdev, scale2, val2);
 	}
 
 	/*

@@ -615,13 +617,13 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 	link->latency_dw.l1 = calc_l1_latency(child);
 
 	/* Setup L1 substate */
-	if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
+	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
 		link->aspm_support |= ASPM_STATE_L1_1;
-	if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
+	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
 		link->aspm_support |= ASPM_STATE_L1_2;
-	if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
+	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
 		link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
-	if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
+	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
 		link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
 
 	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)

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Saheed O. Bolarinwa

author

2020-08-22 21:03 UTC #7 lore raw

RFC PATCH v5 7/23 PCI: Compute aspm_register_info.enable directly

In reply to Saheed O. Bolarinwa

- Create helper function to comute aspm_register_info.enable directly
- Replace all references with call to the helper function

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

drivers/pci/pcie/aspm.c +11 -3

index 0657cad5f290..c5f18d280892 100644
@@ -546,6 +546,14 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
 	link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
 }
 
+static u32 get_aspm_enable(struct pci_dev *pdev)
+{
+	u16 reg16;
+
+	pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &reg16);
+	return (reg16 & PCI_EXP_LNKCTL_ASPMC);
+}
+
 static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 {
 	struct pci_dev *child = link->downstream, *parent = link->pdev;

@@ -599,9 +607,9 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 			PCIE_LINK_STATE_L0S)
 		link->aspm_support |= ASPM_STATE_L0S;
 
-	if (dwreg.enabled & PCIE_LINK_STATE_L0S)
+	if (get_aspm_enable(child) & PCIE_LINK_STATE_L0S)
 		link->aspm_enabled |= ASPM_STATE_L0S_UP;
-	if (upreg.enabled & PCIE_LINK_STATE_L0S)
+	if (get_aspm_enable(parent) & PCIE_LINK_STATE_L0S)
 		link->aspm_enabled |= ASPM_STATE_L0S_DW;
 	link->latency_up.l0s = calc_l0s_latency(parent);
 	link->latency_dw.l0s = calc_l0s_latency(child);

@@ -611,7 +619,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 			((child->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10) &
 			PCIE_LINK_STATE_L1)
 		link->aspm_support |= ASPM_STATE_L1;
-	if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
+	if (get_aspm_enable(parent) & get_aspm_enable(child) & PCIE_LINK_STATE_L1)
 		link->aspm_enabled |= ASPM_STATE_L1;
 	link->latency_up.l1 = calc_l1_latency(parent);
 	link->latency_dw.l1 = calc_l1_latency(child);

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Saheed O. Bolarinwa

author

2020-08-22 21:03 UTC #8 lore raw

RFC PATCH v5 8/23 PCI: Remove unused aspm_calc_l1ss_info() arguments

In reply to Saheed O. Bolarinwa

The two struct aspm_register_info arguments of aspm_calc_l1ss_info() are now redundant.

- Remove redundant arguments.
- Refactor callers to also remove redundant parameters

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

drivers/pci/pcie/aspm.c +2 -4

index c5f18d280892..506552f8dd2b 100644
@@ -495,9 +495,7 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
 }
 
 /* Calculate L1.2 PM substate timing parameters */
-static void aspm_calc_l1ss_info(struct pcie_link_state *link,
-				struct aspm_register_info *upreg,
-				struct aspm_register_info *dwreg)
+static void aspm_calc_l1ss_info(struct pcie_link_state *link)
 {
 	u32 val1, val2, scale1, scale2;
 	u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;

@@ -644,7 +642,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 		link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
 
 	if (link->aspm_support & ASPM_STATE_L1SS)
-		aspm_calc_l1ss_info(link, &upreg, &dwreg);
+		aspm_calc_l1ss_info(link);
 
 	/* Save default state */
 	link->aspm_default = link->aspm_enabled;

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Saheed O. Bolarinwa

author

2020-08-22 21:03 UTC #9 lore raw

RFC PATCH v5 9/23 PCI: Remove pcie_get_aspm_reg() and struct aspm_register_info

In reply to Saheed O. Bolarinwa

All members of struct aspm_register_info are now calculated directly.

- Remove all calls to pcie_get_aspm_reg()
- Remove pcie_get_aspm_reg()
- Remove remaining redundant reference to struct aspm_register_info.
- Remove struct aspm_register_info

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 63 -----------------------------------------
 1 file changed, 63 deletions(-)

drivers/pci/pcie/aspm.c +0 ~~-63~~

index 506552f8dd2b..bf728c82158f 100644
@@ -382,57 +382,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
 	}
 }
 
-struct aspm_register_info {
-	u32 support:2;
-	u32 enabled:2;
-	u32 latency_encoding_l0s;
-	u32 latency_encoding_l1;
-
-	/* L1 substates */
-	u32 l1ss_cap_ptr;
-	u32 l1ss_cap;
-	u32 l1ss_ctl1;
-	u32 l1ss_ctl2;
-};
-
-static void pcie_get_aspm_reg(struct pci_dev *pdev,
-			      struct aspm_register_info *info)
-{
-	u16 reg16;
-	u32 reg32 = pdev->lnkcap;
-
-	info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
-	info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
-	info->latency_encoding_l1  = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
-	pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &reg16);
-	info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
-
-	/* Read L1 PM substate capabilities */
-	info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0;
-	info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
-	if (!info->l1ss_cap_ptr)
-		return;
-	pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CAP,
-			      &info->l1ss_cap);
-	if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) {
-		info->l1ss_cap = 0;
-		return;
-	}
-
-	/*
-	 * If we don't have LTR for the entire path from the Root Complex
-	 * to this device, we can't use ASPM L1.2 because it relies on the
-	 * LTR_L1.2_THRESHOLD.  See PCIe r4.0, secs 5.5.4, 6.18.
-	 */
-	if (!pdev->ltr_path)
-		info->l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;
-
-	pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1,
-			      &info->l1ss_ctl1);
-	pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2,
-			      &info->l1ss_ctl2);
-}
-
 static void pcie_aspm_check_latency(struct pci_dev *endpoint)
 {
 	u32 latency, l1_switch_latency = 0;

@@ -556,7 +505,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 {
 	struct pci_dev *child = link->downstream, *parent = link->pdev;
 	struct pci_bus *linkbus = parent->subordinate;
-	struct aspm_register_info upreg, dwreg;
 	u32 up_l1ss_ctl1, dw_l1ss_ctl1;
 
 	if (blacklist) {

@@ -566,10 +514,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 		return;
 	}
 
-	/* Get upstream/downstream components' register state */
-	pcie_get_aspm_reg(parent, &upreg);
-	pcie_get_aspm_reg(child, &dwreg);
-
 	/*
 	 * If ASPM not supported, don't mess with the clocks and link,
 	 * bail out now.

@@ -586,13 +530,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 	pci_read_config_dword(child, child->l1ss_cap_ptr + PCI_L1SS_CTL1,
 				&dw_l1ss_ctl1);
 
-	/*
-	 * Re-read upstream/downstream components' register state
-	 * after clock configuration
-	 */
-	pcie_get_aspm_reg(parent, &upreg);
-	pcie_get_aspm_reg(child, &dwreg);
-
 	/*
 	 * Setup L0s state
 	 *

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Saheed O. Bolarinwa

author

2020-08-22 21:03 UTC #10 lore raw

RFC PATCH v5 10/23 PCI: Relocate call to aspm_calc_l1ss_info

In reply to Saheed O. Bolarinwa

This function calculates pcie_link_state.l1ss.{ctl1, ctl2} which are only used inside pcie_config_aspm_l1ss().

Move call to aspm_calc_l1ss_info from pcie_aspm_cap_init() to pcie_config_aspm_l1ss().

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

drivers/pci/pcie/aspm.c +2 -4

index bf728c82158f..89f3f3a6d007 100644
@@ -578,9 +578,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
 		link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
 
-	if (link->aspm_support & ASPM_STATE_L1SS)
-		aspm_calc_l1ss_info(link);
-
 	/* Save default state */
 	link->aspm_default = link->aspm_enabled;

@@ -628,7 +625,8 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
 	u32 up_cap_ptr = link->l1ss.up_cap_ptr;
 	u32 dw_cap_ptr = link->l1ss.dw_cap_ptr;
 
-	enable_req = (link->aspm_enabled ^ state) & state;
+	enable_req = (parent->aspm_enabled ^ state) & state;
+	aspm_calc_l1ss_info(link);
 
 	/*
 	 * Here are the rules specified in the PCIe spec for enabling L1SS:

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Saheed O. Bolarinwa

author

2020-08-22 21:03 UTC #11 lore raw

RFC PATCH v5 11/23 PCI: Rework and Rename aspm_calc_l1ss_info()

In reply to Saheed O. Bolarinwa

The value of l1ss_cap_ptr can nw be obtained directly from struct pci_dev, it is no useful to cache it. So, aspm_calc_l1ss_info() will only be computing the values of ctl1 and ctl2.

- Rename aspm_calc_l1ss_info() to aspm_calc_l1ss_ctl_values().
- Rework the function to take a pci_dev and values' pointer.
- Remove caching of pdev->l1ss_cap_ptr
- Change calls to aspm_calc_l1ss_info() into new function.
- Access pdev->l1ss_cap_ptr directly
- No more reference to struct pcie_link_state.l1ss, so remove it.

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 43 ++++++++++++++---------------------------
 1 file changed, 15 insertions(+), 28 deletions(-)

drivers/pci/pcie/aspm.c +15 ~~-28~~

index 89f3f3a6d007..4cff11dc8d83 100644
@@ -74,14 +74,6 @@ struct pcie_link_state {
 	 * has one slot under it, so at most there are 8 functions.
 	 */
 	struct aspm_latency acceptable[8];
-
-	/* L1 PM Substate info */
-	struct {
-		u32 up_cap_ptr;		/* L1SS cap ptr in upstream dev */
-		u32 dw_cap_ptr;		/* L1SS cap ptr in downstream dev */
-		u32 ctl1;		/* value to be programmed in ctl1 */
-		u32 ctl2;		/* value to be programmed in ctl2 */
-	} l1ss;
 };
 
 static int aspm_disabled, aspm_force;

@@ -444,17 +436,15 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
 }
 
 /* Calculate L1.2 PM substate timing parameters */
-static void aspm_calc_l1ss_info(struct pcie_link_state *link)
+static void aspm_calc_l1ss_ctl_values(struct pci_dev *pdev,
+						u32 *ctl1, u32 *ctl2)
 {
+	struct pcie_link_state *link = pdev->link_state;
 	u32 val1, val2, scale1, scale2;
 	u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
 	struct pci_dev *dw_pdev = link->downstream;
 	struct pci_dev *up_pdev = link->pdev;
 
-	link->l1ss.up_cap_ptr = up_pdev->l1ss_cap_ptr;
-	link->l1ss.dw_cap_ptr = dw_pdev->l1ss_cap_ptr;
-	link->l1ss.ctl1 = link->l1ss.ctl2 = 0;
-
 	if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
 		return;

@@ -471,10 +461,10 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link)
 
 	if (calc_l1ss_pwron(up_pdev, scale1, val1) >
 	    calc_l1ss_pwron(dw_pdev, scale2, val2)) {
-		link->l1ss.ctl2 |= scale1 | (val1 << 3);
+		*ctl2 |= scale1 | (val1 << 3);
 		t_power_on = calc_l1ss_pwron(up_pdev, scale1, val1);
 	} else {
-		link->l1ss.ctl2 |= scale2 | (val2 << 3);
+		*ctl2 |= scale2 | (val2 << 3);
 		t_power_on = calc_l1ss_pwron(dw_pdev, scale2, val2);
 	}

@@ -490,7 +480,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link)
 	 */
 	l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
 	encode_l12_threshold(l1_2_threshold, &scale, &value);
-	link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
+	*ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
 }
 
 static u32 get_aspm_enable(struct pci_dev *pdev)

@@ -620,13 +610,13 @@ static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
 /* Configure the ASPM L1 substates */
 static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
 {
-	u32 val, enable_req;
+	u32 val, enable_req, ctl1, ctl2;
 	struct pci_dev *child = link->downstream, *parent = link->pdev;
-	u32 up_cap_ptr = link->l1ss.up_cap_ptr;
-	u32 dw_cap_ptr = link->l1ss.dw_cap_ptr;
+	int up_cap_ptr = parent->l1ss_cap_ptr;
+	int dw_cap_ptr = child->l1ss_cap_ptr;
 
 	enable_req = (parent->aspm_enabled ^ state) & state;
-	aspm_calc_l1ss_info(link);
+	aspm_calc_l1ss_ctl_values(parent, &ctl1, &ctl2);
 
 	/*
 	 * Here are the rules specified in the PCIe spec for enabling L1SS:

@@ -661,24 +651,21 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
 
 		/* Program T_POWER_ON times in both ports */
 		pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2,
-				       link->l1ss.ctl2);
+				       ctl2);
 		pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2,
-				       link->l1ss.ctl2);
+				       ctl2);
 
 		/* Program Common_Mode_Restore_Time in upstream device */
 		pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
-					PCI_L1SS_CTL1_CM_RESTORE_TIME,
-					link->l1ss.ctl1);
+					PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
 
 		/* Program LTR_L1.2_THRESHOLD time in both ports */
 		pci_clear_and_set_dword(parent,	up_cap_ptr + PCI_L1SS_CTL1,
 					PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
-					PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
-					link->l1ss.ctl1);
+					PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
 		pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
 					PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
-					PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
-					link->l1ss.ctl1);
+					PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
 	}
 
 	val = 0;

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Saheed O. Bolarinwa

author

2020-08-22 21:03 UTC #12 lore raw

RFC PATCH v5 12/23 PCI: Add ASPM and CLOCK PM states to struct pci_dev

In reply to Saheed O. Bolarinwa

Move all struct pcie_link_state information to struct pci_dev

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c |  5 -----
 include/linux/pci.h     | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+), 5 deletions(-)

drivers/pci/pcie/aspm.c +0 -5

index 4cff11dc8d83..d9c17093b250 100644
@@ -41,11 +41,6 @@
 #define ASPM_STATE_ALL		(ASPM_STATE_L0S | ASPM_STATE_L1 |	\
 				 ASPM_STATE_L1SS)
 
-struct aspm_latency {
-	u32 l0s;			/* L0s latency (nsec) */
-	u32 l1;				/* L1 latency (nsec) */
-};
-
 struct pcie_link_state {
 	struct pci_dev *pdev;		/* Upstream component of the Link */
 	struct pci_dev *downstream;	/* Downstream component, function 0 */

include/linux/pci.h +32 -0

index fa114c5d01e7..1daf5fe0b913 100644
@@ -305,6 +305,11 @@ struct pci_vpd;
 struct pci_sriov;
 struct pci_p2pdma;
 
+struct aspm_latency {
+	u32 l0s;			/* L0s latency (nsec) */
+	u32 l1;				/* L1 latency (nsec) */
+};
+
 /* The pci_dev structure describes PCI devices */
 struct pci_dev {
 	struct list_head bus_list;	/* Node in per-bus list */

@@ -383,6 +388,33 @@ struct pci_dev {
 					   supported from root to here */
 	int		l1ss_cap_ptr;	/* L1SS cap ptr, 0 if not supported */
 	u32		l1ss_cap;	/* L1 PM substate Capabilities */
+
+	struct pci_dev	*parent;	/* pointer to the parent */
+	struct pci_dev	*root;		/* pointer to the root port */
+	struct pci_dev	*downstream;	/* Downstream component, function 0 */
+	struct list_head sibling;	/* node in link_list */
+
+	/* ASPM state */
+	u32 aspm_support:7;             /* Supported ASPM state */
+	u32 aspm_enabled:7;             /* Enabled ASPM state */
+	u32 aspm_capable:7;             /* Capable ASPM state with latency */
+	u32 aspm_default:7;             /* Default ASPM state by BIOS */
+	u32 aspm_disable:7;             /* Disabled ASPM state */
+
+	/* Clock PM state */
+	u32 clkpm_capable:1;            /* Clock PM capable? */
+	u32 clkpm_enabled:1;            /* Current Clock PM state */
+	u32 clkpm_default:1;            /* Default Clock PM state by BIOS */
+	u32 clkpm_disable:1;            /* Clock PM disabled */
+
+	/* Exit latencies */
+	struct aspm_latency latency_up;	/* Upstream direction exit latency */
+	struct aspm_latency latency_dw;	/* Downstream direction exit latency */
+	/*
+	 * Endpoint acceptable latencies. A pcie downstream port only
+	 * has one slot under it, so at most there are 8 functions.
+	 */
+	struct aspm_latency acceptable[8];
 #endif
 	unsigned int	eetlp_prefix_path:1;	/* End-to-End TLP Prefix */

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Saheed O. Bolarinwa

author

2020-08-22 21:03 UTC #13 lore raw

RFC PATCH v5 13/23 PCI: Initialise and Update values of pci_dev's PCIe link info

In reply to Saheed O. Bolarinwa

The PCIe link state information defined in struct pci_dev are initialised alongside with those of struct pcie_link_state.

The redundancy introduced is cleared out in later patches.

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 133 ++++++++++++++++++++++++++++++++--------
 1 file changed, 109 insertions(+), 24 deletions(-)

drivers/pci/pcie/aspm.c +109 ~~-24~~

index d9c17093b250..e869e7faaac5 100644
@@ -75,6 +75,7 @@ static int aspm_disabled, aspm_force;
 static bool aspm_support_enabled = true;
 static DEFINE_MUTEX(aspm_lock);
 static LIST_HEAD(link_list);
+static LIST_HEAD(pdev_link_list);
 
 #define POLICY_DEFAULT 0	/* BIOS default setting */
 #define POLICY_PERFORMANCE 1	/* high performance */

@@ -145,6 +146,7 @@ static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
 						   PCI_EXP_LNKCTL_CLKREQ_EN,
 						   val);
 	link->clkpm_enabled = !!enable;
+	link->pdev->clkpm_enabled = !!enable;
 }
 
 static void pcie_set_clkpm(struct pcie_link_state *link, int enable)

@@ -183,6 +185,10 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
 	link->clkpm_default = enabled;
 	link->clkpm_capable = capable;
 	link->clkpm_disable = blacklist ? 1 : 0;
+	link->pdev->clkpm_enabled = enabled;
+	link->pdev->clkpm_default = enabled;
+	link->pdev->clkpm_capable = capable;
+	link->pdev->clkpm_disable = blacklist ? 1 : 0;
 }
 
 static bool pcie_retrain_link(struct pcie_link_state *link)

@@ -374,6 +380,7 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
 	u32 latency, l1_switch_latency = 0;
 	struct aspm_latency *acceptable;
 	struct pcie_link_state *link;
+	struct pci_dev *pdev;
 
 	/* Device not in D0 doesn't need latency check */
 	if ((endpoint->current_state != PCI_D0) &&

@@ -381,18 +388,24 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
 		return;
 
 	link = endpoint->bus->self->link_state;
+	pdev = endpoint->bus->self;
 	acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
 
 	while (link) {
 		/* Check upstream direction L0s latency */
 		if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
-		    (link->latency_up.l0s > acceptable->l0s))
+		    (link->latency_up.l0s > acceptable->l0s)) {
 			link->aspm_capable &= ~ASPM_STATE_L0S_UP;
+			pdev->aspm_capable &= ~ASPM_STATE_L0S_UP;
+		}
 
 		/* Check downstream direction L0s latency */
 		if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
-		    (link->latency_dw.l0s > acceptable->l0s))
+		    (link->latency_dw.l0s > acceptable->l0s)) {
 			link->aspm_capable &= ~ASPM_STATE_L0S_DW;
+			pdev->aspm_capable &= ~ASPM_STATE_L0S_DW;
+		}
+
 		/*
 		 * Check L1 latency.
 		 * Every switch on the path to root complex need 1

@@ -408,11 +421,15 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
 		 */
 		latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
 		if ((link->aspm_capable & ASPM_STATE_L1) &&
-		    (latency + l1_switch_latency > acceptable->l1))
+		    (latency + l1_switch_latency > acceptable->l1)) {
 			link->aspm_capable &= ~ASPM_STATE_L1;
+			pdev->aspm_capable &= ~ASPM_STATE_L1;
+		}
+
 		l1_switch_latency += 1000;
 
 		link = link->parent;
+		pdev = pdev->parent;
 	}
 }

@@ -496,6 +513,8 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 		/* Set enabled/disable so that we will disable ASPM later */
 		link->aspm_enabled = ASPM_STATE_ALL;
 		link->aspm_disable = ASPM_STATE_ALL;
+		parent->aspm_enabled = ASPM_STATE_ALL;
+		parent->aspm_disable = ASPM_STATE_ALL;
 		return;
 	}

@@ -524,50 +543,87 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 	 */
 	if (((parent->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10) &
 			((child->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10) &
-			PCIE_LINK_STATE_L0S)
+			PCIE_LINK_STATE_L0S) {
 		link->aspm_support |= ASPM_STATE_L0S;
+		parent->aspm_support |= ASPM_STATE_L0S;
+	}
 
-	if (get_aspm_enable(child) & PCIE_LINK_STATE_L0S)
+	if (get_aspm_enable(child) & PCIE_LINK_STATE_L0S) {
 		link->aspm_enabled |= ASPM_STATE_L0S_UP;
-	if (get_aspm_enable(parent) & PCIE_LINK_STATE_L0S)
+		parent->aspm_enabled |= ASPM_STATE_L0S_UP;
+	}
+
+	if (get_aspm_enable(parent) & PCIE_LINK_STATE_L0S) {
 		link->aspm_enabled |= ASPM_STATE_L0S_DW;
+		parent->aspm_enabled |= ASPM_STATE_L0S_DW;
+	}
+
 	link->latency_up.l0s = calc_l0s_latency(parent);
 	link->latency_dw.l0s = calc_l0s_latency(child);
+	parent->latency_up.l0s = calc_l0s_latency(parent);
+	parent->latency_dw.l0s = calc_l0s_latency(child);
 
 	/* Setup L1 state */
 	if (((parent->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10) &
 			((child->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10) &
-			PCIE_LINK_STATE_L1)
+			PCIE_LINK_STATE_L1) {
 		link->aspm_support |= ASPM_STATE_L1;
-	if (get_aspm_enable(parent) & get_aspm_enable(child) & PCIE_LINK_STATE_L1)
+		parent->aspm_support |= ASPM_STATE_L1;
+	}
+
+	if (get_aspm_enable(parent) & get_aspm_enable(child) &
+			    PCIE_LINK_STATE_L1) {
 		link->aspm_enabled |= ASPM_STATE_L1;
+		parent->aspm_enabled |= ASPM_STATE_L1;
+	}
+
 	link->latency_up.l1 = calc_l1_latency(parent);
 	link->latency_dw.l1 = calc_l1_latency(child);
+	parent->latency_up.l1 = calc_l1_latency(parent);
+	parent->latency_dw.l1 = calc_l1_latency(child);
 
 	/* Setup L1 substate */
-	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
+	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1) {
 		link->aspm_support |= ASPM_STATE_L1_1;
-	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
+		parent->aspm_support |= ASPM_STATE_L1_1;
+	}
+	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2) {
 		link->aspm_support |= ASPM_STATE_L1_2;
-	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
+		parent->aspm_support |= ASPM_STATE_L1_2;
+	}
+	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1) {
 		link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
-	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
+		parent->aspm_support |= ASPM_STATE_L1_1_PCIPM;
+	}
+	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2) {
 		link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
+		parent->aspm_support |= ASPM_STATE_L1_2_PCIPM;
+	}
 
-	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
+	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1) {
 		link->aspm_enabled |= ASPM_STATE_L1_1;
-	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
+		parent->aspm_enabled |= ASPM_STATE_L1_1;
+	}
+	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2) {
 		link->aspm_enabled |= ASPM_STATE_L1_2;
-	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
+		parent->aspm_enabled |= ASPM_STATE_L1_2;
+	}
+	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1) {
 		link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
-	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
+		parent->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
+	}
+	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2) {
 		link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
+		parent->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
+	}
 
 	/* Save default state */
 	link->aspm_default = link->aspm_enabled;
+	parent->aspm_default = parent->aspm_enabled;
 
 	/* Setup initial capable state. Will be updated later */
 	link->aspm_capable = link->aspm_support;
+	parent->aspm_capable = parent->aspm_support;
 
 	/* Get and check endpoint acceptable latencies */
 	list_for_each_entry(child, &linkbus->devices, bus_list) {

@@ -735,6 +791,7 @@ static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
 		pcie_config_aspm_dev(parent, upstream);
 
 	link->aspm_enabled = state;
+	parent->aspm_enabled = state;
 }
 
 static void pcie_config_aspm_path(struct pcie_link_state *link)

@@ -795,8 +852,10 @@ static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
 		return NULL;
 
 	INIT_LIST_HEAD(&link->sibling);
+	INIT_LIST_HEAD(&pdev->sibling);
 	link->pdev = pdev;
 	link->downstream = pci_function_0(pdev->subordinate);
+	pdev->downstream = pci_function_0(pdev->subordinate);
 
 	/*
 	 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe

@@ -809,6 +868,7 @@ static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
 	    pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
 	    !pdev->bus->parent->self) {
 		link->root = link;
+		pdev->root = pdev;
 	} else {
 		struct pcie_link_state *parent;

@@ -820,9 +880,12 @@ static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
 
 		link->parent = parent;
 		link->root = link->parent->root;
+		pdev->parent = pdev->bus->parent->self;
+		pdev->root = pdev->parent->root;
 	}
 
 	list_add(&link->sibling, &link_list);
+	list_add(&pdev->sibling, &pdev_link_list);
 	pdev->link_state = link;
 	return link;
 }

@@ -913,6 +976,7 @@ static void pcie_update_aspm_capable(struct pcie_link_state *root)
 		if (link->root != root)
 			continue;
 		link->aspm_capable = link->aspm_support;
+		link->pdev->aspm_capable = link->aspm_support;
 	}
 	list_for_each_entry(link, &link_list, sibling) {
 		struct pci_dev *child;

@@ -1021,6 +1085,7 @@ static struct pcie_link_state *pcie_aspm_get_link(struct pci_dev *pdev)
 static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
 {
 	struct pcie_link_state *link = pcie_aspm_get_link(pdev);
+	struct pci_dev *bridge = link->pdev;
 
 	if (!link)
 		return -EINVAL;

@@ -1040,23 +1105,37 @@ static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
 	if (sem)
 		down_read(&pci_bus_sem);
 	mutex_lock(&aspm_lock);
-	if (state & PCIE_LINK_STATE_L0S)
+	if (state & PCIE_LINK_STATE_L0S) {
 		link->aspm_disable |= ASPM_STATE_L0S;
-	if (state & PCIE_LINK_STATE_L1)
+		bridge->aspm_disable |= ASPM_STATE_L0S;
+	}
+	if (state & PCIE_LINK_STATE_L1) {
 		/* L1 PM substates require L1 */
 		link->aspm_disable |= ASPM_STATE_L1 | ASPM_STATE_L1SS;
-	if (state & PCIE_LINK_STATE_L1_1)
+		bridge->aspm_disable |= ASPM_STATE_L1 | ASPM_STATE_L1SS;
+	}
+	if (state & PCIE_LINK_STATE_L1_1) {
 		link->aspm_disable |= ASPM_STATE_L1_1;
-	if (state & PCIE_LINK_STATE_L1_2)
+		bridge->aspm_disable |= ASPM_STATE_L1_1;
+	}
+	if (state & PCIE_LINK_STATE_L1_2) {
 		link->aspm_disable |= ASPM_STATE_L1_2;
-	if (state & PCIE_LINK_STATE_L1_1_PCIPM)
+		bridge->aspm_disable |= ASPM_STATE_L1_2;
+	}
+	if (state & PCIE_LINK_STATE_L1_1_PCIPM) {
 		link->aspm_disable |= ASPM_STATE_L1_1_PCIPM;
-	if (state & PCIE_LINK_STATE_L1_2_PCIPM)
+		bridge->aspm_disable |= ASPM_STATE_L1_1_PCIPM;
+	}
+	if (state & PCIE_LINK_STATE_L1_2_PCIPM) {
 		link->aspm_disable |= ASPM_STATE_L1_2_PCIPM;
+		bridge->aspm_disable |= ASPM_STATE_L1_2_PCIPM;
+	}
 	pcie_config_aspm_link(link, policy_to_aspm_state(link));
 
-	if (state & PCIE_LINK_STATE_CLKPM)
+	if (state & PCIE_LINK_STATE_CLKPM) {
 		link->clkpm_disable = 1;
+		bridge->clkpm_disable = 1;
+	}
 	pcie_set_clkpm(link, policy_to_clkpm_state(link));
 	mutex_unlock(&aspm_lock);
 	if (sem)

@@ -1162,6 +1241,7 @@ static ssize_t aspm_attr_store_common(struct device *dev,
 {
 	struct pci_dev *pdev = to_pci_dev(dev);
 	struct pcie_link_state *link = pcie_aspm_get_link(pdev);
+	struct pci_dev *bridge = link->pdev;
 	bool state_enable;
 
 	if (strtobool(buf, &state_enable) < 0)

@@ -1172,11 +1252,15 @@ static ssize_t aspm_attr_store_common(struct device *dev,
 
 	if (state_enable) {
 		link->aspm_disable &= ~state;
+		bridge->aspm_disable &= ~state;
 		/* need to enable L1 for substates */
-		if (state & ASPM_STATE_L1SS)
+		if (state & ASPM_STATE_L1SS) {
 			link->aspm_disable &= ~ASPM_STATE_L1;
+			bridge->aspm_disable &= ~ASPM_STATE_L1;
+		}
 	} else {
 		link->aspm_disable |= state;
+		bridge->aspm_disable |= state;
 	}
 
 	pcie_config_aspm_link(link, policy_to_aspm_state(link));

@@ -1228,6 +1312,7 @@ static ssize_t clkpm_store(struct device *dev,
 	mutex_lock(&aspm_lock);
 
 	link->clkpm_disable = !state_enable;
+	link->pdev->clkpm_disable = !state_enable;
 	pcie_set_clkpm(link, policy_to_clkpm_state(link));
 
 	mutex_unlock(&aspm_lock);

Signature · 6 lines

2.18.4

_______________________________________________
Linux-kernel-mentees mailing list
[email protected]
https://lists.linuxfoundation.org/mailman/listinfo/linux-kernel-mentees

Saheed O. Bolarinwa

author

2020-08-22 21:04 UTC #14 lore raw

RFC PATCH v5 14/23 PCI: Change Return and Argument values from pcie_link_state to pci_dev

In reply to Saheed O. Bolarinwa

- Change Return and Argument values from pcie_link_state to pci_dev
- Refactor callers accordingly

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 145 +++++++++++++++++++++-------------------
 1 file changed, 76 insertions(+), 69 deletions(-)

drivers/pci/pcie/aspm.c +76 ~~-69~~

index e869e7faaac5..6f73eb2ca0bd 100644
@@ -101,7 +101,7 @@ static const char *policy_str[] = {
 
 #define LINK_RETRAIN_TIMEOUT HZ
 
-static int policy_to_aspm_state(struct pcie_link_state *link)
+static int policy_to_aspm_state(struct pci_dev *pdev)
 {
 	switch (aspm_policy) {
 	case POLICY_PERFORMANCE:

@@ -114,12 +114,12 @@ static int policy_to_aspm_state(struct pcie_link_state *link)
 		/* Enable Everything */
 		return ASPM_STATE_ALL;
 	case POLICY_DEFAULT:
-		return link->aspm_default;
+		return pdev->link_state->aspm_default;
 	}
 	return 0;
 }
 
-static int policy_to_clkpm_state(struct pcie_link_state *link)
+static int policy_to_clkpm_state(struct pci_dev *pdev)
 {
 	switch (aspm_policy) {
 	case POLICY_PERFORMANCE:

@@ -130,13 +130,14 @@ static int policy_to_clkpm_state(struct pcie_link_state *link)
 		/* Enable Clock PM */
 		return 1;
 	case POLICY_DEFAULT:
-		return link->clkpm_default;
+		return pdev->link_state->clkpm_default;
 	}
 	return 0;
 }
 
-static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
+static void pcie_set_clkpm_nocheck(struct pci_dev *pdev, int enable)
 {
+	struct pcie_link_state *link = pdev->link_state;
 	struct pci_dev *child;
 	struct pci_bus *linkbus = link->pdev->subordinate;
 	u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;

@@ -149,8 +150,9 @@ static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
 	link->pdev->clkpm_enabled = !!enable;
 }
 
-static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
+static void pcie_set_clkpm(struct pci_dev *pdev, int enable)
 {
+	struct pcie_link_state *link = pdev->link_state;
 	/*
 	 * Don't enable Clock PM if the link is not Clock PM capable
 	 * or Clock PM is disabled

@@ -160,11 +162,12 @@ static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
 	/* Need nothing if the specified equals to current state */
 	if (link->clkpm_enabled == enable)
 		return;
-	pcie_set_clkpm_nocheck(link, enable);
+	pcie_set_clkpm_nocheck(link->pdev, enable);
 }
 
-static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
+static void pcie_clkpm_cap_init(struct pci_dev *pdev, int blacklist)
 {
+	struct pcie_link_state *link = pdev->link_state;
 	int capable = 1, enabled = 1;
 	u16 reg16;
 	struct pci_dev *child;

@@ -191,9 +194,8 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
 	link->pdev->clkpm_disable = blacklist ? 1 : 0;
 }
 
-static bool pcie_retrain_link(struct pcie_link_state *link)
+static bool pcie_retrain_link(struct pci_dev *parent)
 {
-	struct pci_dev *parent = link->pdev;
 	unsigned long end_jiffies;
 	u16 reg16;

@@ -226,11 +228,11 @@ static bool pcie_retrain_link(struct pcie_link_state *link)
  *   could use common clock. If they are, configure them to use the
  *   common clock. That will reduce the ASPM state exit latency.
  */
-static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
+static void pcie_aspm_configure_common_clock(struct pci_dev *parent)
 {
 	int same_clock = 1;
 	u16 reg16, parent_reg, child_reg[8];
-	struct pci_dev *child, *parent = link->pdev;
+	struct pci_dev *child;
 	struct pci_bus *linkbus = parent->subordinate;
 	/*
 	 * All functions of a slot should have the same Slot Clock

@@ -287,7 +289,7 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
 		reg16 &= ~PCI_EXP_LNKCTL_CCC;
 	pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
 
-	if (pcie_retrain_link(link))
+	if (pcie_retrain_link(parent))
 		return;
 
 	/* Training failed. Restore common clock configurations */

@@ -503,8 +505,9 @@ static u32 get_aspm_enable(struct pci_dev *pdev)
 	return (reg16 & PCI_EXP_LNKCTL_ASPMC);
 }
 
-static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
+static void pcie_aspm_cap_init(struct pci_dev *pdev, int blacklist)
 {
+	struct pcie_link_state *link = pdev->link_state;
 	struct pci_dev *child = link->downstream, *parent = link->pdev;
 	struct pci_bus *linkbus = parent->subordinate;
 	u32 up_l1ss_ctl1, dw_l1ss_ctl1;

@@ -527,7 +530,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 		return;
 
 	/* Configure common clock before checking latencies */
-	pcie_aspm_configure_common_clock(link);
+	pcie_aspm_configure_common_clock(parent);
 
 	pci_read_config_dword(parent, parent->l1ss_cap_ptr + PCI_L1SS_CTL1,
 				&up_l1ss_ctl1);

@@ -659,8 +662,9 @@ static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
 }
 
 /* Configure the ASPM L1 substates */
-static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
+static void pcie_config_aspm_l1ss(struct pci_dev *pdev, u32 state)
 {
+	struct pcie_link_state *link = pdev->link_state;
 	u32 val, enable_req, ctl1, ctl2;
 	struct pci_dev *child = link->downstream, *parent = link->pdev;
 	int up_cap_ptr = parent->l1ss_cap_ptr;

@@ -742,8 +746,9 @@ static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
 					   PCI_EXP_LNKCTL_ASPMC, val);
 }
 
-static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
+static void pcie_config_aspm_link(struct pci_dev *pdev, u32 state)
 {
+	struct pcie_link_state *link = pdev->link_state;
 	u32 upstream = 0, dwstream = 0;
 	struct pci_dev *child = link->downstream, *parent = link->pdev;
 	struct pci_bus *linkbus = parent->subordinate;

@@ -775,7 +780,7 @@ static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
 	}
 
 	if (link->aspm_capable & ASPM_STATE_L1SS)
-		pcie_config_aspm_l1ss(link, state);
+		pcie_config_aspm_l1ss(parent, state);
 
 	/*
 	 * Spec 2.0 suggests all functions should be configured the

@@ -794,18 +799,18 @@ static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
 	parent->aspm_enabled = state;
 }
 
-static void pcie_config_aspm_path(struct pcie_link_state *link)
+static void pcie_config_aspm_path(struct pci_dev *pdev)
 {
-	while (link) {
-		pcie_config_aspm_link(link, policy_to_aspm_state(link));
-		link = link->parent;
+	while (pdev) {
+		pcie_config_aspm_link(pdev, policy_to_aspm_state(pdev));
+		pdev = pdev->parent;
 	}
 }
 
-static void free_link_state(struct pcie_link_state *link)
+static void free_link_state(struct pci_dev *pdev)
 {
-	link->pdev->link_state = NULL;
-	kfree(link);
+	pdev->link_state = NULL;
+	kfree(pdev->link_state);
 }
 
 static int pcie_aspm_sanity_check(struct pci_dev *pdev)

@@ -843,13 +848,13 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
 	return 0;
 }
 
-static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
+static int alloc_pcie_link_state(struct pci_dev *pdev)
 {
 	struct pcie_link_state *link;
 
 	link = kzalloc(sizeof(*link), GFP_KERNEL);
 	if (!link)
-		return NULL;
+		return -1;
 
 	INIT_LIST_HEAD(&link->sibling);
 	INIT_LIST_HEAD(&pdev->sibling);

@@ -875,7 +880,7 @@ static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
 		parent = pdev->bus->parent->self->link_state;
 		if (!parent) {
 			kfree(link);
-			return NULL;
+			return -1;
 		}
 
 		link->parent = parent;

@@ -887,7 +892,7 @@ static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
 	list_add(&link->sibling, &link_list);
 	list_add(&pdev->sibling, &pdev_link_list);
 	pdev->link_state = link;
-	return link;
+	return 0;
 }
 
 static void pcie_aspm_update_sysfs_visibility(struct pci_dev *pdev)

@@ -932,18 +937,20 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev)
 		goto out;
 
 	mutex_lock(&aspm_lock);
-	link = alloc_pcie_link_state(pdev);
-	if (!link)
+	if (!(alloc_pcie_link_state(pdev)))
 		goto unlock;
+
+	link = pdev->link_state;
+
 	/*
 	 * Setup initial ASPM state. Note that we need to configure
 	 * upstream links also because capable state of them can be
 	 * update through pcie_aspm_cap_init().
 	 */
-	pcie_aspm_cap_init(link, blacklist);
+	pcie_aspm_cap_init(link->pdev, blacklist);
 
 	/* Setup initial Clock PM state */
-	pcie_clkpm_cap_init(link, blacklist);
+	pcie_clkpm_cap_init(link->pdev, blacklist);
 
 	/*
 	 * At this stage drivers haven't had an opportunity to change the

@@ -955,8 +962,8 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev)
 	 */
 	if (aspm_policy != POLICY_POWERSAVE &&
 	    aspm_policy != POLICY_POWER_SUPERSAVE) {
-		pcie_config_aspm_path(link);
-		pcie_set_clkpm(link, policy_to_clkpm_state(link));
+		pcie_config_aspm_path(link->pdev);
+		pcie_set_clkpm(link->pdev, policy_to_clkpm_state(link->pdev));
 	}
 
 	pcie_aspm_update_sysfs_visibility(pdev);

@@ -968,8 +975,9 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev)
 }
 
 /* Recheck latencies and update aspm_capable for links under the root */
-static void pcie_update_aspm_capable(struct pcie_link_state *root)
+static void pcie_update_aspm_capable(struct pci_dev *root_pdev)
 {
+	struct pcie_link_state *root = root_pdev->link_state;
 	struct pcie_link_state *link;
 	BUG_ON(root->parent);
 	list_for_each_entry(link, &link_list, sibling) {

@@ -1015,15 +1023,15 @@ void pcie_aspm_exit_link_state(struct pci_dev *pdev)
 	parent_link = link->parent;
 
 	/* All functions are removed, so just disable ASPM for the link */
-	pcie_config_aspm_link(link, 0);
+	pcie_config_aspm_link(parent, 0);
 	list_del(&link->sibling);
 	/* Clock PM is for endpoint device */
-	free_link_state(link);
+	free_link_state(parent);
 
 	/* Recheck latencies and configure upstream links */
 	if (parent_link) {
-		pcie_update_aspm_capable(root);
-		pcie_config_aspm_path(parent_link);
+		pcie_update_aspm_capable(root->pdev);
+		pcie_config_aspm_path(parent_link->pdev);
 	}
 out:
 	mutex_unlock(&aspm_lock);

@@ -1043,8 +1051,8 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev)
 	 */
 	down_read(&pci_bus_sem);
 	mutex_lock(&aspm_lock);
-	pcie_update_aspm_capable(link->root);
-	pcie_config_aspm_path(link);
+	pcie_update_aspm_capable(link->root->pdev);
+	pcie_config_aspm_path(pdev);
 	mutex_unlock(&aspm_lock);
 	up_read(&pci_bus_sem);
 }

@@ -1062,13 +1070,13 @@ void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
 
 	down_read(&pci_bus_sem);
 	mutex_lock(&aspm_lock);
-	pcie_config_aspm_path(link);
-	pcie_set_clkpm(link, policy_to_clkpm_state(link));
+	pcie_config_aspm_path(pdev);
+	pcie_set_clkpm(pdev, policy_to_clkpm_state(pdev));
 	mutex_unlock(&aspm_lock);
 	up_read(&pci_bus_sem);
 }
 
-static struct pcie_link_state *pcie_aspm_get_link(struct pci_dev *pdev)
+static struct pci_dev *pcie_aspm_get_link(struct pci_dev *pdev)
 {
 	struct pci_dev *bridge;

@@ -1079,13 +1087,13 @@ static struct pcie_link_state *pcie_aspm_get_link(struct pci_dev *pdev)
 	if (!bridge || !pci_is_pcie(bridge))
 		return NULL;
 
-	return bridge->link_state;
+	return bridge;
 }
 
 static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
 {
-	struct pcie_link_state *link = pcie_aspm_get_link(pdev);
-	struct pci_dev *bridge = link->pdev;
+	struct pci_dev *bridge = pcie_aspm_get_link(pdev);
+	struct pcie_link_state *link = bridge->link_state;
 
 	if (!link)
 		return -EINVAL;

@@ -1130,13 +1138,13 @@ static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
 		link->aspm_disable |= ASPM_STATE_L1_2_PCIPM;
 		bridge->aspm_disable |= ASPM_STATE_L1_2_PCIPM;
 	}
-	pcie_config_aspm_link(link, policy_to_aspm_state(link));
+	pcie_config_aspm_link(link->pdev, policy_to_aspm_state(link->pdev));
 
 	if (state & PCIE_LINK_STATE_CLKPM) {
 		link->clkpm_disable = 1;
 		bridge->clkpm_disable = 1;
 	}
-	pcie_set_clkpm(link, policy_to_clkpm_state(link));
+	pcie_set_clkpm(link->pdev, policy_to_clkpm_state(link->pdev));
 	mutex_unlock(&aspm_lock);
 	if (sem)
 		up_read(&pci_bus_sem);

@@ -1183,8 +1191,8 @@ static int pcie_aspm_set_policy(const char *val,
 	mutex_lock(&aspm_lock);
 	aspm_policy = i;
 	list_for_each_entry(link, &link_list, sibling) {
-		pcie_config_aspm_link(link, policy_to_aspm_state(link));
-		pcie_set_clkpm(link, policy_to_clkpm_state(link));
+		pcie_config_aspm_link(link->pdev, policy_to_aspm_state(link->pdev));
+		pcie_set_clkpm(link->pdev, policy_to_clkpm_state(link->pdev));
 	}
 	mutex_unlock(&aspm_lock);
 	up_read(&pci_bus_sem);

@@ -1216,12 +1224,12 @@ module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
  */
 bool pcie_aspm_enabled(struct pci_dev *pdev)
 {
-	struct pcie_link_state *link = pcie_aspm_get_link(pdev);
+	struct pci_dev *dev = pcie_aspm_get_link(pdev);
 
-	if (!link)
+	if (!dev)
 		return false;
 
-	return link->aspm_enabled;
+	return dev->link_state->aspm_enabled;
 }
 EXPORT_SYMBOL_GPL(pcie_aspm_enabled);

@@ -1229,10 +1237,10 @@ static ssize_t aspm_attr_show_common(struct device *dev,
 				     struct device_attribute *attr,
 				     char *buf, u8 state)
 {
-	struct pci_dev *pdev = to_pci_dev(dev);
-	struct pcie_link_state *link = pcie_aspm_get_link(pdev);
+	struct pci_dev *pdev = pcie_aspm_get_link(to_pci_dev(dev));
 
-	return sprintf(buf, "%d\n", (link->aspm_enabled & state) ? 1 : 0);
+	return sprintf(buf, "%d\n",
+		(pdev->link_state->aspm_enabled & state) ? 1 : 0);
 }
 
 static ssize_t aspm_attr_store_common(struct device *dev,

@@ -1240,8 +1248,8 @@ static ssize_t aspm_attr_store_common(struct device *dev,
 				      const char *buf, size_t len, u8 state)
 {
 	struct pci_dev *pdev = to_pci_dev(dev);
-	struct pcie_link_state *link = pcie_aspm_get_link(pdev);
-	struct pci_dev *bridge = link->pdev;
+	struct pci_dev *bridge = pcie_aspm_get_link(pdev);
+	struct pcie_link_state *link = bridge->link_state;
 	bool state_enable;
 
 	if (strtobool(buf, &state_enable) < 0)

@@ -1263,7 +1271,7 @@ static ssize_t aspm_attr_store_common(struct device *dev,
 		bridge->aspm_disable |= state;
 	}
 
-	pcie_config_aspm_link(link, policy_to_aspm_state(link));
+	pcie_config_aspm_link(link->pdev, policy_to_aspm_state(link->pdev));
 
 	mutex_unlock(&aspm_lock);
 	up_read(&pci_bus_sem);

@@ -1291,18 +1299,17 @@ ASPM_ATTR(l1_2_pcipm, L1_2_PCIPM)
 static ssize_t clkpm_show(struct device *dev,
 			  struct device_attribute *attr, char *buf)
 {
-	struct pci_dev *pdev = to_pci_dev(dev);
-	struct pcie_link_state *link = pcie_aspm_get_link(pdev);
+	struct pci_dev *pdev = pcie_aspm_get_link(to_pci_dev(dev));
 
-	return sprintf(buf, "%d\n", link->clkpm_enabled);
+	return sprintf(buf, "%d\n", pdev->link_state->clkpm_enabled);
 }
 
 static ssize_t clkpm_store(struct device *dev,
 			   struct device_attribute *attr,
 			   const char *buf, size_t len)
 {
-	struct pci_dev *pdev = to_pci_dev(dev);
-	struct pcie_link_state *link = pcie_aspm_get_link(pdev);
+	struct pci_dev *pdev = pcie_aspm_get_link(to_pci_dev(dev));
+	struct pcie_link_state *link = pdev->link_state;
 	bool state_enable;
 
 	if (strtobool(buf, &state_enable) < 0)

@@ -1313,7 +1320,7 @@ static ssize_t clkpm_store(struct device *dev,
 
 	link->clkpm_disable = !state_enable;
 	link->pdev->clkpm_disable = !state_enable;
-	pcie_set_clkpm(link, policy_to_clkpm_state(link));
+	pcie_set_clkpm(link->pdev, policy_to_clkpm_state(link->pdev));
 
 	mutex_unlock(&aspm_lock);
 	up_read(&pci_bus_sem);

@@ -1344,8 +1351,8 @@ static umode_t aspm_ctrl_attrs_are_visible(struct kobject *kobj,
 					   struct attribute *a, int n)
 {
 	struct device *dev = kobj_to_dev(kobj);
-	struct pci_dev *pdev = to_pci_dev(dev);
-	struct pcie_link_state *link = pcie_aspm_get_link(pdev);
+	struct pci_dev *pdev = pcie_aspm_get_link(to_pci_dev(dev));
+	struct pcie_link_state *link = pdev->link_state;
 	static const u8 aspm_state_map[] = {
 		ASPM_STATE_L0S,
 		ASPM_STATE_L1,

Signature · 6 lines

2.18.4

_______________________________________________
Linux-kernel-mentees mailing list
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https://lists.linuxfoundation.org/mailman/listinfo/linux-kernel-mentees

Saheed O. Bolarinwa

author

2020-08-22 21:04 UTC #15 lore raw

RFC PATCH v5 15/23 PCI: Replace pcie_link_state based device list with a pci_dev one

In reply to Saheed O. Bolarinwa

- Replace existing pcie_link_state based device list with one based on struct pci_dev one.
- Remove initialisation and declaration of existing list.
- Replace pcie_link_state.sibling with pci_dev.sibling.
- Remove pcie_link_state.sibling.

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 27 +++++++++++----------------
 1 file changed, 11 insertions(+), 16 deletions(-)

drivers/pci/pcie/aspm.c +11 ~~-16~~

index 6f73eb2ca0bd..9ca06f00e98d 100644
@@ -46,7 +46,6 @@ struct pcie_link_state {
 	struct pci_dev *downstream;	/* Downstream component, function 0 */
 	struct pcie_link_state *root;	/* pointer to the root port link */
 	struct pcie_link_state *parent;	/* pointer to the parent Link state */
-	struct list_head sibling;	/* node in link_list */
 
 	/* ASPM state */
 	u32 aspm_support:7;		/* Supported ASPM state */

@@ -74,7 +73,6 @@ struct pcie_link_state {
 static int aspm_disabled, aspm_force;
 static bool aspm_support_enabled = true;
 static DEFINE_MUTEX(aspm_lock);
-static LIST_HEAD(link_list);
 static LIST_HEAD(pdev_link_list);
 
 #define POLICY_DEFAULT 0	/* BIOS default setting */

@@ -856,7 +854,6 @@ static int alloc_pcie_link_state(struct pci_dev *pdev)
 	if (!link)
 		return -1;
 
-	INIT_LIST_HEAD(&link->sibling);
 	INIT_LIST_HEAD(&pdev->sibling);
 	link->pdev = pdev;
 	link->downstream = pci_function_0(pdev->subordinate);

@@ -889,7 +886,6 @@ static int alloc_pcie_link_state(struct pci_dev *pdev)
 		pdev->root = pdev->parent->root;
 	}
 
-	list_add(&link->sibling, &link_list);
 	list_add(&pdev->sibling, &pdev_link_list);
 	pdev->link_state = link;
 	return 0;

@@ -975,20 +971,19 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev)
 }
 
 /* Recheck latencies and update aspm_capable for links under the root */
-static void pcie_update_aspm_capable(struct pci_dev *root_pdev)
+static void pcie_update_aspm_capable(struct pci_dev *root)
 {
-	struct pcie_link_state *root = root_pdev->link_state;
-	struct pcie_link_state *link;
+	struct pci_dev *link;
+
 	BUG_ON(root->parent);
-	list_for_each_entry(link, &link_list, sibling) {
+	list_for_each_entry(link, &pdev_link_list, sibling) {
 		if (link->root != root)
 			continue;
 		link->aspm_capable = link->aspm_support;
-		link->pdev->aspm_capable = link->aspm_support;
 	}
-	list_for_each_entry(link, &link_list, sibling) {
+	list_for_each_entry(link, &pdev_link_list, sibling) {
 		struct pci_dev *child;
-		struct pci_bus *linkbus = link->pdev->subordinate;
+		struct pci_bus *linkbus = link->subordinate;
 		if (link->root != root)
 			continue;
 		list_for_each_entry(child, &linkbus->devices, bus_list) {

@@ -1024,7 +1019,7 @@ void pcie_aspm_exit_link_state(struct pci_dev *pdev)
 
 	/* All functions are removed, so just disable ASPM for the link */
 	pcie_config_aspm_link(parent, 0);
-	list_del(&link->sibling);
+	list_del(&link->pdev->sibling);
 	/* Clock PM is for endpoint device */
 	free_link_state(parent);

@@ -1177,7 +1172,7 @@ static int pcie_aspm_set_policy(const char *val,
 				const struct kernel_param *kp)
 {
 	int i;
-	struct pcie_link_state *link;
+	struct pci_dev *link;
 
 	if (aspm_disabled)
 		return -EPERM;

@@ -1190,9 +1185,9 @@ static int pcie_aspm_set_policy(const char *val,
 	down_read(&pci_bus_sem);
 	mutex_lock(&aspm_lock);
 	aspm_policy = i;
-	list_for_each_entry(link, &link_list, sibling) {
-		pcie_config_aspm_link(link->pdev, policy_to_aspm_state(link->pdev));
-		pcie_set_clkpm(link->pdev, policy_to_clkpm_state(link->pdev));
+	list_for_each_entry(link, &pdev_link_list, sibling) {
+		pcie_config_aspm_link(link, policy_to_aspm_state(link));
+		pcie_set_clkpm(link, policy_to_clkpm_state(link));
 	}
 	mutex_unlock(&aspm_lock);
 	up_read(&pci_bus_sem);

Signature · 6 lines

2.18.4

_______________________________________________
Linux-kernel-mentees mailing list
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https://lists.linuxfoundation.org/mailman/listinfo/linux-kernel-mentees

Saheed O. Bolarinwa

author

2020-08-22 21:04 UTC #16 lore raw

RFC PATCH v5 16/23 PCI: Remove Exit latencies from struct pcie_link_state

In reply to Saheed O. Bolarinwa

- Initialise pci_dev.acceptable instead of pcie_link_state.acceptable
- Replace all access to pcie_link_state.(acceptable && latency_*) with the versions in struct pci_dev
- Remove pcie_link_state.(acceptable && latency_*)

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 24 ++++++------------------
 1 file changed, 6 insertions(+), 18 deletions(-)

drivers/pci/pcie/aspm.c +6 ~~-18~~

index 9ca06f00e98d..56fdf2e7c98a 100644
@@ -59,15 +59,6 @@ struct pcie_link_state {
 	u32 clkpm_enabled:1;		/* Current Clock PM state */
 	u32 clkpm_default:1;		/* Default Clock PM state by BIOS */
 	u32 clkpm_disable:1;		/* Clock PM disabled */
-
-	/* Exit latencies */
-	struct aspm_latency latency_up;	/* Upstream direction exit latency */
-	struct aspm_latency latency_dw;	/* Downstream direction exit latency */
-	/*
-	 * Endpoint acceptable latencies. A pcie downstream port only
-	 * has one slot under it, so at most there are 8 functions.
-	 */
-	struct aspm_latency acceptable[8];
 };
 
 static int aspm_disabled, aspm_force;

@@ -389,19 +380,19 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
 
 	link = endpoint->bus->self->link_state;
 	pdev = endpoint->bus->self;
-	acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
+	acceptable = &link->pdev->acceptable[PCI_FUNC(endpoint->devfn)];
 
 	while (link) {
 		/* Check upstream direction L0s latency */
 		if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
-		    (link->latency_up.l0s > acceptable->l0s)) {
+		    (link->pdev->latency_up.l0s > acceptable->l0s)) {
 			link->aspm_capable &= ~ASPM_STATE_L0S_UP;
 			pdev->aspm_capable &= ~ASPM_STATE_L0S_UP;
 		}
 
 		/* Check downstream direction L0s latency */
 		if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
-		    (link->latency_dw.l0s > acceptable->l0s)) {
+		    (link->pdev->latency_dw.l0s > acceptable->l0s)) {
 			link->aspm_capable &= ~ASPM_STATE_L0S_DW;
 			pdev->aspm_capable &= ~ASPM_STATE_L0S_DW;
 		}

@@ -419,7 +410,8 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
 		 * L1 exit latencies advertised by a device include L1
 		 * substate latencies (and hence do not do any check).
 		 */
-		latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
+		latency = max_t(u32, link->pdev->latency_up.l1,
+						link->pdev->latency_dw.l1);
 		if ((link->aspm_capable & ASPM_STATE_L1) &&
 		    (latency + l1_switch_latency > acceptable->l1)) {
 			link->aspm_capable &= ~ASPM_STATE_L1;

@@ -559,8 +551,6 @@ static void pcie_aspm_cap_init(struct pci_dev *pdev, int blacklist)
 		parent->aspm_enabled |= ASPM_STATE_L0S_DW;
 	}
 
-	link->latency_up.l0s = calc_l0s_latency(parent);
-	link->latency_dw.l0s = calc_l0s_latency(child);
 	parent->latency_up.l0s = calc_l0s_latency(parent);
 	parent->latency_dw.l0s = calc_l0s_latency(child);

@@ -578,8 +568,6 @@ static void pcie_aspm_cap_init(struct pci_dev *pdev, int blacklist)
 		parent->aspm_enabled |= ASPM_STATE_L1;
 	}
 
-	link->latency_up.l1 = calc_l1_latency(parent);
-	link->latency_dw.l1 = calc_l1_latency(child);
 	parent->latency_up.l1 = calc_l1_latency(parent);
 	parent->latency_dw.l1 = calc_l1_latency(child);

@@ -630,7 +618,7 @@ static void pcie_aspm_cap_init(struct pci_dev *pdev, int blacklist)
 	list_for_each_entry(child, &linkbus->devices, bus_list) {
 		u32 reg32, encoding;
 		struct aspm_latency *acceptable =
-			&link->acceptable[PCI_FUNC(child->devfn)];
+			&parent->acceptable[PCI_FUNC(child->devfn)];
 
 		if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
 		    pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)

Signature · 6 lines

2.18.4

_______________________________________________
Linux-kernel-mentees mailing list
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https://lists.linuxfoundation.org/mailman/listinfo/linux-kernel-mentees

Saheed O. Bolarinwa

author

2020-08-22 21:04 UTC #17 lore raw

RFC PATCH v5 17/23 PCI: Remove .clkpm_* from struct pcie_link_state

In reply to Saheed O. Bolarinwa

- Remove initiations of pcie_link_state.clkpm_*
- Replace all access to pcie_link_state.clkpm_* with pci_pdev.clkpm_*
- Remove pcie_link_state.clkpm_*

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 23 +++++------------------
 1 file changed, 5 insertions(+), 18 deletions(-)

drivers/pci/pcie/aspm.c +5 ~~-18~~

index 56fdf2e7c98a..27a590fe6b23 100644
@@ -53,12 +53,6 @@ struct pcie_link_state {
 	u32 aspm_capable:7;		/* Capable ASPM state with latency */
 	u32 aspm_default:7;		/* Default ASPM state by BIOS */
 	u32 aspm_disable:7;		/* Disabled ASPM state */
-
-	/* Clock PM state */
-	u32 clkpm_capable:1;		/* Clock PM capable? */
-	u32 clkpm_enabled:1;		/* Current Clock PM state */
-	u32 clkpm_default:1;		/* Default Clock PM state by BIOS */
-	u32 clkpm_disable:1;		/* Clock PM disabled */
 };
 
 static int aspm_disabled, aspm_force;

@@ -119,7 +113,7 @@ static int policy_to_clkpm_state(struct pci_dev *pdev)
 		/* Enable Clock PM */
 		return 1;
 	case POLICY_DEFAULT:
-		return pdev->link_state->clkpm_default;
+		return pdev->clkpm_default;
 	}
 	return 0;
 }

@@ -135,7 +129,6 @@ static void pcie_set_clkpm_nocheck(struct pci_dev *pdev, int enable)
 		pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
 						   PCI_EXP_LNKCTL_CLKREQ_EN,
 						   val);
-	link->clkpm_enabled = !!enable;
 	link->pdev->clkpm_enabled = !!enable;
 }

@@ -146,10 +139,10 @@ static void pcie_set_clkpm(struct pci_dev *pdev, int enable)
 	 * Don't enable Clock PM if the link is not Clock PM capable
 	 * or Clock PM is disabled
 	 */
-	if (!link->clkpm_capable || link->clkpm_disable)
+	if (!pdev->clkpm_capable || pdev->clkpm_disable)
 		enable = 0;
 	/* Need nothing if the specified equals to current state */
-	if (link->clkpm_enabled == enable)
+	if (pdev->clkpm_enabled == enable)
 		return;
 	pcie_set_clkpm_nocheck(link->pdev, enable);
 }

@@ -173,10 +166,6 @@ static void pcie_clkpm_cap_init(struct pci_dev *pdev, int blacklist)
 		if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
 			enabled = 0;
 	}
-	link->clkpm_enabled = enabled;
-	link->clkpm_default = enabled;
-	link->clkpm_capable = capable;
-	link->clkpm_disable = blacklist ? 1 : 0;
 	link->pdev->clkpm_enabled = enabled;
 	link->pdev->clkpm_default = enabled;
 	link->pdev->clkpm_capable = capable;

@@ -1124,7 +1113,6 @@ static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
 	pcie_config_aspm_link(link->pdev, policy_to_aspm_state(link->pdev));
 
 	if (state & PCIE_LINK_STATE_CLKPM) {
-		link->clkpm_disable = 1;
 		bridge->clkpm_disable = 1;
 	}
 	pcie_set_clkpm(link->pdev, policy_to_clkpm_state(link->pdev));

@@ -1284,7 +1272,7 @@ static ssize_t clkpm_show(struct device *dev,
 {
 	struct pci_dev *pdev = pcie_aspm_get_link(to_pci_dev(dev));
 
-	return sprintf(buf, "%d\n", pdev->link_state->clkpm_enabled);
+	return sprintf(buf, "%d\n", pdev->clkpm_enabled);
 }
 
 static ssize_t clkpm_store(struct device *dev,

@@ -1301,7 +1289,6 @@ static ssize_t clkpm_store(struct device *dev,
 	down_read(&pci_bus_sem);
 	mutex_lock(&aspm_lock);
 
-	link->clkpm_disable = !state_enable;
 	link->pdev->clkpm_disable = !state_enable;
 	pcie_set_clkpm(link->pdev, policy_to_clkpm_state(link->pdev));

@@ -1349,7 +1336,7 @@ static umode_t aspm_ctrl_attrs_are_visible(struct kobject *kobj,
 		return 0;
 
 	if (n == 0)
-		return link->clkpm_capable ? a->mode : 0;
+		return pdev->clkpm_capable ? a->mode : 0;
 
 	return link->aspm_capable & aspm_state_map[n - 1] ? a->mode : 0;
 }

Signature · 6 lines

2.18.4

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Saheed O. Bolarinwa

author

2020-08-22 21:04 UTC #18 lore raw

RFC PATCH v5 18/23 PCI: Remove .aspm_* from struct pcie_link_state

In reply to Saheed O. Bolarinwa

- Remove initiations of pcie_link_state.aspm_*
- Replace all access to pcie_link_state.aspm_* with pci_pdev.aspm_*
- Remove pcie_link_state.aspm_*
- Do few cleaups

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 137 +++++++++++-----------------------------
 1 file changed, 38 insertions(+), 99 deletions(-)

drivers/pci/pcie/aspm.c +38 ~~-99~~

index 27a590fe6b23..8d5a38081753 100644
@@ -46,13 +46,6 @@ struct pcie_link_state {
 	struct pci_dev *downstream;	/* Downstream component, function 0 */
 	struct pcie_link_state *root;	/* pointer to the root port link */
 	struct pcie_link_state *parent;	/* pointer to the parent Link state */
-
-	/* ASPM state */
-	u32 aspm_support:7;		/* Supported ASPM state */
-	u32 aspm_enabled:7;		/* Enabled ASPM state */
-	u32 aspm_capable:7;		/* Capable ASPM state with latency */
-	u32 aspm_default:7;		/* Default ASPM state by BIOS */
-	u32 aspm_disable:7;		/* Disabled ASPM state */
 };
 
 static int aspm_disabled, aspm_force;

@@ -97,7 +90,7 @@ static int policy_to_aspm_state(struct pci_dev *pdev)
 		/* Enable Everything */
 		return ASPM_STATE_ALL;
 	case POLICY_DEFAULT:
-		return pdev->link_state->aspm_default;
+		return pdev->aspm_default;
 	}
 	return 0;
 }

@@ -373,18 +366,14 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
 
 	while (link) {
 		/* Check upstream direction L0s latency */
-		if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
-		    (link->pdev->latency_up.l0s > acceptable->l0s)) {
-			link->aspm_capable &= ~ASPM_STATE_L0S_UP;
+		if ((link->pdev->aspm_capable & ASPM_STATE_L0S_UP) &&
+		    (link->pdev->latency_up.l0s > acceptable->l0s))
 			pdev->aspm_capable &= ~ASPM_STATE_L0S_UP;
-		}
 
 		/* Check downstream direction L0s latency */
-		if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
-		    (link->pdev->latency_dw.l0s > acceptable->l0s)) {
-			link->aspm_capable &= ~ASPM_STATE_L0S_DW;
+		if ((link->pdev->aspm_capable & ASPM_STATE_L0S_DW) &&
+		    (link->pdev->latency_dw.l0s > acceptable->l0s))
 			pdev->aspm_capable &= ~ASPM_STATE_L0S_DW;
-		}
 
 		/*
 		 * Check L1 latency.

@@ -401,11 +390,9 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
 		 */
 		latency = max_t(u32, link->pdev->latency_up.l1,
 						link->pdev->latency_dw.l1);
-		if ((link->aspm_capable & ASPM_STATE_L1) &&
-		    (latency + l1_switch_latency > acceptable->l1)) {
-			link->aspm_capable &= ~ASPM_STATE_L1;
+		if ((link->pdev->aspm_capable & ASPM_STATE_L1) &&
+		    (latency + l1_switch_latency > acceptable->l1))
 			pdev->aspm_capable &= ~ASPM_STATE_L1;
-		}
 
 		l1_switch_latency += 1000;

@@ -438,7 +425,7 @@ static void aspm_calc_l1ss_ctl_values(struct pci_dev *pdev,
 	struct pci_dev *dw_pdev = link->downstream;
 	struct pci_dev *up_pdev = link->pdev;
 
-	if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
+	if (!(link->pdev->aspm_support & ASPM_STATE_L1_2_MASK))
 		return;
 
 	/* Choose the greater of the two Port Common_Mode_Restore_Times */

@@ -493,8 +480,6 @@ static void pcie_aspm_cap_init(struct pci_dev *pdev, int blacklist)
 
 	if (blacklist) {
 		/* Set enabled/disable so that we will disable ASPM later */
-		link->aspm_enabled = ASPM_STATE_ALL;
-		link->aspm_disable = ASPM_STATE_ALL;
 		parent->aspm_enabled = ASPM_STATE_ALL;
 		parent->aspm_disable = ASPM_STATE_ALL;
 		return;

@@ -525,20 +510,14 @@ static void pcie_aspm_cap_init(struct pci_dev *pdev, int blacklist)
 	 */
 	if (((parent->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10) &
 			((child->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10) &
-			PCIE_LINK_STATE_L0S) {
-		link->aspm_support |= ASPM_STATE_L0S;
+			PCIE_LINK_STATE_L0S)
 		parent->aspm_support |= ASPM_STATE_L0S;
-	}
 
-	if (get_aspm_enable(child) & PCIE_LINK_STATE_L0S) {
-		link->aspm_enabled |= ASPM_STATE_L0S_UP;
+	if (get_aspm_enable(child) & PCIE_LINK_STATE_L0S)
 		parent->aspm_enabled |= ASPM_STATE_L0S_UP;
-	}
 
-	if (get_aspm_enable(parent) & PCIE_LINK_STATE_L0S) {
-		link->aspm_enabled |= ASPM_STATE_L0S_DW;
+	if (get_aspm_enable(parent) & PCIE_LINK_STATE_L0S)
 		parent->aspm_enabled |= ASPM_STATE_L0S_DW;
-	}
 
 	parent->latency_up.l0s = calc_l0s_latency(parent);
 	parent->latency_dw.l0s = calc_l0s_latency(child);

@@ -546,61 +525,39 @@ static void pcie_aspm_cap_init(struct pci_dev *pdev, int blacklist)
 	/* Setup L1 state */
 	if (((parent->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10) &
 			((child->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10) &
-			PCIE_LINK_STATE_L1) {
-		link->aspm_support |= ASPM_STATE_L1;
+			PCIE_LINK_STATE_L1)
 		parent->aspm_support |= ASPM_STATE_L1;
-	}
 
 	if (get_aspm_enable(parent) & get_aspm_enable(child) &
-			    PCIE_LINK_STATE_L1) {
-		link->aspm_enabled |= ASPM_STATE_L1;
+			    PCIE_LINK_STATE_L1)
 		parent->aspm_enabled |= ASPM_STATE_L1;
-	}
 
 	parent->latency_up.l1 = calc_l1_latency(parent);
 	parent->latency_dw.l1 = calc_l1_latency(child);
 
 	/* Setup L1 substate */
-	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1) {
-		link->aspm_support |= ASPM_STATE_L1_1;
+	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
 		parent->aspm_support |= ASPM_STATE_L1_1;
-	}
-	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2) {
-		link->aspm_support |= ASPM_STATE_L1_2;
+	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
 		parent->aspm_support |= ASPM_STATE_L1_2;
-	}
-	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1) {
-		link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
+	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
 		parent->aspm_support |= ASPM_STATE_L1_1_PCIPM;
-	}
-	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2) {
-		link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
+	if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
 		parent->aspm_support |= ASPM_STATE_L1_2_PCIPM;
-	}
 
-	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1) {
-		link->aspm_enabled |= ASPM_STATE_L1_1;
+	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
 		parent->aspm_enabled |= ASPM_STATE_L1_1;
-	}
-	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2) {
-		link->aspm_enabled |= ASPM_STATE_L1_2;
+	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
 		parent->aspm_enabled |= ASPM_STATE_L1_2;
-	}
-	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1) {
-		link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
+	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
 		parent->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
-	}
-	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2) {
-		link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
+	if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
 		parent->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
-	}
 
 	/* Save default state */
-	link->aspm_default = link->aspm_enabled;
 	parent->aspm_default = parent->aspm_enabled;
 
 	/* Setup initial capable state. Will be updated later */
-	link->aspm_capable = link->aspm_support;
 	parent->aspm_capable = parent->aspm_support;
 
 	/* Get and check endpoint acceptable latencies */

@@ -729,7 +686,7 @@ static void pcie_config_aspm_link(struct pci_dev *pdev, u32 state)
 	struct pci_bus *linkbus = parent->subordinate;
 
 	/* Enable only the states that were not explicitly disabled */
-	state &= (link->aspm_capable & ~link->aspm_disable);
+	state &= (link->pdev->aspm_capable & ~link->pdev->aspm_disable);
 
 	/* Can't enable any substates if L1 is not enabled */
 	if (!(state & ASPM_STATE_L1))

@@ -738,11 +695,11 @@ static void pcie_config_aspm_link(struct pci_dev *pdev, u32 state)
 	/* Spec says both ports must be in D0 before enabling PCI PM substates*/
 	if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
 		state &= ~ASPM_STATE_L1_SS_PCIPM;
-		state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
+		state |= (link->pdev->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
 	}
 
 	/* Nothing to do if the link is already in the requested state */
-	if (link->aspm_enabled == state)
+	if (link->pdev->aspm_enabled == state)
 		return;
 	/* Convert ASPM state to upstream/downstream ASPM register state */
 	if (state & ASPM_STATE_L0S_UP)

@@ -754,7 +711,7 @@ static void pcie_config_aspm_link(struct pci_dev *pdev, u32 state)
 		dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
 	}
 
-	if (link->aspm_capable & ASPM_STATE_L1SS)
+	if (link->pdev->aspm_capable & ASPM_STATE_L1SS)
 		pcie_config_aspm_l1ss(parent, state);
 
 	/*

@@ -770,7 +727,6 @@ static void pcie_config_aspm_link(struct pci_dev *pdev, u32 state)
 	if (!(state & ASPM_STATE_L1))
 		pcie_config_aspm_dev(parent, upstream);
 
-	link->aspm_enabled = state;
 	parent->aspm_enabled = state;
 }

@@ -1085,31 +1041,20 @@ static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
 	if (sem)
 		down_read(&pci_bus_sem);
 	mutex_lock(&aspm_lock);
-	if (state & PCIE_LINK_STATE_L0S) {
-		link->aspm_disable |= ASPM_STATE_L0S;
+	if (state & PCIE_LINK_STATE_L0S)
 		bridge->aspm_disable |= ASPM_STATE_L0S;
-	}
-	if (state & PCIE_LINK_STATE_L1) {
+	if (state & PCIE_LINK_STATE_L1)
 		/* L1 PM substates require L1 */
-		link->aspm_disable |= ASPM_STATE_L1 | ASPM_STATE_L1SS;
 		bridge->aspm_disable |= ASPM_STATE_L1 | ASPM_STATE_L1SS;
-	}
-	if (state & PCIE_LINK_STATE_L1_1) {
-		link->aspm_disable |= ASPM_STATE_L1_1;
+	if (state & PCIE_LINK_STATE_L1_1)
 		bridge->aspm_disable |= ASPM_STATE_L1_1;
-	}
-	if (state & PCIE_LINK_STATE_L1_2) {
-		link->aspm_disable |= ASPM_STATE_L1_2;
+	if (state & PCIE_LINK_STATE_L1_2)
 		bridge->aspm_disable |= ASPM_STATE_L1_2;
-	}
-	if (state & PCIE_LINK_STATE_L1_1_PCIPM) {
-		link->aspm_disable |= ASPM_STATE_L1_1_PCIPM;
+	if (state & PCIE_LINK_STATE_L1_1_PCIPM)
 		bridge->aspm_disable |= ASPM_STATE_L1_1_PCIPM;
-	}
-	if (state & PCIE_LINK_STATE_L1_2_PCIPM) {
-		link->aspm_disable |= ASPM_STATE_L1_2_PCIPM;
+	if (state & PCIE_LINK_STATE_L1_2_PCIPM)
 		bridge->aspm_disable |= ASPM_STATE_L1_2_PCIPM;
-	}
+
 	pcie_config_aspm_link(link->pdev, policy_to_aspm_state(link->pdev));
 
 	if (state & PCIE_LINK_STATE_CLKPM) {

@@ -1200,7 +1145,7 @@ bool pcie_aspm_enabled(struct pci_dev *pdev)
 	if (!dev)
 		return false;
 
-	return dev->link_state->aspm_enabled;
+	return dev->aspm_enabled;
 }
 EXPORT_SYMBOL_GPL(pcie_aspm_enabled);

@@ -1211,7 +1156,7 @@ static ssize_t aspm_attr_show_common(struct device *dev,
 	struct pci_dev *pdev = pcie_aspm_get_link(to_pci_dev(dev));
 
 	return sprintf(buf, "%d\n",
-		(pdev->link_state->aspm_enabled & state) ? 1 : 0);
+		(pdev->aspm_enabled & state) ? 1 : 0);
 }
 
 static ssize_t aspm_attr_store_common(struct device *dev,

@@ -1230,17 +1175,12 @@ static ssize_t aspm_attr_store_common(struct device *dev,
 	mutex_lock(&aspm_lock);
 
 	if (state_enable) {
-		link->aspm_disable &= ~state;
 		bridge->aspm_disable &= ~state;
 		/* need to enable L1 for substates */
-		if (state & ASPM_STATE_L1SS) {
-			link->aspm_disable &= ~ASPM_STATE_L1;
+		if (state & ASPM_STATE_L1SS)
 			bridge->aspm_disable &= ~ASPM_STATE_L1;
-		}
-	} else {
-		link->aspm_disable |= state;
+	} else
 		bridge->aspm_disable |= state;
-	}
 
 	pcie_config_aspm_link(link->pdev, policy_to_aspm_state(link->pdev));

@@ -1322,7 +1262,6 @@ static umode_t aspm_ctrl_attrs_are_visible(struct kobject *kobj,
 {
 	struct device *dev = kobj_to_dev(kobj);
 	struct pci_dev *pdev = pcie_aspm_get_link(to_pci_dev(dev));
-	struct pcie_link_state *link = pdev->link_state;
 	static const u8 aspm_state_map[] = {
 		ASPM_STATE_L0S,
 		ASPM_STATE_L1,

@@ -1332,13 +1271,13 @@ static umode_t aspm_ctrl_attrs_are_visible(struct kobject *kobj,
 		ASPM_STATE_L1_2_PCIPM,
 	};
 
-	if (aspm_disabled || !link)
+	if (aspm_disabled || !pdev)
 		return 0;
 
 	if (n == 0)
 		return pdev->clkpm_capable ? a->mode : 0;
 
-	return link->aspm_capable & aspm_state_map[n - 1] ? a->mode : 0;
+	return pdev->aspm_capable & aspm_state_map[n - 1] ? a->mode : 0;
 }
 
 const struct attribute_group aspm_ctrl_attr_group = {

Signature · 6 lines

2.18.4

_______________________________________________
Linux-kernel-mentees mailing list
[email protected]
https://lists.linuxfoundation.org/mailman/listinfo/linux-kernel-mentees

Saheed O. Bolarinwa

author

2020-08-22 21:04 UTC #19 lore raw

RFC PATCH v5 19/23 PCI: Remove .parent from struct pcie_link_state

In reply to Saheed O. Bolarinwa

- Remove initiations of pcie_link_state.parent
- Replace all access to pcie_link_state.parent with pci_pdev.parent
- Remove pcie_link_state.parent

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

drivers/pci/pcie/aspm.c +2 -5

index 8d5a38081753..14b9da0a4efd 100644
@@ -45,7 +45,6 @@ struct pcie_link_state {
 	struct pci_dev *pdev;		/* Upstream component of the Link */
 	struct pci_dev *downstream;	/* Downstream component, function 0 */
 	struct pcie_link_state *root;	/* pointer to the root port link */
-	struct pcie_link_state *parent;	/* pointer to the parent Link state */
 };
 
 static int aspm_disabled, aspm_force;

@@ -396,7 +395,6 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
 
 		l1_switch_latency += 1000;
 
-		link = link->parent;
 		pdev = pdev->parent;
 	}
 }

@@ -813,8 +811,7 @@ static int alloc_pcie_link_state(struct pci_dev *pdev)
 			return -1;
 		}
 
-		link->parent = parent;
-		link->root = link->parent->root;
+		link->root = link->pdev->parent->link_state->root;
 		pdev->parent = pdev->bus->parent->self;
 		pdev->root = pdev->parent->root;
 	}

@@ -948,7 +945,7 @@ void pcie_aspm_exit_link_state(struct pci_dev *pdev)
 
 	link = parent->link_state;
 	root = link->root;
-	parent_link = link->parent;
+	parent_link = link->pdev->parent->link_state;
 
 	/* All functions are removed, so just disable ASPM for the link */
 	pcie_config_aspm_link(parent, 0);

Signature · 6 lines

2.18.4

_______________________________________________
Linux-kernel-mentees mailing list
[email protected]
https://lists.linuxfoundation.org/mailman/listinfo/linux-kernel-mentees

Saheed O. Bolarinwa

author

2020-08-22 21:04 UTC #20 lore raw

RFC PATCH v5 20/23 PCI: Remove .root from struct pcie_link_state

In reply to Saheed O. Bolarinwa

- Remove initiations of pcie_link_state.root
- Replace all access to pcie_link_state.root with pci_pdev.root
- Remove pcie_link_state.root
- Do few cleanups

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

drivers/pci/pcie/aspm.c +4 ~~-12~~

index 14b9da0a4efd..244b28534e7f 100644
@@ -44,7 +44,6 @@
 struct pcie_link_state {
 	struct pci_dev *pdev;		/* Upstream component of the Link */
 	struct pci_dev *downstream;	/* Downstream component, function 0 */
-	struct pcie_link_state *root;	/* pointer to the root port link */
 };
 
 static int aspm_disabled, aspm_force;

@@ -800,18 +799,13 @@ static int alloc_pcie_link_state(struct pci_dev *pdev)
 	if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
 	    pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
 	    !pdev->bus->parent->self) {
-		link->root = link;
 		pdev->root = pdev;
 	} else {
-		struct pcie_link_state *parent;
-
-		parent = pdev->bus->parent->self->link_state;
-		if (!parent) {
+		if (!pdev->bus->parent->self) {
 			kfree(link);
 			return -1;
 		}
 
-		link->root = link->pdev->parent->link_state->root;
 		pdev->parent = pdev->bus->parent->self;
 		pdev->root = pdev->parent->root;
 	}

@@ -944,7 +938,7 @@ void pcie_aspm_exit_link_state(struct pci_dev *pdev)
 		goto out;
 
 	link = parent->link_state;
-	root = link->root;
+	root = link->pdev->root->link_state;
 	parent_link = link->pdev->parent->link_state;
 
 	/* All functions are removed, so just disable ASPM for the link */

@@ -966,9 +960,7 @@ void pcie_aspm_exit_link_state(struct pci_dev *pdev)
 /* @pdev: the root port or switch downstream port */
 void pcie_aspm_pm_state_change(struct pci_dev *pdev)
 {
-	struct pcie_link_state *link = pdev->link_state;
-
-	if (aspm_disabled || !link)
+	if (aspm_disabled || !pdev)
 		return;
 	/*
 	 * Devices changed PM state, we should recheck if latency

@@ -976,7 +968,7 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev)
 	 */
 	down_read(&pci_bus_sem);
 	mutex_lock(&aspm_lock);
-	pcie_update_aspm_capable(link->root->pdev);
+	pcie_update_aspm_capable(pdev->root);
 	pcie_config_aspm_path(pdev);
 	mutex_unlock(&aspm_lock);
 	up_read(&pci_bus_sem);

Signature · 6 lines

2.18.4

_______________________________________________
Linux-kernel-mentees mailing list
[email protected]
https://lists.linuxfoundation.org/mailman/listinfo/linux-kernel-mentees

Saheed O. Bolarinwa

author

2020-08-22 21:04 UTC #21 lore raw

RFC PATCH v5 21/23 PCI: Remove .downstream from struct pcie_link_state

In reply to Saheed O. Bolarinwa

- Remove initiations of pcie_link_state.downstream
- Replace all access to pcie_link_state.downstream with pci_pdev.downstream
- Remove pcie_link_state.downstream

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

drivers/pci/pcie/aspm.c +4 -6

index 244b28534e7f..dd21c17296d7 100644
@@ -43,7 +43,6 @@
 
 struct pcie_link_state {
 	struct pci_dev *pdev;		/* Upstream component of the Link */
-	struct pci_dev *downstream;	/* Downstream component, function 0 */
 };
 
 static int aspm_disabled, aspm_force;

@@ -419,7 +418,7 @@ static void aspm_calc_l1ss_ctl_values(struct pci_dev *pdev,
 	struct pcie_link_state *link = pdev->link_state;
 	u32 val1, val2, scale1, scale2;
 	u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
-	struct pci_dev *dw_pdev = link->downstream;
+	struct pci_dev *dw_pdev = link->pdev->downstream;
 	struct pci_dev *up_pdev = link->pdev;
 
 	if (!(link->pdev->aspm_support & ASPM_STATE_L1_2_MASK))

@@ -471,7 +470,7 @@ static u32 get_aspm_enable(struct pci_dev *pdev)
 static void pcie_aspm_cap_init(struct pci_dev *pdev, int blacklist)
 {
 	struct pcie_link_state *link = pdev->link_state;
-	struct pci_dev *child = link->downstream, *parent = link->pdev;
+	struct pci_dev *child = link->pdev->downstream, *parent = link->pdev;
 	struct pci_bus *linkbus = parent->subordinate;
 	u32 up_l1ss_ctl1, dw_l1ss_ctl1;

@@ -595,7 +594,7 @@ static void pcie_config_aspm_l1ss(struct pci_dev *pdev, u32 state)
 {
 	struct pcie_link_state *link = pdev->link_state;
 	u32 val, enable_req, ctl1, ctl2;
-	struct pci_dev *child = link->downstream, *parent = link->pdev;
+	struct pci_dev *child = link->pdev->downstream, *parent = link->pdev;
 	int up_cap_ptr = parent->l1ss_cap_ptr;
 	int dw_cap_ptr = child->l1ss_cap_ptr;

@@ -679,7 +678,7 @@ static void pcie_config_aspm_link(struct pci_dev *pdev, u32 state)
 {
 	struct pcie_link_state *link = pdev->link_state;
 	u32 upstream = 0, dwstream = 0;
-	struct pci_dev *child = link->downstream, *parent = link->pdev;
+	struct pci_dev *child = link->pdev->downstream, *parent = link->pdev;
 	struct pci_bus *linkbus = parent->subordinate;
 
 	/* Enable only the states that were not explicitly disabled */

@@ -786,7 +785,6 @@ static int alloc_pcie_link_state(struct pci_dev *pdev)
 
 	INIT_LIST_HEAD(&pdev->sibling);
 	link->pdev = pdev;
-	link->downstream = pci_function_0(pdev->subordinate);
 	pdev->downstream = pci_function_0(pdev->subordinate);
 
 	/*

Signature · 6 lines

2.18.4

_______________________________________________
Linux-kernel-mentees mailing list
[email protected]
https://lists.linuxfoundation.org/mailman/listinfo/linux-kernel-mentees

Saheed O. Bolarinwa

author

2020-08-22 21:04 UTC #22 lore raw

RFC PATCH v5 22/23 PCI: Remove .pdev from struct pcie_link_state

In reply to Saheed O. Bolarinwa

- Remove initiations of pcie_link_state.pdev
- Replace all access to pcie_link_state.pdev with pci_pdev.pdev
- Remove pcie_link_state.pdev
- Fix bug if(!alloc_pcie_link_state())

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 137 +++++++++++++++-------------------------
 1 file changed, 52 insertions(+), 85 deletions(-)

drivers/pci/pcie/aspm.c +52 ~~-85~~

index dd21c17296d7..2fc2b958e6d2 100644
@@ -42,7 +42,6 @@
 				 ASPM_STATE_L1SS)
 
 struct pcie_link_state {
-	struct pci_dev *pdev;		/* Upstream component of the Link */
 };
 
 static int aspm_disabled, aspm_force;

@@ -110,21 +109,19 @@ static int policy_to_clkpm_state(struct pci_dev *pdev)
 
 static void pcie_set_clkpm_nocheck(struct pci_dev *pdev, int enable)
 {
-	struct pcie_link_state *link = pdev->link_state;
 	struct pci_dev *child;
-	struct pci_bus *linkbus = link->pdev->subordinate;
+	struct pci_bus *linkbus = pdev->subordinate;
 	u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
 
 	list_for_each_entry(child, &linkbus->devices, bus_list)
 		pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
 						   PCI_EXP_LNKCTL_CLKREQ_EN,
 						   val);
-	link->pdev->clkpm_enabled = !!enable;
+	pdev->clkpm_enabled = !!enable;
 }
 
 static void pcie_set_clkpm(struct pci_dev *pdev, int enable)
 {
-	struct pcie_link_state *link = pdev->link_state;
 	/*
 	 * Don't enable Clock PM if the link is not Clock PM capable
 	 * or Clock PM is disabled

@@ -134,16 +131,15 @@ static void pcie_set_clkpm(struct pci_dev *pdev, int enable)
 	/* Need nothing if the specified equals to current state */
 	if (pdev->clkpm_enabled == enable)
 		return;
-	pcie_set_clkpm_nocheck(link->pdev, enable);
+	pcie_set_clkpm_nocheck(pdev, enable);
 }
 
 static void pcie_clkpm_cap_init(struct pci_dev *pdev, int blacklist)
 {
-	struct pcie_link_state *link = pdev->link_state;
 	int capable = 1, enabled = 1;
 	u16 reg16;
 	struct pci_dev *child;
-	struct pci_bus *linkbus = link->pdev->subordinate;
+	struct pci_bus *linkbus = pdev->subordinate;
 
 	/* All functions should have the same cap and state, take the worst */
 	list_for_each_entry(child, &linkbus->devices, bus_list) {

@@ -156,10 +152,10 @@ static void pcie_clkpm_cap_init(struct pci_dev *pdev, int blacklist)
 		if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
 			enabled = 0;
 	}
-	link->pdev->clkpm_enabled = enabled;
-	link->pdev->clkpm_default = enabled;
-	link->pdev->clkpm_capable = capable;
-	link->pdev->clkpm_disable = blacklist ? 1 : 0;
+	pdev->clkpm_enabled = enabled;
+	pdev->clkpm_default = enabled;
+	pdev->clkpm_capable = capable;
+	pdev->clkpm_disable = blacklist ? 1 : 0;
 }
 
 static bool pcie_retrain_link(struct pci_dev *parent)

@@ -349,7 +345,6 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
 {
 	u32 latency, l1_switch_latency = 0;
 	struct aspm_latency *acceptable;
-	struct pcie_link_state *link;
 	struct pci_dev *pdev;
 
 	/* Device not in D0 doesn't need latency check */

@@ -357,19 +352,18 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
 	    (endpoint->current_state != PCI_UNKNOWN))
 		return;
 
-	link = endpoint->bus->self->link_state;
 	pdev = endpoint->bus->self;
-	acceptable = &link->pdev->acceptable[PCI_FUNC(endpoint->devfn)];
+	acceptable = &pdev->acceptable[PCI_FUNC(endpoint->devfn)];
 
-	while (link) {
+	while (pdev) {
 		/* Check upstream direction L0s latency */
-		if ((link->pdev->aspm_capable & ASPM_STATE_L0S_UP) &&
-		    (link->pdev->latency_up.l0s > acceptable->l0s))
+		if ((pdev->aspm_capable & ASPM_STATE_L0S_UP) &&
+		    (pdev->latency_up.l0s > acceptable->l0s))
 			pdev->aspm_capable &= ~ASPM_STATE_L0S_UP;
 
 		/* Check downstream direction L0s latency */
-		if ((link->pdev->aspm_capable & ASPM_STATE_L0S_DW) &&
-		    (link->pdev->latency_dw.l0s > acceptable->l0s))
+		if ((pdev->aspm_capable & ASPM_STATE_L0S_DW) &&
+		    (pdev->latency_dw.l0s > acceptable->l0s))
 			pdev->aspm_capable &= ~ASPM_STATE_L0S_DW;
 
 		/*

@@ -385,9 +379,8 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
 		 * L1 exit latencies advertised by a device include L1
 		 * substate latencies (and hence do not do any check).
 		 */
-		latency = max_t(u32, link->pdev->latency_up.l1,
-						link->pdev->latency_dw.l1);
-		if ((link->pdev->aspm_capable & ASPM_STATE_L1) &&
+		latency = max_t(u32, pdev->latency_up.l1, pdev->latency_dw.l1);
+		if ((pdev->aspm_capable & ASPM_STATE_L1) &&
 		    (latency + l1_switch_latency > acceptable->l1))
 			pdev->aspm_capable &= ~ASPM_STATE_L1;

@@ -412,16 +405,14 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
 }
 
 /* Calculate L1.2 PM substate timing parameters */
-static void aspm_calc_l1ss_ctl_values(struct pci_dev *pdev,
+static void aspm_calc_l1ss_ctl_values(struct pci_dev *up_pdev,
 						u32 *ctl1, u32 *ctl2)
 {
-	struct pcie_link_state *link = pdev->link_state;
 	u32 val1, val2, scale1, scale2;
 	u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
-	struct pci_dev *dw_pdev = link->pdev->downstream;
-	struct pci_dev *up_pdev = link->pdev;
+	struct pci_dev *dw_pdev = up_pdev->downstream;
 
-	if (!(link->pdev->aspm_support & ASPM_STATE_L1_2_MASK))
+	if (!(up_pdev->aspm_support & ASPM_STATE_L1_2_MASK))
 		return;
 
 	/* Choose the greater of the two Port Common_Mode_Restore_Times */

@@ -467,10 +458,9 @@ static u32 get_aspm_enable(struct pci_dev *pdev)
 	return (reg16 & PCI_EXP_LNKCTL_ASPMC);
 }
 
-static void pcie_aspm_cap_init(struct pci_dev *pdev, int blacklist)
+static void pcie_aspm_cap_init(struct pci_dev *parent, int blacklist)
 {
-	struct pcie_link_state *link = pdev->link_state;
-	struct pci_dev *child = link->pdev->downstream, *parent = link->pdev;
+	struct pci_dev *child = parent->downstream;
 	struct pci_bus *linkbus = parent->subordinate;
 	u32 up_l1ss_ctl1, dw_l1ss_ctl1;

@@ -590,11 +580,10 @@ static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
 }
 
 /* Configure the ASPM L1 substates */
-static void pcie_config_aspm_l1ss(struct pci_dev *pdev, u32 state)
+static void pcie_config_aspm_l1ss(struct pci_dev *parent, u32 state)
 {
-	struct pcie_link_state *link = pdev->link_state;
 	u32 val, enable_req, ctl1, ctl2;
-	struct pci_dev *child = link->pdev->downstream, *parent = link->pdev;
+	struct pci_dev *child = parent->downstream;
 	int up_cap_ptr = parent->l1ss_cap_ptr;
 	int dw_cap_ptr = child->l1ss_cap_ptr;

@@ -674,15 +663,14 @@ static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
 					   PCI_EXP_LNKCTL_ASPMC, val);
 }
 
-static void pcie_config_aspm_link(struct pci_dev *pdev, u32 state)
+static void pcie_config_aspm_link(struct pci_dev *parent, u32 state)
 {
-	struct pcie_link_state *link = pdev->link_state;
 	u32 upstream = 0, dwstream = 0;
-	struct pci_dev *child = link->pdev->downstream, *parent = link->pdev;
+	struct pci_dev *child = parent->downstream;
 	struct pci_bus *linkbus = parent->subordinate;
 
 	/* Enable only the states that were not explicitly disabled */
-	state &= (link->pdev->aspm_capable & ~link->pdev->aspm_disable);
+	state &= (parent->aspm_capable & ~parent->aspm_disable);
 
 	/* Can't enable any substates if L1 is not enabled */
 	if (!(state & ASPM_STATE_L1))

@@ -691,11 +679,11 @@ static void pcie_config_aspm_link(struct pci_dev *pdev, u32 state)
 	/* Spec says both ports must be in D0 before enabling PCI PM substates*/
 	if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
 		state &= ~ASPM_STATE_L1_SS_PCIPM;
-		state |= (link->pdev->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
+		state |= (parent->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
 	}
 
 	/* Nothing to do if the link is already in the requested state */
-	if (link->pdev->aspm_enabled == state)
+	if (parent->aspm_enabled == state)
 		return;
 	/* Convert ASPM state to upstream/downstream ASPM register state */
 	if (state & ASPM_STATE_L0S_UP)

@@ -707,7 +695,7 @@ static void pcie_config_aspm_link(struct pci_dev *pdev, u32 state)
 		dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
 	}
 
-	if (link->pdev->aspm_capable & ASPM_STATE_L1SS)
+	if (parent->aspm_capable & ASPM_STATE_L1SS)
 		pcie_config_aspm_l1ss(parent, state);
 
 	/*

@@ -777,15 +765,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
 
 static int alloc_pcie_link_state(struct pci_dev *pdev)
 {
-	struct pcie_link_state *link;
-
-	link = kzalloc(sizeof(*link), GFP_KERNEL);
-	if (!link)
-		return -1;
-
 	INIT_LIST_HEAD(&pdev->sibling);
-	link->pdev = pdev;
-	pdev->downstream = pci_function_0(pdev->subordinate);
 
 	/*
 	 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe

@@ -799,17 +779,15 @@ static int alloc_pcie_link_state(struct pci_dev *pdev)
 	    !pdev->bus->parent->self) {
 		pdev->root = pdev;
 	} else {
-		if (!pdev->bus->parent->self) {
-			kfree(link);
+		if (!pdev->bus->parent->self)
 			return -1;
-		}
 
 		pdev->parent = pdev->bus->parent->self;
 		pdev->root = pdev->parent->root;
 	}
 
+	pdev->downstream = pci_function_0(pdev->subordinate);
 	list_add(&pdev->sibling, &pdev_link_list);
-	pdev->link_state = link;
 	return 0;
 }

@@ -828,13 +806,13 @@ static void pcie_aspm_update_sysfs_visibility(struct pci_dev *pdev)
  */
 void pcie_aspm_init_link_state(struct pci_dev *pdev)
 {
-	struct pcie_link_state *link;
 	int blacklist = !!pcie_aspm_sanity_check(pdev);
 
 	if (!aspm_support_enabled)
 		return;
 
-	if (pdev->link_state)
+	if (pdev->downstream)
+	    /* Initialised already */
 		return;
 
 	/*

@@ -855,20 +833,18 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev)
 		goto out;
 
 	mutex_lock(&aspm_lock);
-	if (!(alloc_pcie_link_state(pdev)))
+	if (alloc_pcie_link_state(pdev))
 		goto unlock;
 
-	link = pdev->link_state;
-
 	/*
 	 * Setup initial ASPM state. Note that we need to configure
 	 * upstream links also because capable state of them can be
 	 * update through pcie_aspm_cap_init().
 	 */
-	pcie_aspm_cap_init(link->pdev, blacklist);
+	pcie_aspm_cap_init(pdev, blacklist);
 
 	/* Setup initial Clock PM state */
-	pcie_clkpm_cap_init(link->pdev, blacklist);
+	pcie_clkpm_cap_init(pdev, blacklist);
 
 	/*
 	 * At this stage drivers haven't had an opportunity to change the

@@ -880,8 +856,8 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev)
 	 */
 	if (aspm_policy != POLICY_POWERSAVE &&
 	    aspm_policy != POLICY_POWER_SUPERSAVE) {
-		pcie_config_aspm_path(link->pdev);
-		pcie_set_clkpm(link->pdev, policy_to_clkpm_state(link->pdev));
+		pcie_config_aspm_path(pdev);
+		pcie_set_clkpm(pdev, policy_to_clkpm_state(pdev));
 	}
 
 	pcie_aspm_update_sysfs_visibility(pdev);

@@ -921,9 +897,8 @@ static void pcie_update_aspm_capable(struct pci_dev *root)
 void pcie_aspm_exit_link_state(struct pci_dev *pdev)
 {
 	struct pci_dev *parent = pdev->bus->self;
-	struct pcie_link_state *link, *root, *parent_link;
 
-	if (!parent || !parent->link_state)
+	if (!parent)
 		return;
 
 	down_read(&pci_bus_sem);

@@ -935,20 +910,16 @@ void pcie_aspm_exit_link_state(struct pci_dev *pdev)
 	if (!list_empty(&parent->subordinate->devices))
 		goto out;
 
-	link = parent->link_state;
-	root = link->pdev->root->link_state;
-	parent_link = link->pdev->parent->link_state;
-
 	/* All functions are removed, so just disable ASPM for the link */
 	pcie_config_aspm_link(parent, 0);
-	list_del(&link->pdev->sibling);
+	list_del(&parent->sibling);
 	/* Clock PM is for endpoint device */
 	free_link_state(parent);
 
 	/* Recheck latencies and configure upstream links */
-	if (parent_link) {
-		pcie_update_aspm_capable(root->pdev);
-		pcie_config_aspm_path(parent_link->pdev);
+	if (parent->parent) {
+		pcie_update_aspm_capable(parent->root);
+		pcie_config_aspm_path(parent->parent);
 	}
 out:
 	mutex_unlock(&aspm_lock);

@@ -1008,9 +979,8 @@ static struct pci_dev *pcie_aspm_get_link(struct pci_dev *pdev)
 static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
 {
 	struct pci_dev *bridge = pcie_aspm_get_link(pdev);
-	struct pcie_link_state *link = bridge->link_state;
 
-	if (!link)
+	if (!bridge)
 		return -EINVAL;
 	/*
 	 * A driver requested that ASPM be disabled on this device, but

@@ -1042,12 +1012,12 @@ static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
 	if (state & PCIE_LINK_STATE_L1_2_PCIPM)
 		bridge->aspm_disable |= ASPM_STATE_L1_2_PCIPM;
 
-	pcie_config_aspm_link(link->pdev, policy_to_aspm_state(link->pdev));
+	pcie_config_aspm_link(bridge, policy_to_aspm_state(bridge));
 
-	if (state & PCIE_LINK_STATE_CLKPM) {
+	if (state & PCIE_LINK_STATE_CLKPM)
 		bridge->clkpm_disable = 1;
-	}
-	pcie_set_clkpm(link->pdev, policy_to_clkpm_state(link->pdev));
+
+	pcie_set_clkpm(bridge, policy_to_clkpm_state(bridge));
 	mutex_unlock(&aspm_lock);
 	if (sem)
 		up_read(&pci_bus_sem);

@@ -1150,9 +1120,7 @@ static ssize_t aspm_attr_store_common(struct device *dev,
 				      struct device_attribute *attr,
 				      const char *buf, size_t len, u8 state)
 {
-	struct pci_dev *pdev = to_pci_dev(dev);
-	struct pci_dev *bridge = pcie_aspm_get_link(pdev);
-	struct pcie_link_state *link = bridge->link_state;
+	struct pci_dev *bridge = pcie_aspm_get_link(to_pci_dev(dev));
 	bool state_enable;
 
 	if (strtobool(buf, &state_enable) < 0)

@@ -1169,7 +1137,7 @@ static ssize_t aspm_attr_store_common(struct device *dev,
 	} else
 		bridge->aspm_disable |= state;
 
-	pcie_config_aspm_link(link->pdev, policy_to_aspm_state(link->pdev));
+	pcie_config_aspm_link(bridge, policy_to_aspm_state(bridge));
 
 	mutex_unlock(&aspm_lock);
 	up_read(&pci_bus_sem);

@@ -1207,7 +1175,6 @@ static ssize_t clkpm_store(struct device *dev,
 			   const char *buf, size_t len)
 {
 	struct pci_dev *pdev = pcie_aspm_get_link(to_pci_dev(dev));
-	struct pcie_link_state *link = pdev->link_state;
 	bool state_enable;
 
 	if (strtobool(buf, &state_enable) < 0)

@@ -1216,8 +1183,8 @@ static ssize_t clkpm_store(struct device *dev,
 	down_read(&pci_bus_sem);
 	mutex_lock(&aspm_lock);
 
-	link->pdev->clkpm_disable = !state_enable;
-	pcie_set_clkpm(link->pdev, policy_to_clkpm_state(link->pdev));
+	pdev->clkpm_disable = !state_enable;
+	pcie_set_clkpm(pdev, policy_to_clkpm_state(pdev));
 
 	mutex_unlock(&aspm_lock);
 	up_read(&pci_bus_sem);

Signature · 6 lines

2.18.4

_______________________________________________
Linux-kernel-mentees mailing list
[email protected]
https://lists.linuxfoundation.org/mailman/listinfo/linux-kernel-mentees

Saheed O. Bolarinwa

author

2020-08-22 21:04 UTC #23 lore raw

RFC PATCH v5 23/23 PCI: Remove struct pcie_link_state

In reply to Saheed O. Bolarinwa

- Remove free_link_state() and all calls to it
- Remove pci_dev.link_state
- Remove remaining referenced to struct pcie_link_state
- Remove struct pcie_link_state

Signed-off-by Saheed O. Bolarinwa <[email protected]>

---
 drivers/pci/pcie/aspm.c | 15 +--------------
 include/linux/pci.h     |  2 --
 2 files changed, 1 insertion(+), 16 deletions(-)

drivers/pci/pcie/aspm.c +1 ~~-14~~

index 2fc2b958e6d2..0330b10faa29 100644
@@ -41,9 +41,6 @@
 #define ASPM_STATE_ALL		(ASPM_STATE_L0S | ASPM_STATE_L1 |	\
 				 ASPM_STATE_L1SS)
 
-struct pcie_link_state {
-};
-
 static int aspm_disabled, aspm_force;
 static bool aspm_support_enabled = true;
 static DEFINE_MUTEX(aspm_lock);

@@ -722,12 +719,6 @@ static void pcie_config_aspm_path(struct pci_dev *pdev)
 	}
 }
 
-static void free_link_state(struct pci_dev *pdev)
-{
-	pdev->link_state = NULL;
-	kfree(pdev->link_state);
-}
-
 static int pcie_aspm_sanity_check(struct pci_dev *pdev)
 {
 	struct pci_dev *child;

@@ -913,8 +904,6 @@ void pcie_aspm_exit_link_state(struct pci_dev *pdev)
 	/* All functions are removed, so just disable ASPM for the link */
 	pcie_config_aspm_link(parent, 0);
 	list_del(&parent->sibling);
-	/* Clock PM is for endpoint device */
-	free_link_state(parent);
 
 	/* Recheck latencies and configure upstream links */
 	if (parent->parent) {

@@ -945,9 +934,7 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev)
 
 void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
 {
-	struct pcie_link_state *link = pdev->link_state;
-
-	if (aspm_disabled || !link)
+	if (aspm_disabled || !pdev)
 		return;
 
 	if (aspm_policy != POLICY_POWERSAVE &&

include/linux/pci.h +0 -2

index 1daf5fe0b913..b0742ee8ebd2 100644
@@ -300,7 +300,6 @@ struct pci_cap_saved_state {
 };
 
 struct irq_affinity;
-struct pcie_link_state;
 struct pci_vpd;
 struct pci_sriov;
 struct pci_p2pdma;

@@ -383,7 +382,6 @@ struct pci_dev {
 	u32		lnkcap;		/* Link Capabilities */
 
 #ifdef CONFIG_PCIEASPM
-	struct pcie_link_state	*link_state;	/* ASPM link state */
 	unsigned int	ltr_path:1;	/* Latency Tolerance Reporting
 					   supported from root to here */
 	int		l1ss_cap_ptr;	/* L1SS cap ptr, 0 if not supported */

Signature · 6 lines

2.18.4

_______________________________________________
Linux-kernel-mentees mailing list
[email protected]
https://lists.linuxfoundation.org/mailman/listinfo/linux-kernel-mentees